JPS607759A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS607759A JPS607759A JP58115182A JP11518283A JPS607759A JP S607759 A JPS607759 A JP S607759A JP 58115182 A JP58115182 A JP 58115182A JP 11518283 A JP11518283 A JP 11518283A JP S607759 A JPS607759 A JP S607759A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- base plate
- plate
- base board
- external terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、部品点数の削減、製造工程の簡略化を図った
中容間の電力用半導体装置の製造装量に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an intermediate power semiconductor device that reduces the number of parts and simplifies the manufacturing process.
［発明の技術的背景とその問題点］
ダイオード、リイリスタ鋳の少数の半導体素子を一つの
パッケージ内に組込み、所定の回路を形成したいわゆる
複合半導イホ装ＩＩ？７は、電源回路等を構成する場合
等に配線のｎｓ＋略化、組立工数の低減等を図る目的で
多用されている。[Technical background of the invention and its problems] What is the so-called composite semiconductor device II, in which a small number of semiconductor elements such as diodes and relay transistors are incorporated into one package to form a predetermined circuit? 7 is frequently used for the purpose of simplifying the wiring and reducing the number of assembly steps when configuring a power supply circuit or the like.
この複合半導体装置の構成の一例を第１図に示す。An example of the configuration of this composite semiconductor device is shown in FIG.
同図において、ベース板１には、尋電性金屈扱２上に絶
縁層３を介して所定の導電回路パターン４が形成され、
この伝導回路パターン４上に半導体ペレット５が、また
このペレッ１−５上には、外部端子６がそれぞれソルダ
切により固着される。In the figure, a predetermined conductive circuit pattern 4 is formed on a base plate 1 with an insulating layer 3 interposed on a conductive gold plate 2.
A semiconductor pellet 5 is fixed on the conductive circuit pattern 4, and an external terminal 6 is fixed on the pellet 1-5 by soldering.
また、分離された島状の導電回路パターン４は、所定の
回路を構成するために内部接続端子７により接続される
。Further, the separated island-shaped conductive circuit patterns 4 are connected by internal connection terminals 7 to form a predetermined circuit.
その後、必要に応じ所定のパッケージに収められ、樹脂
封止されて完成品とするが、上記の装置には以下のよう
な問題点がある。Thereafter, it is placed in a predetermined package as required and sealed with resin to produce a finished product, but the above-mentioned device has the following problems.
すなわち、外部端子６、内部接続端子７等部品点数が多
く、したがってその組立工数がかかり、またそれぞれそ
別個独立した小部品が多いため取扱いに不便である等の
問題点があった。That is, there are problems such as a large number of parts such as external terminals 6 and internal connection terminals 7, which requires a lot of man-hours to assemble, and also inconvenience in handling because there are many separate small parts.
［発明の目的］
本発明は、上記の小情に↓Ｊづぎなされたもので、部品
点数を削減し、組立、取扱いに便利な半導体装置の製造
方法を提供゛りることを目的とする。[Purpose of the Invention] The present invention was made in response to the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that reduces the number of parts and is convenient for assembly and handling. .
［発明の概要］
本発明は、所定の回路の導体パターンを右りるベース板
上にこのベース板の主面に対して直角方向に外部端子を
導出する半導体装ｆｆｆｉにおいて、前記外部端子を互
に連結枠によって一体的に連結した外部端子プレー１〜
でｔｌＭ成し、このプレートを前記ベース板上に、また
このベース板の所定箇所に半導体ペレットをそれぞれ載
置固定させて所定の回路を形成しただ後、前記プレー１
〜の連結枠を切断し、それぞれ独立した外部端子とする
ことを特徴とする半導体装置の製造方法であって、外部
端子を一枚のプレー１−で形成し、これを最終工程にお
いて個々に切離するようにし、途中工程での取扱いの便
、部品点数の削減等を図つｌ〔ものである、「発明の実
施例」
第２図、第３図は、ベース板および外部端子プレー１〜
の平面図である。[Summary of the Invention] The present invention provides a semiconductor device fffi in which external terminals are led out in a direction perpendicular to the main surface of the base plate on a base plate on which a conductor pattern of a predetermined circuit is arranged, and in which the external terminals are mutually connected. External terminal plate 1~ which is integrally connected by a connecting frame to
After forming a predetermined circuit by placing and fixing this plate on the base plate and placing and fixing semiconductor pellets at predetermined locations on the base plate, the plate 1 is
A method for manufacturing a semiconductor device, characterized in that the connecting frames of ~ are cut to form independent external terminals, the external terminals are formed from one piece of play 1-, and this is individually cut in the final process. Embodiments of the Invention Figures 2 and 3 show the base plate and external terminal plates 1 to 1.
FIG.
りなわち、ベース１０上は絶縁ＩＭ １１を介して所定
の導体回路パターン１２が形成される。一方、外部端子
プレー１〜１３は、外部端子１４が連結枠１５によって
互に一１木的に接続された形状にあらかじめプレス等に
にって打抜かれで形成される。That is, a predetermined conductive circuit pattern 12 is formed on the base 10 via the insulating IM 11. On the other hand, the external terminal plates 1 to 13 are formed in advance by punching with a press or the like into a shape in which the external terminals 14 are connected to each other in a monolithic manner by the connecting frame 15.
次に、上記外部端子プレー１−１３をベース板１０上の
導体回路パターン１２に小ね含Ｕ、さらにこの外部端子
プレー］〜１３上の位置に第４図に示Ｊようにダイオー
ドチップ１Ｇ、サイリスタチップ１７、導電性ダミーチ
ップ′１８を載せる。Next, the external terminal plate 1-13 is attached to the conductor circuit pattern 12 on the base plate 10, and a diode chip 1G is placed on the external terminal plate 1-13 as shown in FIG. A thyristor chip 17 and a conductive dummy chip '18 are mounted.
まＩＣ１これらのチップ１６．１７、および１８−りに
導電性板材に３」；つて形成したＩＦ極側内部端子１９
、負極側内部端子２０Ｊ−５よびゲート内部端子２１を
それぞれ所定位置にに治工具等を用いて載置し、導体回
路パターン１２と外部ｆｌｙ、；子プレー１〜１３の間
および各チップの両主面に介在させたソルダを加熱溶融
させ、それらを一体向に固るさＵる。Moreover, the IC1 chips 16, 17, and 18- have an IF pole side internal terminal 19 formed on a conductive plate material.
, the negative electrode side internal terminal 20J-5 and the gate internal terminal 21 are placed in their respective predetermined positions using a jig or the like, and the conductor circuit pattern 12 and the external fly; The solder interposed on the main surface is heated and melted to solidify them in one direction.
なお、第４図に示す実施例はフライ小イリングダイオー
ド付単相全波混合ブリッジ回路であるが、特にこの回路
に限定されるものではない。Although the embodiment shown in FIG. 4 is a single-phase full-wave mixed bridge circuit with a small Frye ring diode, the present invention is not limited to this circuit.
その後、連結枠１５の鎖線位置をプレス等を用いて切断
し、個々の外部端子１−４とする。Thereafter, the connecting frame 15 is cut along the chain line using a press or the like to form individual external terminals 1-4.
次いで、外部端子１／ｌをそれぞれベース板１０の主面
に対して略直角に立ち上げるように折り曲げ、所定のパ
ッケージを被せて、ざらに必要に応じ樹脂月止し、完成
品とりる。Next, each of the external terminals 1/l is bent so as to stand up substantially at right angles to the main surface of the base plate 10, covered with a predetermined package, and roughly sealed with resin as required, to prepare a finished product.
なお、上記外部端子プレー１−１３から各外部端子１４
を切離Ｊ工程は、それら外部端子１４を折り曲げた後に
行っても良い。In addition, each external terminal 14 from the external terminal play 1-13
The cutting step J may be performed after the external terminals 14 are bent.
［発明の効果］
本発明は上記の、ように外部端子を一枚のプレート上に
一体的に形成し、最終工程において各端子に分離Ｊ−る
にうにしたので、組立途上の部品点数が減少し、かつ、
各部の位置合せも容易になると共に半導体チップ、各端
子、各端子のソルダ付り等の作業が平面的に行えるうに
なるので箸しくその作業性が向上しソルダ（ｌりに対づ
−る信頼性の向上、作業時間の短縮に伴う製品１１ｒｉ
１１１１ｉの低減等を図り得る。[Effects of the Invention] In the present invention, as described above, the external terminals are integrally formed on one plate and separated into each terminal in the final process, so the number of parts during assembly is reduced. And,
It becomes easier to align each part, and work such as soldering the semiconductor chip, each terminal, and each terminal can be done on a flat surface. Product 11ri with improved performance and reduced work time
1111i can be reduced.
第１図は、従来の半導体装置の構成の一例を示す分解組
立図、第２図ないし第４図は、本考案に係わる半導体装
置の製造方法を示す図であって第２図は、ベース板の平
面図、第３図は、外部端子プレートの平面図、第４図は
、上記半導体装置の斜視図である。
１０・・・ベース板
１１・・・絶縁層
１２・・・導体回路パターン
１３・・・外部端子プレーｉ〜
１４・・・外部端子
１５・・・連結枠
１６・・・ダイ′Ａ−１〜チップ
１７・・・サイリスクチップ
１８・・・導電性ダミーデツプ
１９・・・正極側内部端子
２０・・・負極側内部端子
２１・・・内部端子
出願代理人 弁■！Ｉ１士 菊 池 五 部第 ２ 図
／２
弗 ３ 図FIG. 1 is an exploded view showing an example of the configuration of a conventional semiconductor device, and FIGS. 2 to 4 are views showing a method of manufacturing a semiconductor device according to the present invention, in which FIG. 3 is a plan view of the external terminal plate, and FIG. 4 is a perspective view of the semiconductor device. 10...Base plate 11...Insulating layer 12...Conductor circuit pattern 13...External terminal play i~ 14...External terminal 15...Connection frame 16...Die 'A-1~ Chip 17...Sirisk chip 18...Conductive dummy depth 19...Positive internal terminal 20...Negative internal terminal 21...Internal terminal application agent Valve ■! I1 Master Kikuchi Part 5 Part 2 Diagram/2 弗 3 Diagram
Claims (1)
のベース板の主面に対して直角方向にタト部端子を導出
覆る半導体装置おいて、前記外部端子を互に連結枠によ
って一体的に連結した外部端子プレートで形成し、この
プレートを前記ベース板上に、またこのベース板の所定
箇所に半導体ペレッ１−をそれぞれ載置固着さＵて所定
の回路を形成した後、前記プレー１〜の連結枠を切断し
、そｆしぞれ独立した外部端子とすることを特徴とする
半導体装置の製造方法。In a semiconductor device in which a base plate having a conductor circuit pattern of a predetermined circuit is covered with lead-out terminals in a direction perpendicular to the main surface of the base plate, the external terminals are integrally connected to each other by a connecting frame. After forming a predetermined circuit by placing and fixing this plate on the base plate and at a predetermined location of the base plate, connect the plates 1 to 1. A method of manufacturing a semiconductor device, which comprises cutting a frame to form independent external terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115182A JPS607759A (en) | 1983-06-28 | 1983-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115182A JPS607759A (en) | 1983-06-28 | 1983-06-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607759A true JPS607759A (en) | 1985-01-16 |
Family
ID=14656382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58115182A Pending JPS607759A (en) | 1983-06-28 | 1983-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607759A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001033632A1 (en) * | 1999-11-01 | 2001-05-10 | General Semiconductor, Inc. | Planar hybrid diode rectifier bridge |
| CN114121845A (en) * | 2020-09-01 | 2022-03-01 | Jmj韩国株式会社 | Semiconductor package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4922782A (en) * | 1972-05-11 | 1974-02-28 | ||
| JPS5114727B1 (en) * | 1970-08-24 | 1976-05-12 | ||
| JPS5757552B2 (en) * | 1973-05-07 | 1982-12-04 | Dart Ind Inc |
-
1983
- 1983-06-28 JP JP58115182A patent/JPS607759A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5114727B1 (en) * | 1970-08-24 | 1976-05-12 | ||
| JPS4922782A (en) * | 1972-05-11 | 1974-02-28 | ||
| JPS5757552B2 (en) * | 1973-05-07 | 1982-12-04 | Dart Ind Inc |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001033632A1 (en) * | 1999-11-01 | 2001-05-10 | General Semiconductor, Inc. | Planar hybrid diode rectifier bridge |
| US6387730B2 (en) | 1999-11-01 | 2002-05-14 | General Semiconductor, Inc. | Hybrid S.C. devices and method of manufacture thereof |
| CN1327521C (en) * | 1999-11-01 | 2007-07-18 | 通用半导体公司 | Planar hybrid diode rectifier bridge |
| CN114121845A (en) * | 2020-09-01 | 2022-03-01 | Jmj韩国株式会社 | Semiconductor package |
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