JPS607575A - Fixed point fast fourier transform system - Google Patents

Abstract

PURPOSE:To perform a fast Fourier transform operation at high precision by providing a signal bit into each data flowing between operators to show whether a right shift is carried out with a butterfly operation and then adding the data containing the control informaton. CONSTITUTION:The input data containing the signal data of 1 bit is multiplied by the contents of an ROM6 storing a constant by a multiplier 7 and in a fixed point style. The result of this multiplication is delivered to a data register 8. The data is treated as the data excluding the signal bits for the fixed point addition of an adder 9. A controller 15 controls a switch 11. The output of the adder 9 is delivered to the register 8 and a register 12 with the intermediate result and the final result of the addition respectively. The contents of the register 12 are stored in an output data buffer 14. This information includes the presence or absence of a digit overflow as well as the shifting frequency so far.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to fast Fourier transform (hereinafter referred to as FFT operation).

) method, and particularly relates to an FFT calculation method that enables highly accurate and high-speed processing with a small amount of hardware.

[Background of the invention]

In the fields of signal processing and image processing, FFT calculations are often used to examine frequency characteristics and to calculate correlation calculations at high speed. In particular, when it is desired to repeatedly execute F'FT operations at high speed, processors are coupled in a pipeline manner. An example of this type of configuration is
There is a system described in Japanese Patent No. 22982. 1st
The figure shows the part of this system related to FFT calculation.

Conventionally, there have been two types of data representation formats when performing an FFT operation using an apparatus having the configuration shown in FIG. 1: a floating point format and a fixed point format. However, in the case of floating point format, the calculation contents are complicated, and the amount of hardware in the calculation unit 2 shown in FIG. There was a problem in that it was large and expensive.

Furthermore, in the case of fixed-point format, there is a problem with calculation accuracy.

This case will be explained below. Figure 2 shows the flow of the FFT operation when the number of data is 2'' = 8 (XO-X7). Figure 3 shows the butterfly operation that is a component of the FFT operation. Contents of the butterfly operation Here, X and y are the input values of the butterfly operation, and X and Y are the same output values.W represents a complex number with an absolute value of 1.

However, when performing an F F T operation in a fixed-point format, there is a possibility that the digits of the operation result will be mixed up, and the accuracy of the operation result will be significantly reduced. Therefore, in order to prevent digit confusion, the calculation of the following equation, which includes a 1-bit right shift operation, must be performed instead of the calculation of equation (1).

In this case, overflow will never occur. As a result, N=
If you perform an FFT operation in fixed-point format on a point in 2, the data is shifted to the right by 1 bit in each stage of the K-stage butterfly operation, and if you divide by 2, the data length in fixed-point format is valid. Therefore, there was a problem in that the accuracy of the FFT calculation result decreased.

However, the diblock floating method is conventionally known as a method to avoid the problem of reduced precision in fixed-point FFT calculations (for example, Jnl-digital Sig
nal Processing JA, V, Open
Beim,.

et al., Prentice-hall, I
NC1975) oThis method takes a fixed-point format as a data format, but formulas (1) and (2) are used as appropriate for the butterfly calculation content.In other words, a certain stage of butterfly calculation is converted into formula (1). However, if a digit error occurs in the set of input data for a butterfly operation, the butterfly operation at that stage is recalculated from the beginning using equation (2). In this case, the difference in digits will never occur again during the calculation process.

With this block floating method, the number of digits of data is adjusted as and when necessary according to the nature of the input data, so if you scale the data appropriately in advance, you can always make effective use of the data length in fixed-point format. As a result, the accuracy in the p1 result is also the same as above.

However, in the block floating method, the butterfly operation is corrected when a digit error occurs, but in the pipeline type configuration shown in Figure 1, this is a reverse flow of data! 17. Timing control of the calculations in each stage of FFT is extremely complicated and difficult, and at the same time, certain input data in the FFT calculation is
) The number of shifts performed by the formula depends on the nature of the input data, so the F
There is a problem that a difference in relative scale may occur between the FT calculation results.

[Purpose of the invention]

An object of the present invention is to provide an FFT calculation method that solves the above-mentioned problems in the conventional pipeline type FFT calculation method and makes it possible to perform FFT calculations using fixed-point data format with higher precision than in the past. There is a particular thing.

[Summary of the invention]

To achieve the above object, in the present invention, in an FFT arithmetic device in which arithmetic units are coupled in a pipeline type, a right shift is performed in the individual data flowing between the arithmetic units in the butterfly operation immediately before outputting the data as a result. The feature is that a signal bit is provided to indicate whether the data is valid or not, and data containing control information is added to each data string that is a unit of FFT calculation.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows the contents of data stored in the data buffer 1, which consists of N pieces of data 61 and one piece of control information 62, assuming that %p, the length of the data string 9 to be subjected to FFT is N=2.

Figure 5 shows the content of each data 61, where the data length is n bits, the first bit is used as a signal bit 51, and the remaining n-1 bits are valid data 52 expressed in fixed-point format. .

FIG. 4 shows the FFT calculation unit 2 shown in FIG. 1, 3 is an input data buffer, 4 is a switch for switching the data flow, 5 is a shifter for right-shifting data by 1 bit according to the signal focus, and 6 is a read-only memory that stores constants, 7 is a multiplier, 8 is a data register, 9 is an adder, 10 is an overflow flag for the addition result, 11 is a switch similar to 4, and 12 is a signal bit for the addition result. Additional registers 13 are registers for storing control information, and 14 are output data buffers for storing output results. 15 is a controller that controls these components by a microprogram.

The operation of this device will be explained below.

In addition, in this example, the fixed point data is -1 and 1.
The explanation will be given assuming that the value is between.

First, the meaning of the signal bit 51 in FIG. 5 is that when it is 0, it indicates that the data including this signal bit has not been shifted to the right in the previous butterfly operation, and when it is 1, it indicates that it has been shifted to the right. Still, FIG. 7 shows the structure of the control information 62 shown in FIG. 6, and shows how many times the N pieces of data to which this control information has been attached have been shifted during the Flli"T operation up to that point. It consists of a shift count 71, and a swift flag 72 indicating whether right shift was performed at least once in the butterfly operation at the immediately previous stage.

Prior to all calculations, the controller 15 moves the control information in the input data buffer 3 to the register 13, and reads the shift flag at this time.

When the shift flag is O, Fl! ”It means that no right shift occurred even once in the immediately preceding stage in the T operation,
In that case, there is no need to align the digits of the input data in the currently targeted stage. Therefore, controller 1
5, switch 4 is switched to bypass shifter 5. When the shift flag is still 1, it is necessary to shift the input data by 1 bit to the right according to the signal bit attached to each data, and the controller 15 switches off the switch 4 so that it is connected to the shifter 5. exchange. After these switches are completed, the shift flag of the control information in the register 13 is cleared to prepare for the next process.

Shifter 5 shifts the data to the right by 1 bit when the signal bit of the input data is 0, and clears the signal bit without performing the shift when the signal bit is 1, and inputs the result to multiplier 7. This operation aligns the digits of the input data.

The multiplier 7 is connected to a ROM 6 in which input data and constants are stored.
Multiplication is performed in fixed-point format with the contents of , and the result is output to the data register 8.

In the fixed-point addition by the adder 9, data is treated as data of signal bits less than (n-1) bits. If the result of addition is (n-1) bit data, an overflow flag 10 is set, and at the same time, the addition result is shifted one bit to the right/backward and hot water is dispensed. Controller 1
5 controls a switch 11 to store the output of the adder 9 in the data register 8 if the addition result is an intermediate result, and to store the output in the register 12 if the result is the final result of a calculation.

At this time, when the adder 9 calculates the intermediate result to be stored in the data register 8, overflow cannot occur. In other words, the intermediate result according to equation (1) is the term WY, but if IYI<1, IWY l≦IWI・IYI≦IYI<1 (3
).

Therefore, the data stored in the data register 8 always has a signal bit of 0.

The data output as the final result of the butterfly operation is once stored in the register 12, and the first bit is replaced with the contents of the overflow flag 10 (1 when an overflow occurs, otherwise 1), and then the output data buffer 14 is stored in

In addition, the contents of the overflow flag 10 are compared with the contents of the register 13 every time the result of the adder 9 is output, and only when the overflow flag 10 is 1 and the shift flag is 00, the number of shifts is increased by 1. Increase and set the shift flag to 1. In other cases, the contents of register 13 remain unchanged. By performing the necessary operations, it is possible to correctly set the presence or absence of a digit error, which is control information to be transmitted to the arithmetic unit in the next stage, and the number of shifts performed up to the current stage.

As described above, according to this embodiment, by using a fixed-point data format in an FFT arithmetic unit in which arithmetic units are combined in a pipeline type, the hardware can be greatly simplified and processing speed can be increased. By making the most effective use of the data length in decimal point format, it has the effect of enabling high-precision calculations.

〔Effect of the invention〕

As described above, according to the present invention, in a fixed-point FFT arithmetic device in which arithmetic units are coupled in a pipeline type, the data length in the fixed-point data format can be used most effectively. This has the effect of making it possible to do so.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram of a pipeline type FFT calculation device.
Figure 2 is a diagram showing the general flow of FFT calculation, and Figure 3 is a diagram showing the general flow of FFT calculation.
FIG. 4 is a diagram showing the configuration of an embodiment of the FFT calculator according to the present invention; FIG. 5 is a diagram showing the data structure to be subjected to FFT calculation;
FIG. 6 is a diagram showing the data structure that is the unit of FFT calculation,
FIG. 7 is a diagram showing the contents of the control information. l...Data buffer, 2...Butterfly calculator. y 1 Mouth 2nd figure 32 14- concave) 5 5 Rero 〕U Otsu figure

Claims (1)

[Scope of Claims] 1. In a fast Fourier transform device in which fixed-point arithmetic units are coupled in a pipeline type, control for controlling the digit shift of each data into a data string that is a unit of fast Fourier transform from a plurality of data. A fixed-point high-speed 7-bit conversion method characterized in that a signal bit indicating the history of digit movement of each data is added to each data in order to add information and make it correspond to the control information. 2. The control information includes information indicating the number of digit shifts performed in the data string up to the current fixed-point operation, and information indicating whether digit shift was performed for at least one piece of data in the immediately preceding fixed-point operation. The fixed-point fast Fourier transform method according to claim 1, which is characterized by all the features derived from flag information. 3. The above-mentioned signal bit indicates whether or not the data including the bit has undergone digit shift in the fixed-point operation immediately before the current time, and the bit is referred to when executing the current fixed-point operation on the above-mentioned data. The fixed-point fast Fourier transform method according to claim 1 or 2, characterized in that whether or not to shift the digits of data is specified by the flag information.