JPH06282418A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To use the output result of a multiplier as an input to the multiplier immediately in a next machine cycle. CONSTITUTION:In the arithmetic unit which performs data transfer, multiplication, and ALU arithmetic by a pipeline system by cascading the multiplier 1 having two input and output latches 4 and a data ALU circuit 5 having two inputs, the output latch 4 of the multiplier 1 is connected to a selector 7 for one input of the data ALU circuit 5 and also connected to selectors 2 and 3 for two inputs of the multiplier 1, and a register file 8 and the output latch 4 of the multiplier 1 can be selected as the input to the multiplier 1. Then when continuous arithmetic processing for a three-term product, a four-term product, a five-term product, etc., is performed, the output of the output latch 4 can be supplied directly to the input of the multiplier 1 through the selectors 2 and 3 and the number of execution steps can greatly be decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a processor for processing electric signals, and more particularly to a processor for digital signal processing such as audio coding and image coding, that is, a digital signal processor (hereinafter referred to as DSP). It refers to)).

[0002]

2. Description of the Related Art The main (most frequently appearing) processing in digital signal processing, including coding and filtering of voice and images, is a sum of products operation. FIG. 3 shows a typical configuration example of the central part of a conventional DSP arithmetic circuit. In this example, two data buses are provided, and two data can be transferred between the memory 10 and the register file 8 at the same time. As shown in the figure, a data ALU having two inputs in order to perform the multiply-accumulate operation at high speed.
Besides the circuit (OMPY) 5, two input and output latches 4
Has a dedicated multiplier (OMLT) 1 equipped with
And ALU circuits 5 are connected in cascade to perform data transfer, multiplication, and ALU operation by a pipeline method.

The two inputs of the data ALU circuit 5 have selectors 6 and 7, respectively, the output of which is sent to the register file 8. The two inputs of the multiplier 1 also have selectors 2 and 3, respectively. The output from the output latch 4 of the multiplier 1 is sent to the data AL via the selector 7.
It is sent to one input of the U circuit 5. In the configuration shown in FIG. 3, xn and yn (n = 1, 2,
3 ..., n), the sum of products operation x1 × y1 + x2 × y2
The procedure for executing + ... xN × yN and returning the result to the memory 10 is as follows. However, one line corresponds to one step.

R1 = x1; R2 = y1; (1.1) OMLT = R1 × R2; R1 = x2; R2 = y2; (1.2) For n = 3, ..., N, Repeat one step. R3 = R3 + OMPY; OMLT = R1 × R2; R1 = xn; R2 = yn; (1.3) R3 = R3 + OMPY; OMLT = R1 × R2; (1.4) R3 = R3 + OMPY; (1.5) R3 → MEM (1.6) That is, (N + 3) steps are required.

Here, = indicates the transfer of values to the registers R1, R2, ... Of the register file 8, × indicates the operation by the multiplier, and → indicates the memory (MEM) of the operation result in the register. Each means transfer to 10. In the above equation (1.3), x (n-2) is stored in the register R3.
The result of xy (n-2) is added, and at the same time x (n-1)
Xy (n-1) multiplication is performed, and at the same time, xn
And yn have been transferred from the memory 10. This is DS
It is a flow of pipeline processing in the product-sum operation on P.

The above product-sum operation x1 × y1 + x2 × y2 +
... In the processing of xN × yN, since the multiplication occurs N times, it means that the number of steps is N order, so that the multiplier 1 always operates except the overhead at the beginning and end of the processing. It means that the processing is being performed without waste. As is clear from the above description,
In the circuit configuration of the conventional DSP shown in FIG. 3, the product-sum operation can be processed at high speed by the pipeline method.

[0007]

However, not only the product-sum operation but also the ternary product,
Many operations such as the quaternary product that continuously use the multiplier without using the ALU circuit also appear. The conventional configuration as shown in FIG. 3 is not always effective when performing such an operation. Because the output latch of the multiplier is not directly connected to the input of the multiplier, the multiplication result cannot be immediately used as the multiplication target in the next machine cycle, and the machine cycle of transfer only between registers is inevitable. Because it is.

With respect to this point, D of the configuration shown in FIG.
The case of SP will be described as an example. In order to perform an operation in which N ternary products of xn, yn, and zn (n = 1, 2, 3, ..., N) stored in the memory are continuously calculated and the result is returned to the memory, , Requires the following steps: However, one line corresponds to one step. R1 = x1; R2 = y1; (2.1) OMLT = R1 × R2; R2 = z1; (2.2) R1 ← OMLT (2.3) n = 1, 2, 3, ..., N- Repeat the following 3 steps for 1.

OMLT = R1 × R2; R1 = x (n + 1); R2 = y (n + 1) (2.4) R1 ← OMLT; OMLT = R1 × R2; R2 = z (n + 1) (2.5) R1 → MEM; R1 ← OMLT (2.6) OMLT = R1 × R2; (2.7) R1 ← OMLT; (2.8) R1 → MEM; (2.9) That is, (3N + 3) steps are required.

Here, = indicates the transfer of the value to the register, ←
Means transfer of a value to the register via the data ALU, × means operation by the multiplier, and → means transfer of the operation result in the register to the memory. In this example, since the multiplication occurs 2N times, if the processing can be executed without waste, the number of steps on the order of 2N should be sufficient.
However, since N + 2 steps appear in which only the data is transferred without using the multiplier,
A step count of 3N order is required.

As described above, in the conventional DSP,
When performing an arithmetic operation that continuously uses only a multiplier without using an ALU circuit, such as a ternary product of continuous data, a step in which the multiplier cannot be used, that is, a step only in which data is transferred occurs. Therefore, there is a problem that the calculation efficiency of the entire processor is deteriorated.

[0012]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is an arithmetic unit for performing high-speed arithmetic processing based on a pipeline system by connecting multipliers and ALU circuits in cascade like a DSP. In the above, a path is provided in which the output of the multiplier can be directly input to the input of this multiplier, and the output result of the multiplier can be immediately input to the multiplier in the next machine cycle. .

[0013]

By applying the present invention, the output of the multiplier can be changed to the following when performing an operation such as a triplet product or a quadratic product that continuously uses only the multiplier without using the ALU circuit. Since it can be used as a multiplier input immediately in a machine cycle, a step only for data transfer does not appear and an increase in the number of steps can be suppressed. Therefore, it is possible to remarkably improve the processing capability of the entire processor, especially at the time of executing an operation such as a product of three terms and a product of four.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a first arithmetic device according to the present invention.
FIG. 4 is a circuit configuration diagram showing an embodiment of FIG.
Similar to the SP, the present invention is applied to a DSP having two data buses and capable of simultaneously transferring two data between the memory 10 and the register file 8. Therefore, the same reference numerals are given to the components and elements corresponding to those in FIG. 3, and the description thereof will be omitted unless necessary.

In this embodiment, the output latch 4 of the multiplier 1 is connected to the selector 7 of one input of the data ALU circuit 5 and at the same time directly connected to the selectors 2 and 3 of the two inputs of the multiplier 1. It enables the output of the output latch 4 to be directly supplied to the two inputs of the multiplier 1 through the selectors 2 and 3, and the output result of the multiplier 1 is immediately input to the multiplier 1 in the next machine cycle. It was made possible.

That is, the paths from the output latch 4 of the multiplier 1 to the two inputs of the multiplier 1 are respectively provided so that the register file 8 and the output latch 4 can be selected as the inputs of the multiplier 1. is there. In the case of the configuration of this embodiment shown in FIG. 1, xn, yn, and z stored in the memory
The following procedure is required in order to perform N arithmetic operations of N ternary products of n (n = 1, 2, 3, ..., N) and return the result to the memory. . However, one line corresponds to one step.

R1 = x1; R2 = y1; (3.1) OMLT = R1 × R2; R2 = z1; (3.2) OMLT = OMLT × R2; R1 = x2; R2 = y2; (3.3) The following two steps are repeated for n = 2, 3, ..., N. R1 = OMLT; OMLT = R1 × R2; R2 = zn; (3.4) R1 → MEM; OMLT = OMLT × R2; R1 = x (n + 1); R2 = y (n + 1) (3.5 ) That is, (2N + 1) steps will suffice. This is a reduction in the number of steps of N or more as compared with the conventional configuration.

Thus, according to this embodiment, the multiplier 1 of the multiplier 1 is used at the time of executing an operation such as the triplet product or the quartet product which continuously uses only the multiplier 1 without using the ALU circuit 5. Since the output can be immediately used as the input of the multiplier 1 in the next machine cycle, the step of only data transfer does not appear, and the increase in the number of steps can be suppressed. Therefore, the processing capability of the entire processor can be significantly improved.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. In the first embodiment, the output latch 4 of the multiplier 1 is replaced by the selectors 2 and 3 of the two inputs of the multiplier 1.
Although a path from the output latch 4 of the multiplier 1 to the input of the multiplier 1 is provided by directly connecting to, the output of the multiplier 1 is directly connected to the register file 8 in this embodiment as shown in FIG. Then, the register file 8 has a function of latching the output of the multiplier 1 so that the output of the multiplier 1 can be directly supplied to the two inputs of the multiplier 1 through the selectors 2 and 3. Is.

That is, in this embodiment, the output of the multiplier 1 is directly supplied to the register file 8 so that it is not necessary to provide the multiplier 1 with an output latch, and the output result of the multiplier 1 is immediately output in the next machine cycle. It is configured so that it can be used as an input to the multiplier 1. In the case of the configuration of this embodiment shown in FIG. 2, xn, y stored in the memory
In order to perform N operations of n and zn (n = 1, 2, 3, ..., N) consecutively and return the result to the memory,
The following steps are required. However, one line corresponds to one step.

R1 = x1; R2 = y1; (4.1) OMLT = R1 × R2; R2 = z1; (4.2) For n = 2, 3, ..., N, the following two steps are performed. repeat. OMLT → MEM; OMLT = R1 × R2; R2 = zn; (4.3) OMLT = OMLT × R2; R1 = x (n + 1); R2 = y (n + 1); (4.4) 2N steps will suffice.

Thus, also in this embodiment, the product of three terms,
Multiplier 1 without using ALU circuit 5 such as quadratic product
When performing an arithmetic operation in which only one is continuously used, the output of the multiplier 1 can be immediately used as the input of the multiplier 1 in the next machine cycle, so that the step of only data transfer does not appear and the operation is executed. The number of steps can be significantly reduced. Therefore, the processing capability of the entire processor can be significantly improved.

In each of the above embodiments, the case where the ternary product is continuously calculated has been described, but the case where not only the ternary product but also the quadratic product, the quintic product, and the like is continuously calculated. It is needless to say that the present invention can be applied to and the same operational effect can be obtained. Further, the present invention can be applied to a device configured to use the data bus in a time division manner, and further to a device configured to insert a shifter between the output latch of the multiplier and the input to the data ALU circuit. Of course, the present invention can be applied. In addition, it goes without saying that various modifications and changes can be made as necessary.

[0024]

As described above, according to the present invention, D
Since a multiplier and an ALU circuit are connected in cascade like SP and an arithmetic device for performing high-speed arithmetic processing based on a pipeline system is provided with a path capable of directly inputting the output of the multiplier to the input of this multiplier, The output result of the multiplier can be immediately input to the multiplier in the next machine cycle. Therefore, in the arithmetic processing in which only the multiplier is continuously used, the step of only data transfer can be eliminated, so that the number of execution steps can be significantly reduced and the processing capacity of the entire processor can be reduced. There is an effect that it can be remarkably improved, and the effect is particularly remarkable in the continuous arithmetic processing of the ternary product, the quaternary product, ....

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of an arithmetic unit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the arithmetic unit according to the present invention.

FIG. 3 is a circuit configuration diagram showing an example of a conventional arithmetic device.

Front Page Continuation (72) Inventor Yukihiko Okumura 2-10-1 Toranomon, Minato-ku, Tokyo NTT Mobile Communication Network Co., Ltd.

Claims (2)

[Claims] 1. A multiplier having two inputs, each input having a selector and having an output latch, an ALU circuit having two inputs and having a selector at each input, and a plurality of registers. With
It has an input / output interface with a data bus, receives the output of the ALU circuit as an input, and gives the value of an arbitrary register as the input of the multiplier and the ALU circuit via the multiplier and the selector of the ALU circuit, respectively. And a register file capable of storing the register file, and a path from the output latch of the multiplier to each selector of the multiplier is provided, and the register file and the output latch of the multiplier serve as inputs of the multiplier. An arithmetic unit characterized by being selectable. 2. A multiplier having two inputs, each input having a selector, an ALU circuit having two inputs and each input having a selector, a plurality of registers, and a data bus. It has an input / output interface and receives the output of the ALU circuit as an input,
An arithmetic unit comprising: a register file capable of giving a value of an arbitrary register as an input to the multiplier and the ALU circuit via a selector of the multiplier and the ALU circuit, respectively. A path is provided to allow the register file to have a function of latching the output of the multiplier, and the output of the multiplier latched in the register file can be selected as an input of the multiplier. An arithmetic unit characterized by.