JPS6075155A - Timing pull-in system - Google Patents

Abstract

PURPOSE:To attain rapidly pull-in by supervising a frequency offset based on an amount of error, and applying the correction proportional to said amount. CONSTITUTION:After an amplitude of a signal is adjusted by a timing AGC20, the signal is delayed by a delay circuit 21 and the phase is corrected by multipliers 22, 23. Then the result is delayed at a delay circuit 24, the amount of error is calculated by a multiplier 25, a control coefficient beta is multiplied by a multiplier 26, the result is integrated by an adder 27 and a delay circuit 28, and the phase angle is obtained by an inverse tangent calculation circuit 37. Then a delay time calculation circuit 36 derives the delay time to control a symbol rate/ sampling rate correction circuit 30, and a clock pulse control circuit 29 for PLL is controlled by constituting a low pass filter of the multiplier 31, the adder 32, the delay circuit 33 and the multiplier 34.

Description

[Detailed Description of the Invention] [Technical Part of the Invention f] The present invention relates to a timing pull-in method in a modem,
In particular, the timing pull-in is made fast and stable.

[Prior art and problems]

When extracting data from the received 1d signal in the modem,
In order to separate the data from the transmitted signal, it must be sampled at a certain timing.

Although it is necessary to create a clock for this sampling, the timing on the receiving side will vary slightly due to the influence of the line. Therefore, during reception, it is necessary to synchronize the clock according to this shifted clock. For example, in a 9,600 bit/second transmission circuit having signal points as shown in FIG. 1, there is a deviation of approximately ±1,100 PP, so it is necessary to synchronize the clocks to account for this deviation.

For this purpose, conventionally, as shown in Figure 2, in the initial state, the input signal is sampled by the A/D conversion circuit 1, the timing waveform is extracted by the timing waveform extraction circuit 2, and its peak value is kept constant. After inputting the signal to the normalization circuit 6 and making the amplitude constant, the signal is input to the phase correction circuit 4, and the phase of the waveform is corrected to obtain the optimum timing phase. This output is then input to a timing phase pull-in circuit 5 to take two pulls between one symbol of the input waveform.

By taking the arctangent of the two samples, information on a delay time that forces one of the two samples to 06 is input to the digital PLL circuit 6.

This digital PLL circuit 6 can perform phase jumps based on delay time information to match the optimal timing phase.

Here, the details of the timing waveform extraction circuit 2 are as follows.

This is shown in FIG.

The sampling signal of the line input signal has the same frequency and a phase of 90° in the first demodulator 7 and the second demodulator 8.
By multiplying different carrier waves, an output of a component of % of the symbol rate is obtained. In this example 96.00 bit
Since this is a modem of /s, the symbol rate is 2400 Hz, and 4 bits of data are transmitted per symbol. Thus, the 1200 Hz component is transmitted to the first demodulator 7.
and is output from the second demodulator 8, and these are 1200H
z (1200 by the pass filters 9 and 10) (
Z is output, and a 24001 (component of Z) is outputted by a squaring circuit constituted by 2 multipliers 11 and 12. Then, these are added by an adder 16, and a timing component is output regardless of the phase. 2400 Hz] The DC component is cut by the I-pass filter 4, and the DC component is cut by the 2400 Hz band-pass filter 5 shown in Figure 4.
An AC waveform of 0 Hz is obtained. Then, this is input to the normalization circuit 6 and the amplitude is adjusted to a constant amplitude. This is 9
The phase is corrected by α by the phase correction circuit 4, which is composed of a delay circuit 16 to the power 3), a device 17, 18, and an adder 19, and the output ω(ωt
+α) is obtained.

This phase-corrected output is sent to the timing phase pull-in circuit 5.
, but here, as shown in Figure 5 (b), <, 24
001-IZ input waveform of 1 symbol of 9600 bits of sembling points S□ to S4, two consecutive
Point 1 For example, take S, , SZ and calculate the ta♂r of these two samples.
im, and select one of the sampling points (SZ in the example in Figure 5) by strongly filling Oo.
1) Data on delay time information such as
Input to L circuit 6. As a result, as shown in FIG. 5(d), B2 of B1°B2 is delayed by this amount and becomes Bt, and the digital PLL circuit 6 performs a phase jump based on this delay time information. 2 400 H when the sampling point S2 shown in is zero-crossed
The Z signal is obtained from the digital PLL circuit 6.

In this way, one sampling point 9 in one symbol that is forcibly adjusted to 0°, for example, the sampling point S2 that crosses zero, is monitored. At this time, if there is no deviation at all in the line input signal, the output at that sampling point should be zero, and if there is small oscillation, negative and negative signals will appear alternately. However, several symbols in a row are + or -
If there is an output in the direction of , this means that a frequency shift exists. Therefore, in cases like this.

By switching the capture range, the clock forming the digital PLL circuit 6 is removed or inserted to match the timing frequency.

However, in such a method, frequency synchronization has not yet been achieved at the time when two phases are matched, and frequency synchronization is performed sequentially after one phase synchronization, resulting in slow pull-in. In addition, since only the sign of the phase at the specific sampling point is monitored in the foot control system, there is a drawback that unstable operation may occur, such as erroneous judgments when the sign momentarily reverses due to noise or the like.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing pull-in method that monitors errors not only based on signs, but also amounts, and makes corrections proportional to the amount of errors, in order to overcome these drawbacks.

[Structure of the invention]

In order to achieve this object, the timing pull-in method of the present invention is provided with an extraction section that extracts a received timing signal from an input signal, and an error amount integration means that integrates a variation error of the extracted timing signal phase, The present invention is characterized in that the reception timing pull-in sound is controlled by synchronizing the frequency of the timing signal extracted by the error amount integrating means.

[Embodiments of the invention]

An embodiment of the present invention will be explained with reference to FIGS. 6 and 7.

FIG. 6 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is an explanatory diagram of its operation.

In FIG. 6, 20 is a timing AGC circuit, which corresponds to the normalization circuit 3 in the r's2 diagram, and unifies the amplitude of the signal output from the timing waveform extraction circuit to its maximum amplitude. It is something.

The PLL clock pulse control circuit 29 is a clock pulse control circuit for PLL (second
This is a jump-enabled control that determines where the capture range of the digital PLL (in the figure) is initially set.
, B pattern is used to jump adjust the capture range and quickly synchronize one frequency.

Symbol rate/sampling rate correction circuit 30 (J
This not only makes corrections when the symbol rate or sampling rate is changed, but also adjusts the capture range by one clock to match the phase. The sampling rate is created based on the symbol rate.

Next, the operation of the present invention will be explained in the case of a 9600 t) ps modem (D). In this case, the sampling frequency is 2400 symbols/S + sampling frequency B9600H7i.

First, in FIG. 6, delay circuit 242 multiplier 25, 26
．． Adder 27. The lines of the delay circuit 28 will be explained.

In the same manner as described above in detail with respect to the phase correction circuit 4 of FIG. 4, a phase correction output of the optimal timing phase α is obtained by the delay circuit 212 and the multipliers 22.23. This phase correction output is input to the delay circuit 241 and the multiplier 25. At this time, the delay circuit 24 is delayed by one symbol (2400 HZ). Therefore, this delay circuit 24 and multiplier 2
The circuit constituted by 5 performs the following operation.

In Figure 7 (a), the carrier of 24υOHZ is 96
0 o ) (When sampled at the sampling points S,, S,... of Z, Sl and 85 are delayed by one cycle. Therefore, if there is no fluctuation in frequency at this time, around this one cycle The complex common category of is zero, but there is a deviation by θ′.

e-1θ*61(θ+θ)me+θ', and the error portions t and l are output. This blur is output from the multiplier 25 and multiplied by a coefficient β in the 9 multiplier 26.

If this state of blur continues, the amount of error will be determined by the integrating circuit constituted by the adder 27 and the delay circuit 28. Therefore, due to the error amount of tzu, PLL
Controls the clock pulse control circuit 29 for adjusting the PLL capture range by jumping as the case requires.
Immediately correct frequency fluctuations.

Next, the route of the arctangent calculation circuit 67 will be explained.

The real component R is transmitted to this arctangent calculation circuit 37 from the multiplier 22 of the two-phase correction circuit.
5, the image component is transmitted. When the sampling point at this time is Sl, 1 rm tan page = θ0 The phase angle θ is determined by the above equation. I get criticized. This is calculated for two consecutive sampling points, and based on these data, the delay time calculation circuit 56 calculates the sampling point SI or S.
The delay time required to make either one of the two points a zero cross point is determined. Therefore, this delay time allows the symbol rate/sampling rate correction circuit 60 to be controlled to perform the initial phase angle adjustment.

Also, a 2 multiplier 61. Adder 52. The N extension circuit 63 and the N filter 54 constitute a low pass filter.

This low-pass filter is 71977 around one symbol.
The state of the points is compared, and the multipliers 51 and 54 multiply by appropriate control coefficients α' and β'.

This low-pass filter detects the frequency pull-in state of the sampling point, for example, at the zero cross point. If there is no retraction, the sampling point near the zero loss point will be either static or negative, but if it is retracted, it will alternate between positive and negative depending on the slight fluctuation.

Eliminate the changes in heat using a low-pass filter. Therefore, this low-pass filter has a control function in the C, D pattern or data region of the LPFi, i, l-laning signal.

In the present invention, in the initial state, the received signal is
Extract the Hz timing waveform and use the 9th timing AG
After the peak value is set to a constant level by the C circuit 20, 9
It is branched into two in the phase correction circuit. One remains unchanged and the other is delayed by the sampling period, so 24
A tone of 00Hz has a phase shift of 90@. Then, one is the real R2, the other is the imager, and the second is the coefficient time α that will be the optimal phase when the timing is retracted.
.

-α is multiplied, the results are added, and the delay circuit 24 and the integration circuit configured by the adder 27 and the delay circuit 28 integrate the result. The PLL clock pulse control circuit 29 calculates the integral value of the frequency offset obtained in this way.
The capture range of PI and L is greatly controlled by transmitting the signal to 9 frequencies, and the 9 frequencies are matched. This operation is A of the training signals.

This is done using pattern B.

One sampling point out of four samples in one symbol is extracted from the real component R and the image component Xm obtained from the multipliers 22 and 25 of the phase correction circuit, and then t a r+7'! ”, and from this calculate the delay time so that this sampling point becomes the zero cross point,
Extend the symbol rate and jump one phase to match the phase.

After the phases are matched in this way and frequency pull-in is performed, 5, for example, an image component is taken out from the sampling point in one symbol matched with 09 of the 1 phase correction circuit and inputted to the low-pass filter LPF. The output of this low-pass filter LPF is zero when the phases match, and becomes a + value when the reception timing is behind the I+) conversion timing, and conversely, when the reception timing is ahead of the I) conversion timing. has a negative value. PLL
The digital PLL control circuit 29 uses the sign and magnitude of this clock pulse I, PF'.
(inserting or removing pulses from the clock) and correcting the symbol rate.

Note that as the timing AGC circuit 20.

If the dynamic range is set to an appropriate value, and only those above a certain level are kept at a constant peak value, and those below a certain level are set to a small level, the feedback iμ of the timing component at a small level that is easily affected by noise will be reduced. Therefore, the timing pull-in of the present invention can be made more stable.

Note that although the above description has been made using an example of a 9600 bps modem, the present invention is of course not limited to this.

〔Effect of the invention〕

According to the present invention, the nine-frequency offset can be monitored not only by the sign but also by the error amount, and correction can be made in proportion to this, so that the pull-in can be performed quickly.

[Brief explanation of drawings]

Figure f431 is a diagram of signal points, Figure 2 is a conventional timing pull-in method, Figure 6 is a detailed diagram of a timing waveform extraction circuit, and Figure 54 is a detailed diagram of a phase correction circuit. FIG. 5 is an explanatory diagram of the retracting operation, FIG. 6 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is an explanatory diagram of the operation. In the figure, 1 is an A/D conversion circuit, 2 is a timing waveform extraction circuit, 3 is a normalization circuit, and 4 is a phase correction circuit. 5 is a timing phase pull-in circuit, 6 is a digital PLL, 2
9tJ: PLL clock pulse control circuit. 60 is a symbol rate/sampling rate correction circuit;
66 is a delay time calculation circuit, and 67 is an arctangent calculation circuit. q) Applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani Figure 5 Figure 7

Claims (1)

[Claims] an extraction unit that extracts the reception timing signal from the input signal;
An error amount integrating means for integrating a fluctuation error amount of the extracted timing signal phase is provided, and the frequency of the timing signal extracted by the error amount integrating means is synchronized to control reception timing pull-in. Timing pull-in method.