JPH0657019B2 - Timing pull-in method - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a timing acquisition method in a modem,
In particular, the timing pull-in is fast and stable.

[Conventional technology and problems]

When extracting data from a received signal in a modem, it is necessary to sample at some timing in order to distinguish the data from the transmitted signal. Then, it is necessary to create a clock for this sampling, but the timing slightly deviates on the receiving side due to the influence of the line. Therefore, in reception, it is necessary to synchronize the clocks according to the shifted clocks. For example, in a 9600 bit / sec transmission circuit having signal points as shown in FIG. 1, ± 100P
Since there is a PM shift, it is necessary to synchronize the clocks accordingly.

Therefore, conventionally, as shown in FIG. 2, in the initial state, the input signal is sampled by the A / D conversion circuit 1, the timing waveform is extracted by the timing waveform extraction circuit 2, and the peak value is made constant. Is input to the normalization circuit 3 and the amplitude is made constant, and then input to the phase correction circuit 4 to correct the phase of the waveform for the optimum timing phase.
Then, this output is input to the timing phase pull-in circuit 5 to take two samples between one symbol of the input waveform and take the arctangent of two samples to force one of the two samples to 0 °. The information of various delay times is input to the digital PLL circuit 6. This digital PLL circuit 6 can perform a phase jump according to the delay time information and match the optimum timing phase.

Details of the timing waveform extraction circuit 2 are shown in FIG.

In the first demodulator 7 and the second demodulator 8, the sampling signal of the line input signal has the same frequency and a phase of 90 °.
The symbol rate of 1 by multiplying different carriers
Obtain the output of the / 2 component. In this example, 9600 bits /
In the case of the s modem, the symbol rate is 2400 HZ, and 4-bit data is transmitted per symbol. On the receiving side, the first demodulator 7 and the second demodulator 8
The component including 1200HZ demodulated and output from 1200
1200 HZ by HZ bandpass filters 9 and 10
Is output, and the 2400 HZ component is output by the squaring circuit configured by the multipliers 11 and 12. Then, these are added by the adder 13 and the timing component is output regardless of the phase. A direct current component of this is cut by a high-pass filter 14 of 2400HZ, and a 2400HZ filter shown in FIG.
An AC waveform of 2400 HZ is obtained by the HZ band pass filter 15. Then, this is input to the normalization circuit 3 so that the amplitude is adjusted to a constant magnitude. A delay circuit 16 for delaying this by 90 °, multipliers 17 and 18, and an adder 19
The phase is corrected by α by the phase correction circuit 4 constituted by the above, and the output cos (ωt + α) of the optimum timing phase is obtained.

This phase-corrected output is the timing phase pull-in circuit 5
It is input to, but as shown in FIG.
Two consecutive points of sampling points S _{1 to} S ₄ of 9600 HZ between one symbol of the input waveform of 00 HZ, for example, S
_{Take 1} and S ₂ of these 2 samples Then, information on the delay time for forcibly setting either one of the sampling points (S _{2 in} the example of FIG. 5) to 0 ° is input to the digital PLL circuit 6. Thus, as shown in FIG. 5 (d), the baud rate B _1, B of the ₂ B ₂
There B _'2 becomes delayed by this amount, digital PL
The L circuit 6 makes a phase jump according to this delay time information, and the sampling point S ₂ shown in FIG.
A 400 HZ signal is obtained from the digital PLL circuit 6.

In this way, one sampling point in one symbol forcibly adjusted to 0 °, for example, the sampling point S _{2 at} which the zero cross is made is monitored. At this time, if there is no deviation in the line input signal, the output at the sampling point should be zero, and if it vibrates small, plus and minus appear alternately. But several symbols in succession + or-
If there is an output in the direction of, this means that there is a frequency shift. Therefore, in such cases,
The capture range is switched, and the clock configuring the digital PLL circuit 6 is extracted or inserted to match the timing frequency.

However, in such a method, since the frequency synchronization has not yet been achieved at the time of phase matching, the lead-in is slow because the frequency synchronization is sequentially performed after the phase synchronization. Further, even in the steady state, since only the sign of the phase of the specific sampling point is monitored, there is a drawback that an unstable operation is performed such as an erroneous judgment when the sign is momentarily inverted due to noise or the like.

[Object of the Invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing pull-in method for remedying such a drawback, in which the error is monitored not by the code alone but by the amount and a correction proportional to the error amount is applied.

[Structure of Invention]

To achieve this object, the timing pull-in method of the present invention has a PLL clock pulse control circuit that creates a timing signal for reproducing a received signal, and the sampling timing generated by the PLL clock pulse control circuit is used as the received signal. In the timing pull-in method for synchronizing with the above, the reception timing signal is extracted from the reception signal, the phase variation error amount between the extracted reception timing signal and the sampling timing is extracted and integrated, and the PLL clock pulse control circuit The phase of the sampling timing signal generated by the PLL clock pulse control circuit is corrected based on the integrated value.

Example of Invention

An embodiment of the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is an operation explanatory diagram thereof.

In FIG. 6, reference numeral 20 denotes a timing AGC circuit, which corresponds to the normalization circuit 3 of FIG. 2 and unifies the amplitude of the signal output from the timing waveform extraction circuit to have the maximum width. It is a thing.

The PLL clock pulse control circuit 29 includes a PLL (second
This is to control where the capture range of the digital PLL shown in the figure is set first so that it can be jumped. As will be described later, the capture range is jump adjusted by using the A and B patterns in the training signal of the modem, and the frequency is adjusted. The synchronization is done immediately.

The symbol rate / sampling rate correction circuit 30
Not only is the correction performed when the symbol rate or sampling rate is changed, but the capture range is adjusted by one clock to perform phase matching. The sampling rate is created based on the symbol rate.

Next, the operation of the present invention will be described in the case of a 9600 bps modem. In this case 2400 symbols / S,
The sampling frequency is 9600HZ.

First, in FIG. 6, the delay circuit 24, the multipliers 25, 2
6, the lines of the adder 27 and the delay circuit 28 will be described.

In the same manner as described above in detail with respect to the phase correction circuit 4 in FIG. 4, the delay circuit 21 and the multipliers 22 and 23 obtain the phase correction output of the optimum timing phase α. This phase correction output is input to the delay circuit 24 and the multiplier 25. At this time, the delay circuit 24 delays by one symbol (2400HZ). Therefore, the delay circuit 24 and the multiplier 25
The circuit configured by performs the following operation.

In FIG. 7A, the sine wave of 2400 HZ is 960.
When being sampled at the sampling points S ₁ , S ₂ ... Of 0HZ, S ₁ and S ₅ are delayed by one cycle.
Therefore, at this time, if there is no shake in the frequency, the complex conjugate number around this one cycle is zero, but if there is a shake of θ ', e ^-j _θ · e ^{j (} _{θ + θ' )} = e ^j _{θ '} The minute e ^j _θ'is output. This blur is output from the multiplier 25, and this imaginary part is multiplied by the coefficient β in the multiplier 26.
Is multiplied.

If this blurring state continues, the amount of error will be obtained by the integrating circuit composed of the adder 27 and the delay circuit 28. Therefore, the PLL clock pulse control circuit 29 is controlled by this error amount, the capture range of the PLL is jumped and adjusted depending on the case, and the frequency fluctuation is immediately corrected. That is, when the frequency of the timing component extracted as described above is c and the frequency of the reference clock is _R , Therefore, it is possible to know how fast or slow the frequency of fc is than the reference frequency.

Next, the route of the arctangent calculation circuit 37 will be described.

The real component R is transmitted from the multiplier 22 of the phase correction circuit to the arctangent calculation circuit 37, and the multiplier 2
The Imaginary component Im is transmitted from 3. When the sampling point at this time is S ₁ The phase angle θ ₀ is obtained by the above equation. 2 in succession
One sampling point is obtained, and the delay time required for the delay time calculation circuit 36 to set either _one of the sampling points S ₁ or S ₂ as a zero cross point from these data. Therefore, due to this delay time, the symbol rate / sampling rate correction circuit 30
Can be controlled to perform the first phase alignment.

Further, the multiplier 31, the adder 32, the delay circuit 33, and the multiplier 34 constitute a low-pass filter. This low-pass filter is for comparing the states of sampling points before and after one symbol, and is multiplied by appropriate control coefficients α ′ and β ′ in the multipliers 31 and 34. Note that the delay circuit 38 inputs the image merge Im to the multiplier 31. With this low-pass filter, for example, the frequency pull-in state at the sampling point at the zero cross point is detected. If the pull-in is not performed, the sampling points near the zero cross point will be either positive or negative, but if pull-in, positive and negative will change depending on a slight blurring, but
This change is eliminated by a low pass filter. Therefore, the low pass filter LPF has a control function in the C and D patterns of the training signal or in the data area.

In the present invention, first, in the initial state, 2400 is obtained from the received signal.
The timing waveform of HZ is extracted, and then the timing AG is used.
After the peak value is set to a constant level by the C circuit 20,
It is branched into two in the phase correction circuit. One is unchanged and the other is delayed by the sampling period, so 24
The phase is shifted by 90 ° with the tone of 00HZ. One is real R and the other is image merge Im, and the coefficient co is such that the optimum phase is obtained when the timing is next pulled.
The delay circuit 24 multiplies sα and sinα and adds them.
And to the multiplier 25. With this, the error amount of the frequency is calculated, and this error amount is multiplied by the control coefficient β, and this is integrated by the integrating circuit configured by the adder 27 and the delay circuit 28. The integrated value of the frequency offset thus obtained is transmitted to the PLL clock pulse control circuit 29 to significantly control the capture range of the PLL.
Match the frequency. This operation is performed using the A and B patterns of the training signal.

A real component R obtained from the sum of the multipliers 22 and 23 of the phase circuit and an image component Im obtained from the delay circuit 38.
1 out of 4 samples in 1 symbol from Is calculated, the delay time is calculated from this so that the sampling point becomes the zero cross point, the symbol rate is extended, and the phase is jumped to match the phase.

After the phases are matched and the frequency is pulled in this way, for example, an image component of a sampling point in one symbol adjusted to 0 ° of the phase correction circuit is extracted and input to the low pass filter LPF. The output of this low-pass filter LPF becomes zero when the phases match,
It becomes a positive value when the reception timing is behind the reproduction timing, and is a negative value when the reception timing is ahead of the reproduction timing. PLL
The clock pulse control circuit 29 for use calculates the number of pulses for inserting or removing clock pulses of the digital PLL according to the sign and size of the low-pass filter LPF, and corrects the symbol rate.

The timing AGC circuit 20 is easily affected by noise by setting its dynamic range to an appropriate value, keeping only the peak level above a certain level and keeping the peak level below a small level. The feedback amount of the small-level timing component becomes small, and the timing pull-in according to the present invention can be made more stable.

In the above description, an example of a 9600 bps modem has been described, but the present invention is not limited to this.

〔The invention's effect〕

According to the present invention, the frequency offset is monitored not only by the sign but also by the error amount, and the correction proportional to this can be performed, so that the lead-in can be performed quickly.

[Brief description of drawings]

1 is an explanatory view of signal points, FIG. 2 is a conventional timing pull-in system, FIG. 3 is a detailed view of a timing waveform extraction circuit,
FIG. 4 is a detailed view of the phase correction circuit, FIG. 5 is a drawing for explaining the pull-in operation, FIG. 6 is a block diagram of an embodiment of the present invention, and FIG. 7 is a drawing for explaining the operation. In the figure, 1 is an A / D conversion circuit, 2 is a timing waveform extraction circuit, 3 is a normalization circuit, 4 is a phase correction circuit, 5 is a timing phase pull-in circuit, 6 is a digital PLL, and 29 is a PLL.
Clock pulse control circuit, 30 symbol rate / sampling rate correction circuit, 36 delay time calculation circuit,
Reference numeral 37 indicates an arctangent calculation circuit.

Claims (1)

[Claims] 1. A timing pull-in method for synchronizing a sampling timing generated by the PLL clock pulse control circuit with a received signal, the PLL clock pulse control circuit generating a timing signal for reproducing the received signal, The reception timing signal is extracted, and the variation error amount of the phase between the extracted reception timing signal and the sampling timing is extracted and integrated, and the PLL clock pulse control circuit determines the PLL clock pulse control circuit based on the integrated value. A timing pull-in method, characterized in that the phase of a sampling timing signal generated is corrected.