JPS6074480A - Manufacture of iii-v semiconductor device - Google Patents

Abstract

PURPOSE:To lower operating voltage and to upgrade the efficiency of a III-V semiconductor device by a method wherein a first conductive-type low-resistance region is epitaxially grown on a high-resistance region and second conductive- type impurities are diffused in the low-resistance region. CONSTITUTION:A high resistive i-layer or v-layer 11 and a p<+> type layer 12 are grown on a substrate 10 by a liquid-phase growth method. During the growing time, S of n type impurities is diffused in the i.v-layer 11 and a thin n<+> type layer 20 is formed. then, Zn is diffused in the p<+> type layer 12, a diffusion layer 13 is formed, the n<+> type substrate 10 is made thinner, the thickness of the total of the epitaxially grown layer and the n<+> type substrate 10 is formed in less than 10mum or thereabouts, and an ohmic contact is respectively formed at the n<+> type substrate 10 and the p<+> type diffusion layer 13.

Description

[Detailed description of the invention] One of the two low resistance regions forming the pn junction is a 11 channel under the reverse direction high density of the pn junction, which is based on the method for manufacturing extremely thin semiconductor devices. Negative resistance die Δ-de due to immersion and transit time effect, tie y straw tongue 1 to die A-do (Special Public Show/l'l-1 10 9 5 8
) is a transit time negative resistance diode using avalanche injection (Inbara 1 ~ Gui 71-1 ~) J, which can also operate at high frequency and have low lightning pressure, lI (hl?"1) Are known.

Figure 1 shows the ideal electric field distribution of a tannet diode. 1 (This is a region where the electric field strength is strong enough to cause one person to occur, and 2 is a region where the electric field strength is strong enough to cause the tunnel-injected carriers to be saturated). It is.

The die needle structure that realizes the electric field distribution shown in Figure 1 is as follows:
11''-n+-i (ν) = n+ type is ideal, but the thickness required for tunnel implantation is approximately 100 Å or less, making it difficult to manufacture.

The inventor of this application has already filed Japanese Patent Application No. 55-15135,
5-1750/4 @J:su, p+.

-1(shi)-1) Provides an easy manufacturing method for a Tannet type 1-tie A-de, varactor diode, etc.

The present invention provides a method for manufacturing 1-v semiconductor devices such as tannet diodes and efficient varactor diodes that can reduce the power required for oscillation.

The present invention will be described in detail below with reference to the drawings. Figure 2 (
A) to (e) are examples of the method for manufacturing a tannet diode of the present invention.

10 is 3i doped II Ga A S j, <IF
1, (There is a high resistance <, -i layer on the substrate 10, and the V layer 11 and the first layer 12 are grown at approximately 800°C by a liquid phase growth method using a vapor pressure 11 temperature 1α difference method. 1) In the Qa melt for layer growth, IJ, p-type impurities are added to Ge, and n-type impurities (Ga2, s3 to As, s3 are added). The 11-type impurity S diffuses into the i layer 11 and forms a thin 11-1 layer 20.
(Fig. 2(c)), and then heated 711 to 600'C (for example, 15 min.~1
Diffusion for about an hour to form a diffusion layer 13 (FIG. 2(d))
, n substrate with Noflumina powder and lapping with Kagakuken ρ1 etc.; II ↓1 to the plate, Δu-Qe alloy 15, l
) + Δri to the diffusion layer 13, J to the Zn alloy 14: Δ−
After forming the Mikini I contact 1, the gold layer 17 is formed and covered by vacuum vaporization method or plating method (Fig. 2 (+)). A-
In the case of d3, it is sufficient to write Wd=3″Us/=1.f.Here, VS is the saturation speed B of the main 1 aria.
(cm/sec), f is the operating frequency (Hz). 'lis = 1 x 10 cm/see, [100GI-1z, 200Gl-12,30
0Gl-1z, 500Gl-(Z and Zurudoki, W (
I is 0.75μl++, 0.38t1m, respectively.
It may be set to about 0.25 μm, 0.1511 m. 1
) + The thickness of the layer 12 should be J3 approximately 1 μ■ or less in order to reduce the thermal resistance, and the thickness of the diffusion layer 13 (, J
] - λ than the thickness of the p+ layer 12 by bitaxial growth
9 J is enough.

FIG. 3 shows yet another embodiment of the present invention, and the difference from FIG. <
13)). The following is the same as the embodiment shown in FIG. 11
By setting the impurity density of the layer 18 to, for example, 5.times.10 cm.sup.2, the embodiment J.sub.Z of FIG. 2 also has the advantage of reducing the series resistance.

Please take a look at the T shown in Figure 3.10 (') L/
Fig. 4 shows an example in which the Il+ square is cut out and bonded to a millimeter wave path pad/7-, 30 is the Tannet 1-diode 1~ of the present invention, 31 is a quartz stand, 32
33 is a gold tape, and 33 is a gold-plated copper stem.

The diameter of the joint is made smaller using a tannet dye (for example, 6Aj acid, hydrogen peroxide solution, water, etc.). -1- is one millimeter wave (Yahiti (110~170G)
However, the conventional oscillation threshold voltage 7~℃)\/J, Rimo The low value of about 5.3V is 1", (1"11" junction is 1) + layer 12 is grown, GaFAAl is poured into the solution and covered. It goes without saying that it can be adjusted by changing the skewer of usJ, and can be applied to the production of tannet 1, ties A-F, as well as 4I: Kubaraku tie) Y-1 to '-9.111 Diffusion layer 13 on the surface It is not 211, but 1) It is not a good thing to say that it is a small and dull material. 3. The growth method may be liquid phase growth using a slow cooling method.

As explained above, the present invention operates at a lower voltage than the conventional Tannet (-) diode and can significantly improve efficiency, and is a semiconductor having a thin 1)+-11 junction. Effective for manufacturing equipment.

[Brief explanation of drawings]

Figure 1 is a graph showing the electric field distribution of an ideal tannet diode, Figures 2 and 3 are examples of the present invention, and Figure 4 is an example of a packaged tannet diode for millimeter waves. It is. Patent applicant / Figure (CL') (shi) #! Figure 2 - (b> [ (C) (C) ts, Figure 5

Claims (2)

[Claims] (1) High resistance of the first conductivity type ■-■ semiconductor region'' Second, a thin first low resistance of the first conductivity type 111-■ A second low resistance of the second conductivity type which is the opposite conductivity type to the semiconductor region. 1 [1-V semiconductor region and forming a 1)1) junction between the first and second low resistance ■-■¥: conductor regions, the method comprising: A 1) a-type second low resistance semiconductor region containing the first conductivity type impurity directly on the resistor ■-V semi-S semiconductor region is epitaxially grown on the liquid phase, and a thin first conductivity type impurity is grown on the liquid phase. The resistor 11-V 2+4 conductor area is connected to the 3'? 1-resistance 1-V semiconductor region; and 1-V semiconductor region.
V semiconductor device manufacturing method. (2) Said 1"J a' characterized by roughly including a step of covering said high resistance ■-V semiconductor region on said first conductivity type low resistance ■-■ semiconductor substrate by liquid phase epitaxial growth.
t A method for manufacturing an I[l-V semiconductor device according to claim 11, 1