JPS6072572U - Composite signal peak level detector - Google Patents

Composite signal peak level detector

Info

Publication number
JPS6072572U
JPS6072572U JP16501283U JP16501283U JPS6072572U JP S6072572 U JPS6072572 U JP S6072572U JP 16501283 U JP16501283 U JP 16501283U JP 16501283 U JP16501283 U JP 16501283U JP S6072572 U JPS6072572 U JP S6072572U
Authority
JP
Japan
Prior art keywords
composite signal
level detector
peak level
signal peak
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16501283U
Other languages
Japanese (ja)
Inventor
金子 光幸
Original Assignee
安藤電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 安藤電気株式会社 filed Critical 安藤電気株式会社
Priority to JP16501283U priority Critical patent/JPS6072572U/en
Publication of JPS6072572U publication Critical patent/JPS6072572U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はコンポジット信号の波形例を示す図、第2図は
この考案による実施例の回路図。 1・・・・・・コンポジット信号、2・・・・・・エン
ベロープ、11・・・・・・入力端子、12・・・・・
・コンパレータ、13・・・ダイオード、14・・・・
・・抵抗、15・・・・・・コンデンサ、16・・・・
・・増幅器、17・・・・・・指示計゛、18・・・・
・・リセットスイッチ、19・・・・・・出力、20・
・・・・・積分器。
FIG. 1 is a diagram showing an example of the waveform of a composite signal, and FIG. 2 is a circuit diagram of an embodiment according to this invention. 1...Composite signal, 2...Envelope, 11...Input terminal, 12...
・Comparator, 13...Diode, 14...
...Resistor, 15...Capacitor, 16...
...Amplifier, 17...Indicator, 18...
...Reset switch, 19... Output, 20.
...Integrator.

Claims (1)

【実用新案登録請求の範囲】 同相入力と逆相入力をもつコンパレータと、前記コンパ
レータの出力に接続するダイオードと、前記ダイオード
の出力に接続する積分器とを備え、 コンポジット信号を前記コンパレータの1つの入力に接
続し、前記積分器の出力を前記コンパレータの他の入力
に接続することを特徴とするコンポジット信号のピーク
レベル検出器。
[Claims for Utility Model Registration] A comparator having an in-phase input and an anti-phase input, a diode connected to the output of the comparator, and an integrator connected to the output of the diode, and a composite signal is input to one of the comparators. A peak level detector for a composite signal, characterized in that the output of the integrator is connected to the other input of the comparator.
JP16501283U 1983-10-25 1983-10-25 Composite signal peak level detector Pending JPS6072572U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16501283U JPS6072572U (en) 1983-10-25 1983-10-25 Composite signal peak level detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16501283U JPS6072572U (en) 1983-10-25 1983-10-25 Composite signal peak level detector

Publications (1)

Publication Number Publication Date
JPS6072572U true JPS6072572U (en) 1985-05-22

Family

ID=30361615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16501283U Pending JPS6072572U (en) 1983-10-25 1983-10-25 Composite signal peak level detector

Country Status (1)

Country Link
JP (1) JPS6072572U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120784U (en) * 1974-08-01 1976-02-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120784U (en) * 1974-08-01 1976-02-16

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