JPS6072341A - Channel setting system of pll synthesizer circuit - Google Patents

Channel setting system of pll synthesizer circuit

Info

Publication number
JPS6072341A
JPS6072341A JP58178151A JP17815183A JPS6072341A JP S6072341 A JPS6072341 A JP S6072341A JP 58178151 A JP58178151 A JP 58178151A JP 17815183 A JP17815183 A JP 17815183A JP S6072341 A JPS6072341 A JP S6072341A
Authority
JP
Japan
Prior art keywords
frequency divider
synthesizer circuit
pll synthesizer
synchronism
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58178151A
Other languages
Japanese (ja)
Inventor
Masaaki Hata
秦　正明
Kuniyoshi Marui
丸井　國與
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58178151A priority Critical patent/JPS6072341A/en
Publication of JPS6072341A publication Critical patent/JPS6072341A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To prevent disturbance to other channels and deterioration of S/N ratio to realize a communication operation of high performance, by again inputting information regarding the number of frequency division into a programmable frequency divider only when an out of synchronism is detected. CONSTITUTION:An out of synchronism detecting circuit 20 which detects the out of synchronism of a PLL synthesizer circuit 10 is provided and refreshing operations are made to be performed by again inputting information regarding the number of frequency division into a programmable frequency divider 12 only when the circuit 20 detects the out of synchronism. As a result, disturbance to other channels can be suppressed and, at the same time, deterioration of the S/N ratio can be prevented and, therefore, normal communicating operations can be secured easily for a long time.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はプログラマブル分周器を有するＰＬＬシンセ
サイザ回路のチャネル設定方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a channel setting method for a PLL synthesizer circuit having a programmable frequency divider.

〔発明の技術的背景およびその問題点〕多チャンネル切
換可能な自動車電話などの無線機では１通常フェーズ・
ロックド・ループ・シンセサイザ回路（以下単にＰＬＬ
という）が用いられており、第１図に従来のこの種の装
置の構成を示す。[Technical background of the invention and its problems] In radio equipment such as car telephones that can switch multiple channels, one phase
Locked loop synthesizer circuit (hereinafter simply PLL)
) is used, and FIG. 1 shows the configuration of a conventional device of this type.

第１図において、ｌはＣＰＵ２、ＲＡＭ３゜ＲＯＭ４お
よび入出力ポート５から成る周知構成のマイクロプロセ
ッサであり、１０は戒圧制御発振器（ＶＣＯ）１１．プ
ログラマブル分周器１２１位相比較器１３、基準発振器
１４およびループフィルタ１５から成るＰＬＬである。In FIG. 1, 1 is a microprocessor with a well-known configuration consisting of a CPU 2, RAM 3, ROM 4, and input/output port 5, and 10 is a control oscillator (VCO) 11. It is a PLL consisting of a programmable frequency divider 121, a phase comparator 13, a reference oscillator 14, and a loop filter 15.

マイクロプロセッサ１の演算によって、多チヤンネル中
の所定１チヤンネルが選択され、該所定チャンネルに対
応した周波数の出力を得ることができる分局数が設定さ
れる。マイクロプロセッサ１は該設定した分局数に対応
した分周数情報を人、出力ボート５を介してＰＬＬｌ０
のプログラマブル亦周器１２に出力する。プログラマブ
ル分周器１２はところで、この桟のＰＬＬシンセザイザ
においては屯縣ノイズなどの外乱の影響によってプログ
そこで従来は、マイクロプロセッサｌからプロ謂ゆるり
フレッシュ動作を行なうことで、プログを防止するよう
にしていた。By the calculation of the microprocessor 1, one predetermined channel among the multiple channels is selected, and the number of divisions that can obtain an output of the frequency corresponding to the predetermined channel is set. The microprocessor 1 sends frequency division number information corresponding to the set number of divisions to the PLL l0 via the output port 5.
The output signal is output to the programmable frequency regulator 12. By the way, in this PLL synthesizer, the programmable frequency divider 12 suffers from programming due to the influence of external disturbances such as Tongata noise.Therefore, conventionally, the programmable frequency divider 12 performs a so-called slow refresh operation from the microprocessor l to prevent programming. Ta.

第２図は上記リフレッシュ動作の具体例を示すタイムチ
ャートであり、（ａ）は分用靭情報、（ｂ）は外乱、（
Ｃ）はチャネル状態を示している。第２図に示すように
分ｌＪ＆情報は所定時間Ｔおきにプログラマブル分周器
１２に入力されてリフレッシ−動作が行なわれるが、こ
の第２図では時刻ｔ２において外乱が混入し、この結果
ＩＰＬＩ、１０の出力チャネルは所定のＡチャネルから
所定外のＢチャネルにずれたことを示している。すなわ
ち、この場合次のリフレッシ−動作が行なわれる時刻ｔ
３までは、Ｐ　Ｌ　Ｌ　ＩＱは所定外のＢチャネルで動
作することになる。FIG. 2 is a time chart showing a specific example of the above refresh operation, in which (a) shows the divisional toughness information, (b) shows the disturbance, and (
C) shows the channel state. As shown in FIG. 2, the divided lJ& information is input to the programmable frequency divider 12 at predetermined time intervals T to perform a refresh operation, but in FIG. Output channel 10 indicates a shift from a predetermined A channel to a non-predetermined B channel. That is, in this case, the time t at which the next refresh operation is performed
3, PLL IQ operates on a non-specified B channel.

したがって、上述した従来方式によれは、リフレッシ−
間隔Ｔの時間が長い場合にはプログラマブル分周器に記
憶した分局数情報が誤っている時間が長くなり、その間
正常な通信動作をなし得ないばかりでなく、他のチャネ
ルの通信に妨害を与える可能性が大きくなるという不都
合があった。Therefore, according to the conventional method described above, the refresh
If the interval T is long, the time during which the division number information stored in the programmable frequency divider is incorrect will increase, and during that time not only will normal communication operations not be possible, but it will also interfere with communication on other channels. The disadvantage was that the possibilities were greater.

〔発明の目的〕[Purpose of the invention]

〔発明の実施例１１ 以下、この発明を添付図面に示す実施例にしたがって詳
細に説明する。[Embodiment 11 of the Invention] Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

第３図はこの発明の実施例を示すものであり、先の第１
図に示したものと同じ構成要素については同一符号を付
しており、それらの説明は省略する。FIG. 3 shows an embodiment of this invention, and is similar to the first embodiment described above.
Components that are the same as those shown in the figures are designated by the same reference numerals, and their explanations will be omitted.

すなわち、本実施例においては位相比較器１３の出力に
基づき、チャネルの切換りを確実に検出するロックはず
れ検出回路２０をＰＬＬｌ０内に設け、咳ロックはすれ
検出回路２０の検出出力をマイクロプロセッサ１に人力
するとともに、マイクロプロ２ソサ１では上記検出出力
が入力されたときのみ二、プログラマブル分周器１３内
の記憶情報をリフレッシュする分周数情報を分周器１３
に再入力する二うにする。That is, in this embodiment, a lock loss detection circuit 20 that reliably detects channel switching is provided in the PLL10 based on the output of the phase comparator 13, and the detection output of the cough lock loss detection circuit 20 is sent to the microprocessor 1. At the same time, the MicroPro 2 Sosa 1 refreshes the information stored in the programmable frequency divider 13 only when the above detection output is input to the frequency divider 13.
Make sure to re-enter it.

第４図は本実施例のりフレラン−動作の具体例−示すタ
イムチャートであり、（ａ）はマイクロプロッサ１から
プログラマブル分周器１２に入力され〜分周数情報、（
ｂ）は外乱、（Ｃ）はロックはずれ検出回路２１）σ）
埼出出カーｒｄ）１寸千七太ル】Ｉす能忘云１７て（ハ
る。この第４図では、時刻ｔ、において外乱が混入し、
この結果ＰＬ、Ｌ１０の出力チャネルＩ０１゛所定のＡ
チャネルから所定外のＢチャネルに移行する過程で、同
期はずれが発生する。この同期はずれはロックはずれ検
出回路２０によって直ぢに検出され、該検出出力は入出
力ポート５を介してマイクロプロセッサＨ７）ＣＰＵ２
に送られる。これにより、マイクロプロセッサ１はプロ
グラマブル分周器１３に対してＡチャネルの分周数に対
応した分周数情報を再出力するリフレッシュ動作を行な
う。この結果、ＰＬＬｌ０のチャネルは再びＡチャネル
に復帰する。FIG. 4 is a time chart showing a specific example of the free run operation of this embodiment, in which (a) is input from the microprocessor 1 to the programmable frequency divider 12, ...
b) is a disturbance, (C) is an out-of-lock detection circuit 21) σ)
In this Figure 4, a disturbance is mixed in at time t,
As a result, PL, output channel I01 of L10゛predetermined A
In the process of transitioning from a channel to a non-predetermined B channel, a loss of synchronization occurs. This out-of-synchronization is directly detected by the out-of-lock detection circuit 20, and the detection output is sent to the microprocessor H7) CPU2 via the input/output port 5.
sent to. As a result, the microprocessor 1 performs a refresh operation to re-output frequency division number information corresponding to the frequency division number of the A channel to the programmable frequency divider 13. As a result, the channel of PLLl0 returns to the A channel again.

このように、本実施例によれば同期はずれが発生しない
状態ではマイクロプロセッサ】からプログラマブル分周
器に対して分周数情報が再出力されないために、従来の
方式のようにノイズ発生によるｂ　／　Ｎ比の劣化を防
止することができ、また外乱によって同期はずれが発生
した場合には速やかにリフレッシュ動作が行なわれるた
めに、所定外のチャネルで動作する期間は極めて短かく
なり、他のチャネルの通信に妨害を与えるというような
事態を好適に防止することができる。As described above, according to this embodiment, when no synchronization occurs, the frequency division number information is not re-outputted from the microprocessor to the programmable frequency divider, so that b/ Since deterioration of the N ratio can be prevented, and refresh operation is performed quickly when synchronization occurs due to disturbance, the period of operation on a non-designated channel is extremely short, and the period of operation on other channels is extremely short. It is possible to suitably prevent situations such as interference with communication.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明にがかるＰＬＬシンセサ
イザ回路のチャネル設定方式によれば、（１）正常な通
信動作を長期間容易に確保することができる。As explained above, according to the channel setting method of the PLL synthesizer circuit according to the present invention, (1) normal communication operation can be easily ensured for a long period of time.

（２）他チャネルに対する妨害を抑制することができる
０ （３）　Ｓ／Ｎ比の劣化を防止することができる。(2) Interference with other channels can be suppressed. (3) Deterioration of the S/N ratio can be prevented.

等の優れた効果を奏する。It has excellent effects such as

【図面の簡単な説明】 第１図は従来装置の構成を示すブロック図、第２図は従
来のリフレッシュ動作を示すタイムチャート、第３図は
この発明を実施するための構成例を示すブロック図、第
４図はこの発明によるリフレッシエ動作例を示すタイム
チャートである０１・・・マイクロプロセッサ、２・・
・ＣＰＵ、３・・・ＲＡＭ、４・・・ＲＯＭ、５・・・
入出力ポート、１０・・・ＰＬＬシンセサイザ回路、１
１・・・■Ｃ０１１２・・・プログラマブル分周器、１
３・・・位相比較器、１４・・・基準発振器、１５・・
・ループフィルタ、２０・・・ロックはずれ検出回路。 代理人弁理士　則近憲佑（ｉｉａ、１名）第１図 第２図 （ｂ） １１　１２　ｊ３ 第３０ 第４図 １Ｂ−４−ｖ３Ｆ−ル[Brief Description of the Drawings] Fig. 1 is a block diagram showing the configuration of a conventional device, Fig. 2 is a time chart showing a conventional refresh operation, and Fig. 3 is a block diagram showing an example of the configuration for implementing the present invention. , FIG. 4 is a time chart showing an example of refresher operation according to the present invention. 01...Microprocessor, 2...
・CPU, 3...RAM, 4...ROM, 5...
Input/output port, 10... PLL synthesizer circuit, 1
1...■C0112...Programmable frequency divider, 1
3... Phase comparator, 14... Reference oscillator, 15...
- Loop filter, 20...Lock loss detection circuit. Representative Patent Attorney Kensuke Norichika (IIA, 1 person) Figure 1 Figure 2 (b) 11 12 j3 30 Figure 4 1B-4-v3F-le

Claims (1)

【特許請求の範囲】[Claims] 入力された分局数情報を記憶し、該記憶した分周故に基
づく分局動作を行なうプログラマブル分周器を有するＰ
ＬＬシンセサイザ回路のチャネル設定方式において、前
記ＰＬＬシンセサイザ回路の同期はずれを検出する同期
はずれ検出回路を具え、前記同期はずれ検出回路が前記
同期はずれを検出し卒場合にのみ前記分周数情報を前記
プログラマブル分周器に再入力するようＫしたことを特
徴とするＰＬＬシンセサイザ回路のチャネル設定方式。P having a programmable frequency divider that stores input division number information and performs division operation based on the stored frequency division reason.
The channel setting method for the LL synthesizer circuit includes an out-of-synchronization detection circuit that detects out-of-synchronization of the PLL synthesizer circuit, and the frequency division number information is set in the programmable manner only when the out-of-synchronization detection circuit detects the out-of-synchronization. A channel setting method for a PLL synthesizer circuit characterized in that K is inputted again to a frequency divider.
JP58178151A 1983-09-28 1983-09-28 Channel setting system of pll synthesizer circuit Pending JPS6072341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58178151A JPS6072341A (en) 1983-09-28 1983-09-28 Channel setting system of pll synthesizer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58178151A JPS6072341A (en) 1983-09-28 1983-09-28 Channel setting system of pll synthesizer circuit

Publications (1)

Publication Number Publication Date
JPS6072341A true JPS6072341A (en) 1985-04-24

Family

ID=16043523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58178151A Pending JPS6072341A (en) 1983-09-28 1983-09-28 Channel setting system of pll synthesizer circuit

Country Status (1)

Country Link
JP (1) JPS6072341A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044215A (en) * 2007-08-06 2009-02-26 Nippon Dempa Kogyo Co Ltd Pll synthesizer circuit
JP2011155599A (en) * 2010-01-28 2011-08-11 Nippon Dempa Kogyo Co Ltd Pll oscillator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044215A (en) * 2007-08-06 2009-02-26 Nippon Dempa Kogyo Co Ltd Pll synthesizer circuit
JP2011155599A (en) * 2010-01-28 2011-08-11 Nippon Dempa Kogyo Co Ltd Pll oscillator circuit

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