JPS5949023A - Synchronizing signal circuit - Google Patents

Abstract

PURPOSE:To avoid the disturbance of synchronism in spite of any dropout, by using a circuit which detects the period of a dropped-out synchronizing signal, a circuit which gates the dropout periods of input and output synchronizing signals of a PLL circuit and a PLL (phase locking loop) circuit having an oscillation frequency of (m) times as high as the input synchronizing signal. CONSTITUTION:A monostable multivibrator circuit 10 is always set as long as the synchronizing signal is normal and then reset until it is set again with the next synchronizing signal after an inversion given immediately after the dropout of a synchronizing signal. Thus an output of (b) is obtained from the circuit 10, and this output undergoes the integration and waveform shaping to obtain a signal of (c). As shown in (d), a gate circuit 2 gates the synchronizing signal of a dropout period by a detecting signal given from a detecting circuit 4. A gate circuit 5 also gates the synchronizing signal of a dropout period for the output synchronizing signal sent from a 1/m-dividing circuit 9 as shown in (e). That is, the phase difference of a phase comparator 6 is eliminated by gating the dropout period for both the signal of (d) and the signal of (e) which are supplied to the circuit 6. As a result, the oscillation frequency sent from a PLL circuit is locked correctly, and the synchronism is never disturbed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronizing signal circuit constituting a PLL (phase locked loop) in a signal processing system circuit.

Configuration of conventional example and its problems In a conventional PLL circuit, a loop is constructed of a phase comparison circuit and a voltage controlled oscillation circuit, and the voltage controlled oscillation circuit generates m times the frequency based on the synchronization signal input to the phase comparison circuit. The oscillation output is divided into (1/rn) by a (17m) frequency dividing circuit.
) and becomes an output synchronization signal, and an output synchronization signal is generated in synchronization with the input synchronization signal. However, if the input periodic signal is missing or discontinuous, the phase comparison circuit
It is determined that the phase of the frequency dividing circuit has shifted, and an error signal is output in the direction of shifting the phase of the voltage controlled oscillation circuit. This had the disadvantage that the frequency of the voltage controlled oscillation circuit, which had been properly locked, would shift, and the synchronization of the PLL circuit would be greatly disrupted.

OBJECTS OF THE INVENTION The present invention is a synchronization signal circuit that normally configures a PLL (phase locked loop) even if the input synchronization signal is missing or discontinuous, and is intended to eliminate the above-mentioned drawbacks.

Structure of the Invention FIG. 1 is a block diagram showing the structure of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the g1 diagram. As shown in FIG. 2a, the input terminal 1 is supplied with discontinuous and missing synchronization signals, and is provided with a detection circuit 4 that detects the period of the discontinuity and missing synchronization signals, and a detection circuit 4 that detects the periods of the discontinuous and missing synchronization signals. The signal causes the PLL circuit 30 input synchronization signal and the PLL
It is comprised of gate circuits 2 and 5 that gate discontinuous and missing periods of the output synchronization signal from the circuit 3, and a PLL (phase locked loop) circuit 3 having an oscillation frequency m times that of the input synchronization signal.

The input terminal 1 is supplied with a discontinuous and missing synchronization signal as shown in FIG.

As shown in FIG. 2, this detection circuit 4 detects discontinuous and missing periods and supplies them to the gate circuits 2 and 5. As shown in FIG. 2C, the gate circuit 2 gates discontinuous and missing periods of the synchronization signal from the input terminal 1, and
The signal is supplied to the LL circuit 3. Also, in the gate circuit 5, as shown in FIG. 2d, the discontinuous and missing periods of the output synchronization signal from the PLL circuit 3 are gated, and the signal is supplied to the PLL circuit 3.

That is, by gating discontinuous and missing periods in the input synchronizing signal of FIG. 2C supplied to the PLL circuit and the output synchronizing signal from the gate circuit 5 of ζ phase 2, FIG. This eliminates the phase difference in the phase comparator circuit.

Therefore, the oscillation frequency from PLL1 path 3 is correctly locked, and the synchronization of PLL1 path 3 is not disturbed.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of FIG. 3. Components that operate in the same way as in FIG. 1 are designated by the same numerals and their explanations will be omitted.

The PLL circuit 3 includes a voltage controlled oscillator circuit 8 that oscillates at a frequency m times that of the input synchronizing signal, and a voltage controlled oscillator circuit 8 that oscillates at a frequency m times that of the input synchronizing signal,
) (17m) frequency divider circuit 9, a phase comparator circuit 6 that detects the phase difference between the frequency-divided output synchronization signal and the input synchronization signal, and a control voltage proportional to the phase difference. It is composed of an LPF (low pass filter) 7. The voltage controlled oscillator circuit 8 has an input synchronization signal (17 m
) Negative feedback is applied in the direction of increasing the phase difference of the output synchronizing signal from the frequency dividing circuit 9.

The missing synchronization signal is supplied to the input terminal 1 as shown in FIG. The signal is supplied to the detection circuit 4.

The monostable multivibrator 1o is set to have a time constant slightly longer than one period of the synchronization signal. Therefore, as long as the synchronization signal shown in FIG. 4a continues, it is always in the cent state.

Furthermore, when the synchronization signal is lost, the monostable multivibrator 10 is in a recent state until it is reversed immediately after and is set again by the next synchronization signal, and the output shown in FIG. 4 is obtained from the monostable multivibrator 10. The output from the monostable multivibrator 10 is integrated by an integrating circuit 11 and waveform-shaped by a waveform shaping circuit 12 to create a signal shown in FIG. 4C.

The output of the waveform shaping circuit 12 is supplied to the gate circuit 2.7. As shown in FIG. 4d, the gate circuit 2 gates the synchronization signal during the period in which the synchronization signal is missing based on the detection signal from the detection circuit 4, and supplies it to the phase comparator circuit 6. Similarly, in the gate circuit 5, as shown in FIG. 6.

That is, by gating discontinuous and missing periods in the input synchronizing signal of FIG. 4d supplied to the phase comparator circuit 6 and the output synchronizing signal from the gate circuit 5 of FIG. 4e, the phase comparator circuit 6 This eliminates the phase difference at Therefore, the oscillation frequency from PLL1 path 9 is correctly locked and the synchronization is not disturbed.

FIG. 5 is also a block diagram showing another embodiment of the present invention,
FIG. 6 is a waveform diagram for explaining the operation of FIG. 5.

Components that operate in the same way as in FIG. 3 are designated by the same reference numerals and their explanations will be omitted.

As shown in FIGS. 6a and 6b, the input terminal 1 is supplied with a synchronization signal with discontinuous and missing vertical periods, and is connected to a frequency separating circuit 13 for detecting the discontinuous and missing vertical periods, and a frequency separating circuit 13 that detects the discontinuous and missing vertical periods. The vertical signal from the circuit 13 connects the gate circuits 2 and 5 to gate the discontinuous and missing vertical periods of the input synchronization signal of the phase comparator circuit 6 and the output synchronization signal from the (17m) frequency divider circuit 9, and the gate circuits 2 and 5 of the input synchronization signal. It is composed of a PLL (phase locked loop) circuit 3 having an oscillation frequency m times higher.

A synchronizing signal with discontinuous or missing vertical periods is supplied to the input terminal 1 as shown in FIGS. 6a and 6b, and the synchronizing signal from the input terminal 1 is supplied to the gate circuit 2 and the frequency separation circuit 13. The frequency separation circuit 13 separates the discontinuous and missing vertical signals of low frequency components and supplies them to the gate circuits 2 and 5, as shown in FIG. 6C.

In the gate circuit 2, as shown in FIG. 6d, the vertical period of the synchronization signal which is discontinuous or missing from the input terminal 1 is gated, and is supplied to the phase comparator circuit 6. Similarly, in the Ushida gate circuit 5, as shown in Fig. 6e (17m)
The frequency separation circuit 1 of the output synchronization signal from the frequency division circuit 9
The vertical period signal from 3 is gated and supplied to the phase comparator circuit 6.

That is, by gating discontinuous and missing vertical periods in the input synchronization signal of FIG. 6d supplied to the phase comparison circuit 6 and the output synchronization signal from the gate circuit 5 of FIG. The phase difference at 6 is eliminated.

Therefore, the oscillation frequency from the PLL1 path is correctly locked, and the synchronization of the PLL circuit 9 is not disturbed.

Effects of the Invention As described above, according to the present invention, even if the input synchronization signal is missing or discontinuous, the oscillation frequency from the PLL circuit is always correctly locked, and the synchronization is not disturbed. Therefore, the operation of the signal processing system circuit associated therewith becomes stable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a waveform diagram illustrating the operation of the blocks in FIG. 1, and FIG. 3 is a block diagram showing a synchronization signal circuit in an embodiment of the present invention. Figure 4 is a waveform diagram to explain the operation of Figure 3,
FIG. 5 is a block diagram of a synchronizing signal circuit in another embodiment of the present invention, and FIG. 6 is a waveform diagram for explaining the operation of FIG. 5. 2.5...Gate circuit, 4...Detection circuit, 10-
・・Monostable multivibrator, 11-1 integral circuit, 1
2... Waveform shaping circuit, 13... Frequency separation circuit, 3... PLL circuit, 6-... Phase comparison circuit, 7...
...LPF, a...-voltage controlled oscillation circuit, 9...
・1 frequency divider circuit. Name of agent: Patent attorney Toshio Nakao? 17511
Figure 1 Figure 2 d) Figure 3/ Figure 4 e-

Claims (2)

[Claims] (1) Detection means for detecting missing and discontinuous periods of the input synchronization signal, first gate means for gating the input synchronization signal by the detection signal, m times the synchronization signal (m
voltage-controlled oscillation means that oscillates at a frequency of (is a positive number); frequency-dividing means that divides the output of the voltage-controlled oscillation means into (17m); and frequency-dividing means that divides the output of the frequency-dividing means by the detection signal. Synchronization characterized in that a phase-locked loop is configured by a second gate means and a phase comparison means for performing a phase comparison between the output signal of the second gate means and the output signal of the first gate means. signal circuit. (2) The synchronization signal circuit according to claim 1, wherein the detection means is constituted by a monostable multivibrator having a time constant slightly longer than one period of the synchronization signal. 0) The synchronization signal circuit according to claim 1, wherein the detection means is constituted by a frequency separation circuit that detects the vertical signal from the synchronization signal.