JPS6072302A - Semiconductor switch - Google Patents

Abstract

PURPOSE:To suppress the reflection of a switch-on condition and to reduce a loss by connecting a microstrip line indicating an inductive reactance to an FET gate electrode. CONSTITUTION:An input-output line is formed by connecting microstrip lines 6 and 6 constituted on a semiconductor substrate 1 with the drain electrode 4 and source electrode 3 of an FET2 constituted on the same substrate 1. Moreover, the electrodes 3 and 4 are connected with each other by means of a microstrip line 7 constituted on the same substrate 1 and a bias circuit 8 which impresses a bias voltage upon a gate electrode 5 is installed. Then a reactance load 14 composed of a microstrip line constituted on the same substrate 1 as the one to which the FET2 is installed is connected with the electrode 5. As a result, the reflection of a switch-on condition is suppressed and a loss can be reduced without giving any influences to the high isolation of a switch-off condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improving the performance of a semiconductor Hayabusa switch using a field effect transistor (hereinafter abbreviated as FFtT) as a control element.

[Prior Art] □: Figure 1 shows a conventional example of a semiconductor switch comprising an FET and a microstrip line on one semiconductor substrate. □For simplicity, we will introduce a single-pole single-plate
In the diagram, (1) is the semiconductor substrate, 2) is F B T , +31 is the source electrode of FBT, (4) is the drain electrode of FIBT, and (h) is 2
□1,0 game, gate, +6) & i-ka, -4 Seio, earthwork 9.7. . Yo28. See, phiy -7-Z 'Kmlt
The inductor and foot path (8) are for applying bias and voltage to the gate electrode 7+51 (9) are the source electrode (3) and the drain' electrode (4). This is a second bias circuit 2 that sets the voltage to the ground potential in terms of direct current.

These, bias circuit 1 +81, noise circuit 2 (6), have a high impedance line (1 [and...
Consisting of a low isibidance λ line fI+1 for
(A gate bias: as voltage is supplied from the earth terminal 0, and the ground terminal (11 is grounded.

Note that the back surface of the semiconductor substrate +11 is entirely metalized,
It constitutes the ground conductor of the microstrip line.

FIG. 2 is a diagram illustrating the operation of the semiconductor switch shown in FIG. 1. Figure 2(a) shows the gate electrode.

Figure 2(b) shows the OFF state of the switch when a pinch-off voltage is applied, and the ON state of the switch when the gate electrode is set to the ground voltage.
What circuit does it represent, such as showing the state? Here, bias circuit 1 (8) and bias circuit 2 (9) are configured to have a high impedance to the microwave at the design center frequency so as not to affect the microwave circuit. The illustration is omitted here. As shown in Fig. 2(a), when the gate bias force is put into a pinch-off state,
A capacitor having an equivalent capacitance of 9 (OFzT) is formed between the drain and source. Here, the inductor line with electrical length θL is connected between the drain and source (summary z■ because they are connected by force).

zL: Connected by an inductor having the characteristic impedance value of the inductor line (7). Therefore, L in Equation 11 and the amount "FKT" between the drain and source are
If the inductor line (7) is configured to resonate in parallel at the design center frequency, the microwave circuit shown by the equal circuit in Figure 2(a) will reflect most of the incident radio waves and will have high isolation. come to realize the state.

On the other hand, as shown in FIG. 2(b), when the gate bias voltage is set to the ground potential, the resistance, (CF
ET) component. At this time.

Since the drain and source of the inductor line (7) are at substantially the same potential, both ends of the inductor line (7) are excited in the same phase, and the middle of the inductor line (7) becomes an electric wall. Therefore, the inductor line (7) having the electrical length θL has an effect equivalent to that of connecting a septance with an open end of electrical length 0L/ to the source electrode (3) and drain electrode (4). Generally, θL is the electrical length, which is less than 90°, so the above susceptance value is BL=tan(L/
2) −−−−=−−−−−(21L), which is the capacitive susceptance. This is represented by the capacitance OL in FIG. 2(b).

Kokote, θL is sufficiently short and capacitive susceptance value BL
is small, the main line (6
) has little effect on propagating microwaves, but CF
Large L for small ET and high isolation
If this is necessary, θL becomes long, which has the drawback of increasing reflection and loss when the switch is on.

``Summary of the Invention'' This invention was made with the aim of improving these drawbacks, and proposes a semiconductor switch in which a reactive load is connected to the FET gate' electrode to reduce reflection and loss when the switch is on. be.

[Embodiments of the invention] FIG. 3 shows an embodiment of the invention.

Compared to conventional semiconductor switches, the gate electrode (5).

The difference is that a matching line I is connected.

The operation of the embodiment shown in FIG. 3 will be explained using FIG. 4.

FIG. 4(a) shows the circuit in the switch OFF state with the gate bias voltage set to the pinch-off voltage.

The drain-source CFET of F]iiT is F
F! If the gate electrode is located at the center of T, the drain, gate-to-gate, and source-to-gate V capacitances can be regarded as 1'.20 FETs, respectively, as shown in FIG. 4(,).

Here, the electrical length θM of the matching microstrip line I
is less than 180° and more than 90°, and the inductive susceptance B
Load M onto the gate electrode.

In other words, BM is BM=-tan(θM)・・・・・・・・・・・・・・・
...+31M zM: Given by the characteristic impedance of the matching inductor line +141. This is shown by the inductance IIM in the circuit shown in FIG. 4(a).

This inductive susceptance is loaded outside the closed loop of the parallel resonant circuit consisting of the drain-source capacitance of F'ET and the inductor line (7).

It does not affect this resonant circuit.

That is, even if the matching line I is loaded, the semiconductor switch according to the present invention can achieve high isolation comparable to that of the conventional semiconductor switch.

On the other hand, in the switch ON state shown in FIG. 4 (1)), the capacitive susceptance Bl due to the inductor line (7) and the inductive susceptance B due to the matching line f14) are loaded in parallel on the main line. Ru.

Here, PF! Since the drain-source resistance RPET of T is generally sufficiently small, several ohms or less, if the electrical length θM of the matching line I is appropriately selected, the inductor line (7
) can create a parallel resonance state.

That is, the electrical length θM of the matching line I at this time is (2
) is given by Equation (3).

In this state, there is no need for an unnecessary sassflice that is loaded in parallel on the main line (6) when the switch is in the ON state.

It is possible to improve reflection characteristics and reduce loss.

Incidentally, in the above description, the present invention was applied to a single-pole single-plate switch (8PST switch), but it goes without saying that it can also be applied to a single-pole multi-plate switch (SPMT switch).

Furthermore, it may be used in a phase shifter configured by combining single-pole multi-plate switches (SPDT switches).

[Effects of the Invention] As explained above, this invention provides Fl! By connecting a microstrip line exhibiting inductive reactance to the iT gate electrode, it is possible to suppress reflection in the ON state of the switch without affecting the high isolation of the switch 97F state, thereby reducing loss.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional single-pole single-plate switch, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. 3 is a diagram showing the structure of a conventional single-pole single-plate switch. FIG. 1 is a diagram showing an embodiment of a semiconductor switch of the present invention. FIG. 4 is an explanatory diagram of the operation of FIG. 3. In the figure, (1) is a semi-integral base plate, (2) is F ICT,
(31 is the source electrode, (4) is the drain electrode, (5) is the gate electrode, (6) is the main line, (7) is the inductor line, (8) is the bias circuit 1. +91 is the bias circuit 2
．． (11 is a high impedance line for Bytes, αυ is a low impedance line for bias, α is a bias terminal, and Ql is a grounding terminal. α is a matching line. In Figure 9, the same or equivalent parts are indicated with the same reference numerals. Agent Masuo Oiwa Figure 1 I3 Second Introduction (α) Figure 4 (0L)

Claims (1)

[Claims] The drain electrode and the source electrode of the field effect transistor formed on a semiconductor substrate are connected to the IJ tube line (micrometers) formed on the same semiconductor substrate as an input/output line, and the drain and source electrodes of the field effect transistor are connected to each other. In a semiconductor switch, the gate electrode is connected to the semiconductor switch by a microstrip line formed on the same semiconductor substrate, and is further provided with a bias circuit for applying a bias voltage to the gate electrode of the field effect transistor. A semiconductor switch characterized in that a reactive load consisting of a microstrip line configured on the same substrate as a field effect transistor is connected.