JP4122600B2 - Field effect transistor and semiconductor circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor (hereinafter referred to as FET) having an expanded impedance variable function, or a semiconductor circuit such as a semiconductor phase shifter or semiconductor amplifier using the FET as a circuit element.
[0002]
[Prior art]
An FET and a semiconductor circuit using the FET are widely used in various devices such as a microwave band and a millimeter wave band, and are applied to the fields of mobile communication, in-vehicle, and satellite communication. FIG. 28 shows an example of a metal pattern structure of a semiconductor circuit called a switched line type phase shifter configured using a conventional FET. The configuration of this figure is disclosed in “X-band 5-bit monolithic GaAsFET phase shifter”, Iyama et al.
[0003]
The phase shifter shown in this figure is composed of an input line 1, an output line 2, two SPDT switches 3 and 4, a reference transmission line 5 and a delay transmission line 6, and a function for realizing two phase states. have. The SPDT switch 3 on the input side includes two FETs Q1 and Q2 and two resonance inductor lines 7 connected between the drain and the source. The input line 1 is used as a reference transmission line 5 or a delay transmission line 6. It is means for selectively connecting to either of the above. On the other hand, the SPDT switch 4 on the output side is composed of two FETs Q3 and Q4 and two resonant inductor lines 7 connected between the drain and source in the same manner as the SPDT switch 3 described above. 2 is a means for selectively connecting 2 to either the reference transmission line 5 or the delay transmission line 6. A bias is applied to the FETs Q1 to Q4 from the outside via the gate bias terminal 8, but a bias circuit for that purpose is not shown here.
[0004]
The structure of the FET will be described in more detail. Since the four FETs have the same structure, the FET Q1 is taken up here and an example of the electrode structure is shown in FIG. A drain electrode finger 9 and a source electrode finger 10 are formed in a finger-cross manner, and a gate electrode finger 11 is disposed between the drain electrode finger 9 and the source electrode finger 10. The gate electrode fingers 11 are connected to each other by a gate connection wiring 12, drawn to the outside, and connected to the gate bias terminal 11. Further, in order to avoid competition / interference with the gate connection wiring 12, the source electrode finger 10 is drawn out through the air bridge 13.
[0005]
Next, the operation of the conventional semiconductor phase shifter will be described.
First, in a passing state in which 0V is applied to the gates (G) of the FETs Q1 and Q3 and a pinch-off voltage is applied to the gates (G) of the FETs Q2 and Q4, the drain (D) and source (S) of the FETs Q1 and Q3. As shown in FIG. 30 (a), the resistance is low impedance (ON state) represented by the equivalent resistance 14, while the drain (D) and the source (S) of the FETs Q2 and Q4 are not connected. As shown in FIG. 30B, the capacitive high impedance (OFF state) represented by the equivalent capacitance 15 is obtained. In the ON state, the drain electrode (D) and the source electrode (S) have the same potential across the surface and become low resistance, and the influence of the resonance inductor line 7 remains. On the other hand, in the OFF state, the drain electrode (D) and the source electrode (S) are cut off at the frequency at which the capacitances of the FETs Q2 and Q4 and the resonance inductor line 7 connected to each FET resonate in parallel. Become. Therefore, between the input line 1 and the delay transmission line 6 and between the delay transmission line 6 and the output line 2 are cut off, while the FETs Q1 and Q3 are conductive, so that they are incident from the input line 1. The signal appears on the output line 2 through the reference transmission line 5.
[0006]
Next, the bias applied to each FET is reversed. In this case, contrary to the above, between the input line 1 and the reference transmission line 5 and between the reference transmission line 5 and the output line 2 are interrupted. At this time, since the FETs Q2 and Q4 have low impedance, the signal incident from the input line 1 passes through the delay transmission line 6 and appears on the output line 2. The delay transmission line 6 has a longer electrical length than the reference transmission line 5, and therefore when the SPDT switches 3 and 4 are both switched to the reference transmission line 5 side compared to when the SPDT switches 3 and 4 are switched to the reference transmission line 5 side. This increases the propagation delay in the phase shifter. As described above, by changing the bias voltage applied to the four FETs, the passing terminals of the SPDT switches 3 and 4 are switched, and the delay phase is changed by switching the signal propagation path to operate as a phase shifter. .
[0007]
[Problems to be solved by the invention]
In the configuration in which the phase control action is performed by combining the FET such as the resonant inductor line, the reference transmission line, the delay transmission line and the like as in the prior art described above, a line structure is required. A substrate area corresponding to the occupied area is required, and there is a problem that the circuit scale and the device are increased. In addition, since the inductor line is provided outside the FET, radio wave leakage is likely to occur due to coupling between adjacent inductor lines, and the electrical problem that the switching characteristics and phase shifter performance deteriorate due to the interference action. there were. These problems have become more prominent in multi-bit phase shifters and the like that need to realize a large number of phase states.
[0008]
The present invention has been made to solve the above-described problems, and expands the impedance variable function of the FET and reduces the size of a semiconductor circuit such as a semiconductor phase shifter and a semiconductor amplifier configured by using this function. The purpose is to make it multifunctional.
[0009]
[Means for Solving the Problems]
In the FET according to the first invention, one end is bridge-connected to one of the drain electrode and the source electrode by a wiring method that does not cause competition or contact with the gate wiring, and the other end is the same as the one end. A waveguide finger connected to the other electrode in a bridge connection or extended structure, and 2 in the length direction between the waveguide finger and the adjacent drain electrode source or source electrode finger. A divided gate electrode finger is provided, and a bias is applied independently to the divided gate electrode finger.
[0010]
In the FET according to the second invention, the waveguide finger is divided into two in the length direction to form a stub shape, and is provided adjacent to the length of the divided waveguide finger. The divided gate electrode fingers are formed so as to have substantially the same length.
[0011]
The FET according to the third invention has a plurality of waveguide fingers, and the lengths of the divided gate electrode fingers provided adjacent to each of the waveguide fingers are different from each other. To do.
[0012]
The FET according to the fourth invention is characterized in that the FETs according to the first to third inventions are connected in series so that the drain electrode or the source electrode is electrically connected to each other.
[0013]
The FET according to the fifth invention has three waveguides extending from one of the drain electrode and the source electrode and bridge-connected to the other by a wiring method that does not cause competition or contact with the gate wiring. A gate electrode finger is provided between the waveguide fingers, and the width of the other waveguide finger is wider than the width of the central waveguide finger.
[0014]
The FET according to the sixth invention includes three waveguides extending from one of the drain electrode and the source electrode and bridged to the other by a wiring method that does not cause competition or contact with the gate wiring. A gate electrode finger is provided between the waveguide fingers, and the central waveguide finger is divided into two to form a stub, and the width of the central waveguide finger Is wider than the width of other waveguide fingers.
[0015]
The FET according to the seventh invention is provided with an electrode finger of the same type as the finger so as to be in parallel with the drain electrode finger or the source electrode finger arranged on the outermost side, and the plurality of drain electrode fingers or A gate electrode finger is provided between the source electrode fingers.
[0016]
A semiconductor circuit according to an eighth invention is characterized in that a plurality of FETs according to the first to seventh inventions are connected via a line having a length of ¼ wavelength at an approximate required frequency. .
[0017]
A semiconductor circuit according to a ninth invention is characterized in that the gate electrode fingers of the plurality of FETs according to the first to seventh inventions are connected to each other.
[0018]
The semiconductor circuit according to the tenth invention is characterized in that the drain electrode or the source electrode of the FET according to the first to seventh inventions is connected to each of two output terminals to which the power of the hybrid coupler is distributed. And
[0019]
A semiconductor circuit according to an eleventh invention is characterized in that the FET according to the present invention is provided in a reference phase side transmission line and a delay phase side transmission line of a line switching type semiconductor phase shifter.
[0020]
A semiconductor circuit according to a twelfth aspect of the present invention is characterized in that two FETs according to the seventh aspect of the present invention are used and their drain electrodes or source electrode fingers are connected to each other.
[0021]
According to a thirteenth aspect of the present invention, there is provided a semiconductor circuit using the FET according to the present invention as a part of a matching circuit.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the structure similar to the prior art example shown by FIG. 28, FIG. 29, or a corresponding structure, and description is abbreviate | omitted.
[0023]
Embodiment 1 FIG.
FIG. 1 is an FET configuration diagram showing Embodiment 1 of the present invention according to the first invention. The FET shown in this figure has a first waveguide finger 16 disposed in the center thereof, and both ends thereof are connected to a drain electrode (D) and a source electrode via an air bridge 13 so as not to compete with the gate connection wiring 12. Connected to (S). Between the first waveguide finger 16 and the source electrode finger 10 adjacent thereto, a first adjacent gate electrode finger 17 on the source electrode (S) side and a second adjacent gate electrode on the drain electrode (D) side. Fingers 18 are provided and electrically connected to the first gate bias terminal 19 and the second gate bias terminal 20 through the gate connection wiring 12, respectively.
[0024]
FIG. 2A shows an equivalent circuit in a state where 0 [V] is applied to all the gates of the FET shown in this figure. In this case, since the gate electrode finger 11 and the channel immediately below the first and second adjacent gate electrode fingers 17 and 18 become conductive, the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16. Are at the same potential. Therefore, the part provided with these fingers acts as a single-sided conductor, and in this case, it is represented by an equivalent resistance 14-1 having a minute resistance. As a result, the FET functions as a transmission path as a whole, and a passage state is established between the drain electrode (D) and the source electrode (S) of the FET.
[0025]
On the other hand, FIG. 2B shows an equivalent circuit in a state where a bias voltage corresponding to the pinch-off voltage is applied to all the gates of the FET shown in FIG. Since the gate electrode finger 11 and the channel immediately below the first and second adjacent gate electrode fingers 17 and 18 are blocked, the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16 are independent circuits. Acts as an element. At this time, the space between the drain electrode finger 9 and the source electrode finger 10 is represented by an equivalent capacitance 15 as in the case of the conventional FET shown in FIG. The first waveguide finger 16 is represented as an independent waveguide conductor 21-1. As a result, the circuit exhibits inductive reactance at a frequency lower than the parallel resonance frequency of the inductance and the capacitance exhibited by the waveguide conductor. In addition, the circuit exhibits capacitive reactance at frequencies higher than the parallel resonance frequency.
[0026]
Further, an equivalent circuit in a state where 0 [V] is applied to the first gate bias terminal 19 of the FET shown in FIG. 1 and a bias voltage corresponding to the pinch-off voltage is applied to the second gate bias terminal 20 is shown in FIG. Shown in In this case, since only the channel immediately below the gate electrode finger 11 and the first adjacent gate electrode finger 17 is conductive, the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16 are adjacent to each other. Only the portion along the gate electrode finger 17 has the same potential. Therefore, unlike the case shown in FIG. 2A, only the portion provided with these fingers acts as a single-surface conductor, and only this portion is a low resistance transmission line represented by the equivalent resistance 14-2. Function as. On the other hand, since the channel immediately below the second adjacent gate electrode finger 18 is blocked, the portion along the second adjacent gate electrode finger 18 of the first waveguide finger 16 functions as an independent circuit element, and the independent waveguide. Appears as conductor 21-2. However, the length is shorter than the entire length of the first waveguide finger 16. Here, since both ends of the independent waveguide conductor are excited in substantially the same phase, this portion is equivalently displayed as the open end stub 22 equivalently as shown in FIG. Therefore, when the electrical length of this portion is shorter than ¼ wavelength, a capacitive susceptance is loaded, and beyond this, an inductive susceptance is loaded at a length of ½ wavelength.
[0027]
As described above, the impedance of the FET of this embodiment can be changed to three types by switching the bias applied to the gate bias terminal. Accordingly, three different passing phases can be obtained, and a small phase shifter can be realized by using these as phase control elements. Here, since the waveguide finger, which is a determinant of impedance, is formed in the FET, the pattern is not occupied outside the FET, so that the circuit is small, and a circuit constituted by using a plurality of these can be miniaturized. Further, since this FET configuration prevents the coupling between waveguide fingers as line elements, leakage and coupling of radio waves when using a plurality of FETs can be reduced. Furthermore, in the ON state of the FET in which all applied biases are set to 0 [V], the above line element becomes a part of the conduction part (drain-source transmission line) of the FET and does not become a stub as a reflection source. Good reflection characteristics can be realized in the state. In addition, since susceptance loading according to not only the length of the waveguide finger but also the length of the first and second adjacent gate electrode fingers is possible, the size of the FET, the drain electrode finger, and the source electrode finger There is an advantage that the impedance can be set independently of the shape, number, etc., and circuit characteristics corresponding to the required performance can be realized. In particular, it is possible to load a very small susceptance by making the length of the second adjacent gate electrode finger very short, which is effective for realizing a phase shifter with a small amount of phase shift.
[0028]
In the present invention, since the drain and source constituting the FET perform an electrically equivalent function, the same effect as in the above description can be obtained even if the drain and source in the above configuration and description are reversed. Similarly, it is apparent that the same effect as described above can be obtained even if the drain electrode finger and the source electrode finger are reversed.
[0029]
Embodiment 2. FIG.
FIG. 3 is an FET configuration diagram showing a second embodiment of the present invention according to the first invention. In the first embodiment, the gate electrode finger 11 has a different length from the first and second adjacent gate electrode fingers 17 and 18. However, in this embodiment, the gate electrode finger 11 is also divided, and the drain electrode (D) side portion is controlled simultaneously with the second adjacent gate electrode finger 18 and the source electrode (S) side portion is controlled. Control is performed simultaneously with the adjacent gate electrode finger 17. In this case, when the same bias is applied to all the gates, the equivalent circuits shown in FIGS. 2A and 2B are realized in the same manner as in the first embodiment. Furthermore, when a bias voltage corresponding to the pinch-off voltage is applied to the first gate bias terminal 19 and 0 [V] is applied to the second gate bias terminal 20, the equivalent circuit shown in FIG. In this case, the equivalent resistance 14-1 is formed on the drain (D) side, and the parallel circuit of the independent waveguide conductor 12-1 and the equivalent capacitance 15-1 is formed on the source (S) side. . On the other hand, in the state where the applied bias is reversed, 0 [V] is applied to the first gate bias terminal 19 and the bias voltage corresponding to the pinch-off voltage is applied to the second gate bias terminal 20, as shown in FIG. An equivalent circuit is realized. In this case, the equivalent resistance 14-2 is formed on the source (S) side, and a parallel circuit of the independent waveguide conductor 21-2 and the equivalent capacitance 15-2 is formed on the drain (D) side. . Accordingly, four different passing phases can be obtained by appropriately selecting the lengths of the first and second adjacent gate electrode fingers 17 and 18.
[0030]
Embodiment 3 FIG.
FIG. 5 is an FET configuration diagram showing Embodiment 3 of the present invention according to the second invention. The waveguide finger is divided into two in the length direction to form a stub shape to form the first divided waveguide finger 23 and the second divided waveguide finger 24, and the length of the divided waveguide finger. And the lengths of the divided first adjacent gate electrode 17 and second adjacent gate electrode 18 provided adjacent thereto are made substantially equal. As a result, the open-ended stub 22 can be realized together with the equivalent resistance 14 in the FET as in the equivalent circuit shown in FIG. 6, so that a relatively large capacitive susceptance can be easily realized.
[0031]
Embodiment 4 FIG.
FIG. 7 is an FET configuration diagram showing Embodiment 4 of the present invention according to the second invention. Compared to the third embodiment, the third gate bias terminal 25 for independently controlling the first adjacent gate electrode finger 17 is provided. As a result, as shown in FIG. 8, in addition to the case of the third embodiment, there is an advantage that a different susceptance can be loaded. Here, in order to avoid congestion of the gate connection wiring, the case where the fourth gate bias terminal 26 is provided separately is shown.
[0032]
Embodiment 5. FIG.
FIG. 9 is an FET configuration diagram showing Embodiment 5 of the present invention according to the third invention. Compared to the first and second embodiments, the second waveguide finger 27 is further provided, and the second adjacent gate electrode finger 18 having a divided structure provided adjacent to each waveguide finger. And third adjacent gate electrode fingers 28 have different lengths, and second and third gate bias terminals 20 and 25 for individually controlling them are provided. As described above, since a plurality of controllable waveguide fingers are provided, more impedance states can be realized as compared with the first and second embodiments without increasing the FET size. Note that although the number of waveguide fingers is two here, the present invention is not limited to this, and a larger number of waveguide fingers may be provided together with a larger number of drain electrode fingers and source electrode fingers.
[0033]
Embodiment 6 FIG.
FIG. 10 is an FET configuration diagram showing Embodiment 6 of the present invention according to the fourth invention. Compared to the case of the fifth embodiment, a fourth gate bias terminal 26 is further provided so that an individual bias can be applied to the fourth adjacent gate electrode finger 29, and an independently controllable waveguide finger portion is added. It is. As a result, a larger number of phase states can be realized without increasing the size of the FET.
[0034]
Embodiment 7 FIG.
FIG. 11 is an FET configuration diagram showing Embodiment 7 of the present invention according to the fourth invention. Here, as an example, two FETs Q1 and Q2 according to the present invention relating to the fourth embodiment are used, and the source electrode S1 and the drain electrode D1 are connected in series so as to be electrically connected to each other. Since it is possible to provide more controllable electrode fingers in a narrow area, a greater number of impedance states can be realized. In addition, since periodic impedance discontinuity can be realized, it is possible to realize frequency response characteristics corresponding to the shape. In the above example, the FET according to the fourth embodiment has been described. However, the present invention is not limited to this, and any FET of the first to sixth embodiments may be used.
[0035]
Embodiment 8 FIG.
FIG. 12 is an FET configuration diagram showing an eighth embodiment of the present invention according to the fifth invention. The third waveguide finger 30 extending from the drain electrode (D) and connected to the source electrode (S) is extended from the source electrode (S) so as not to cause competition or contact with the gate wiring. A fourth waveguide finger 31 bridged to the drain electrode (D) via the air bridge 13 and the two waveguide fingers are provided between the two waveguide fingers, and the air bridge 13 is connected to the drain electrode and the source electrode at both ends. The second gate bias terminal 20 includes three waveguide fingers of the fifth waveguide finger 32 connected via or directly, and a fifth adjacent gate electrode finger 33 is provided between the waveguide fingers. More bias is applied. Further, the width of the other waveguide fingers is made wider than the width of the center fifth waveguide finger 32. In this configuration, since the conductor portion between the drain and source electrodes that does not exhibit reactance characteristics is wide, the resistance between these is low. Therefore, an FET with a small passage loss is realized.
[0036]
Embodiment 9 FIG.
FIG. 13 is an FET configuration diagram showing Embodiment 9 of the present invention according to the fifth invention. Compared to the eighth embodiment, the length of the fifth adjacent gate electrode finger 33 is shortened. Thereby, it is possible to realize two different loading susceptances with small parasitic resistance by changing the applied bias.
[0037]
Embodiment 10 FIG.
FIG. 14 is an FET configuration diagram showing Embodiment 10 of the present invention according to the sixth invention. A sixth waveguide finger 34 extending from the drain electrode (D) and connected to the source electrode (S) via the air bridge 13, and a drain electrode (D extending from the source electrode via the air bridge 13, D ) Connected to the seventh waveguide finger 35, and a third waveguide finger provided between the two waveguide fingers, one end of which is electrically connected to the drain electrode and the source electrode via the air bridge 13, respectively. Fourth divided waveguide fingers 36 and 37 are provided, and a gate electrode finger is provided between the waveguide fingers so that a bias is applied independently from the first and second gate bias terminals 19 and 20. Furthermore, the width of the central waveguide finger is formed wider than the width of the other waveguide fingers. With this configuration, since the stub can be configured with a wide strip conductor, a relatively large capacitive susceptance can be realized.
[0038]
Embodiment 11 FIG.
FIG. 15 is an FET configuration diagram showing Embodiment 11 of the present invention according to the seventh invention. Inside, a first waveguide finger 16 is provided, and an external electrode finger 39 of the same type as the above finger is provided in parallel with the outermost source electrode finger 38 disposed at the outermost part, and An external gate electrode finger 40 is provided between the plurality of source electrode fingers. In this configuration, according to the bias applied from the first and second gate bias terminals 19 and 20, the conventional capacitor consisting of the equivalent capacitor 15-1 shown in FIG. In addition to the similar parallel circuit, as shown in FIG. 16B, an equivalent capacitor 15-2 can be realized by the external electrode finger 39 functioning as a tip open stub. As a result, an inverted L-shaped circuit composed of capacitance and inductance can be formed by the FET itself, and there is an effect that a small filter circuit with a small parasitic content can be realized.
[0039]
Embodiment 12 FIG.
FIG. 17 is an FET configuration diagram showing Embodiment 12 of the present invention according to the seventh invention. Unlike the eleventh embodiment, the inside has an electrode finger structure similar to that of a conventional FET as shown in FIG. 29, for example, and an outer electrode finger 39 using a folded structure using an air bridge 13 on the outer side. -1, 39-2 and external gate electrode fingers 40-1, 40-2. FIG. 18 shows an equivalent circuit when a pinch-off voltage is applied to the first and second gate bias terminals 19 and 20 at a frequency at which the entire length of the external electrode fingers 39-1 and 39-2 is longer than a quarter wavelength. Shown in In this case, a high-pass inverted L circuit composed of the equivalent capacitor 15 and the equivalent inductor 41, which was difficult to realize with the FET according to the eleventh embodiment, can be newly realized.
[0040]
Embodiment 13 FIG.
FIG. 19 is a semiconductor circuit configuration diagram showing Embodiment 13 of the present invention according to the eighth invention. Here, as a plurality of field effect transistors according to the present invention, two FETs Q1 and Q2 according to the first embodiment are connected via a first line 42 having a length of ¼ wavelength at a substantially required frequency. . In this configuration, the effect of the first line 42 can cancel the reflection in a state where the susceptance or reactance is loaded, and a semiconductor circuit with good reflection characteristics can be realized. The important point here is that in the FET according to the present invention, in the so-called ON state, the reflection is only due to the resistance component and is extremely small. Therefore, it is not necessary to consider the adverse effects of reflection for one of the two phase states. For this reason, the configuration shown here realizes a phase control circuit with good reflection in both of the two phase states. The FET is not limited to this, and may be another FET according to the present invention.
[0041]
Embodiment 14 FIG.
FIG. 20 is a semiconductor circuit configuration diagram showing Embodiment 14 of the present invention according to the ninth invention. Here, as the plurality of field effect transistors, FETs Q1 and Q2 according to the first embodiment are used, connected to each other via the first line 42, and the same kind of gate electrode fingers are electrically connected to each other. Thus, the bias is applied collectively from the first and second gate bias terminals 19 and 20. Since a plurality of adjacent FETs are integrated, the semiconductor circuit can be further reduced in size.
[0042]
Embodiment 15 FIG.
FIG. 21 is a semiconductor circuit configuration diagram showing Embodiment 15 of the present invention according to the tenth invention. As the FET having the configuration described in the above-described example, each of the two output terminals 44 to which the power of the hybrid coupler 43 is distributed is used as the drain electrode (D of the FETs Q1 and Q2 according to the fifth embodiment having the configuration illustrated in FIG. And the source electrode (S) is connected to the via hole 45 and grounded. Since reflection to the input side can be reduced by utilizing the power combining characteristic of the hybrid coupler 43, a small semiconductor circuit with low reflection and no influence between FETs can be realized even when a plurality of phase states are realized. . Here, a case where a so-called Lange coupler is used as the hybrid coupler 43 is shown, but the present invention is not limited to this, and other hybrid couplers such as a branch line type hybrid, a rat race circuit, and a broad side coupler may be used. .
[0043]
Embodiment 16 FIG.
FIG. 22 is a semiconductor circuit configuration diagram showing the sixteenth embodiment of the present invention according to the eleventh invention. In the reference transmission path 5 and the delay transmission path 6 of the line switching type semiconductor phase shifter using the conventional FETs Q1 to Q4 having the structure described in the conventional example, for example, in the third embodiment having the configuration shown in FIG. It has a configuration in which a related FET is provided. Since the FET according to the present invention capable of realizing different phase states is provided in the transmission line in the line switching type phase shifter, it is possible to increase the number of bits of the phase shifter without increasing the pattern occupation area. In particular, if a large phase shift amount is realized by the line switching type semiconductor phase shifter and a small phase shift amount is realized by the FET according to the present invention, the advantages of each other can be utilized effectively.
[0044]
Embodiment 17. FIG.
FIG. 23 is a semiconductor circuit configuration diagram showing Embodiment 17 of the present invention according to the twelfth invention. Two FETs Q1 and Q2 according to the seventh embodiment shown in FIG. 11 are used to connect the drain electrodes (D) to each other. By utilizing the fact that one FET according to the present invention can be switched between a passing state, a reactance and a susceptance loaded state, an equivalent inductor 41 and an equivalent capacitance as shown in FIG. 15 is formed so that impedance matching can be achieved by forming a π-type low-pass circuit, and a small low-pass filter can be realized, and the pass amplitude characteristic and the pass phase characteristic are switched by switching the applied bias. The semiconductor circuit which can be realized is realizable.
[0045]
Embodiment 18 FIG.
FIG. 25 is a semiconductor circuit configuration diagram showing Embodiment 18 of the present invention according to the twelfth aspect of the present invention. Two FETs Q1 and Q2 according to the twelfth embodiment shown in FIG. 17 are used to connect the drain electrodes (D) to each other. Utilizing the fact that one FET according to the present invention can switch between a passing state, a reactance, and a susceptance loaded state, a combination of two FETs, as shown in FIG. 26, is composed of an equivalent capacitor 15 and an equivalent inductor 41. A high-pass circuit can be formed so that impedance matching can be achieved, and a small high-pass filter can be realized. In addition, a semiconductor circuit that can switch pass amplitude characteristics and pass phase characteristics by switching the applied bias Can be realized.
[0046]
Embodiment 19. FIG.
FIG. 27 is a semiconductor circuit configuration diagram showing Embodiment 19 of the present invention according to the thirteenth aspect. Here, an amplifier is taken as an example, and the case where the FET according to the invention is used as a part of the input matching circuit is shown. For example, the FET Q1 shown in FIG. 1 according to the first embodiment is connected to the gate of the common-source amplification FET 46 via the first and second matching lines 47 and 48 and the matching stub 49, and the input matching circuit 50 is It is configured. When 0 [V] is applied to all the gates of the FET Q1, this FET portion is in the same state as the transmission line, and the input signal is transmitted to the amplification FET. On the other hand, when a pinch-off voltage is applied only to the second gate bias terminal 20 in this state, for example, a capacitive stub is formed in this FET portion. Therefore, even if the characteristics of the amplification FET change due to temperature change, aging, etc., or even if the characteristics of the amplification FET vary depending on the manufacturing conditions, the impedance characteristics of the input matching circuit can be changed by electrical means. Therefore, it is possible to maintain good matching conditions. As described above, the FET according to the present invention can be used to switch the loading reactance or loading susceptance in an arbitrary range in a stepwise manner, so that the semiconductor circuit can be provided with a function capable of adjusting and controlling the matching characteristics by electric means. In the above embodiment, the case where one FET according to the present invention is used has been described. However, the present invention is not limited to this, and more precise or wide-range compensation can be performed by using a plurality of FETs according to the present invention. In the above embodiment, the FET according to the present invention is used for the input matching circuit of the amplifier. However, the present invention is not limited to this, and an output matching circuit may be used. A mixer, modulator, oscillator, A device such as a multiplier may be used. Further, it is clear that the present invention is effective even when used in a compound semiconductor circuit such as a module or a BFN circuit in which these devices are combined.
[0047]
【The invention's effect】
According to the first invention, one end is bridge-connected to one of the drain electrode and the source electrode and the other end is made the same as the one end by a wiring method that does not cause competition or contact with the gate wiring. A waveguide finger connected to the other electrode in a bridge-connected or extended structure, and in the length direction between the waveguide finger and a drain electrode finger or a source electrode finger adjacent to the waveguide finger. Since the gate electrode finger divided into two is provided and a means for applying a bias independently to the divided gate electrode finger is provided, the impedance exhibited by the FET can be changed by switching the bias applied to the gate bias terminal. It can be changed to 3 types. Accordingly, three or four different passing phases can be obtained, and a small phase shifter can be realized by using these as phase control elements. Here, since the waveguide finger, which is a determinant of impedance, is formed in the FET, the pattern is not occupied outside the FET, so that the circuit is small, and a circuit constituted by using a plurality of these can be miniaturized. Further, since this FET configuration prevents the coupling between waveguide fingers as line elements, leakage and coupling of radio waves when using a plurality of FETs can be reduced. Furthermore, in the ON state of the FET in which all applied biases are set to 0 [V], the above line element becomes a part of the conduction part (drain-source transmission line) of the FET and does not become a stub as a reflection source. Good reflection characteristics can be realized in the state. In addition, since susceptance loading according to not only the length of the waveguide finger but also the length of the first and second adjacent gate electrode fingers is possible, the size of the FET, the drain electrode finger, and the source electrode finger There is an advantage that the impedance can be set independently of the shape, number, etc., and circuit characteristics corresponding to the required performance can be realized. In particular, it is possible to load a very small susceptance by making the length of the second adjacent gate electrode finger very short, which is effective for realizing a phase shifter with a small amount of phase shift.
[0048]
According to the second invention, the waveguide finger is divided into two stubs in the length direction, and the length of the divided waveguide finger is provided adjacent to the stub shape. The divided gate electrode fingers are formed to have substantially the same length. As a result, since the open end stub can be realized, a relatively large capacitive susceptance can be easily realized.
[0049]
Further, according to the third invention, as compared with the case of the first invention, the divided gate is provided with a plurality of waveguide fingers and provided adjacent to each of the waveguide fingers. The electrode fingers have different lengths and are provided with second and third gate bias terminals for individually controlling them. As described above, since a plurality of controllable waveguide fingers are provided, a larger number of impedance states can be realized without increasing the FET size.
[0050]
According to the fourth invention, the FETs according to any one of the first to third inventions are connected in series so that the drain electrodes or the source electrodes are electrically connected to each other, and are controlled in a narrow area. Since the number of possible electrode fingers can be increased, a larger number of impedance states can be realized. In addition, since periodic impedance discontinuity can be realized, it is possible to realize frequency response characteristics corresponding to the shape.
[0051]
Further, according to the fifth aspect of the present invention, it extends from one of the drain electrode and the source electrode and is bridged to the other by means such as via an air bridge so as not to cause competition or contact with the gate wiring. In addition, there are three waveguide fingers, a gate electrode finger is provided between the waveguide fingers, and the width of the other waveguide fingers is wider than the width of the central waveguide finger. is doing. In this configuration, since the conductor portion between the drain and the source is wide, the resistance between them is low. Therefore, an FET with a small passage loss is realized.
[0052]
Further, according to the sixth invention, since the waveguide finger that is divided into two in the middle to form a stub is formed wider than the other waveguide fingers, the stub can be constituted by a wide strip conductor. A relatively large capacitive susceptance can be realized.
[0053]
According to the seventh invention, the external electrode finger of the same type as the finger is provided in parallel with the drain electrode finger or the source electrode finger arranged at the outermost part, and the plurality of drain electrode fingers are provided. Alternatively, by providing an external gate electrode finger between the source electrode fingers and controlling the bias applied to the external gate electrode finger, a capacitive and inductive susceptance can be loaded on the transmission line, Competing with the portion, an inverted L-type filter circuit whose transmission characteristics can be switched can be formed in the transmission line.
[0054]
According to the eighth invention, the plurality of field effect transistors according to any one of the first to seventh inventions are connected via a line having a length of ¼ wavelength at an approximate required frequency. Therefore, reflection in a state where susceptance or reactance is loaded can be canceled, and a semiconductor circuit with good reflection characteristics can be realized.
[0055]
According to the ninth invention, since the gate electrode fingers of the plurality of FETs according to any one of the first to seventh inventions are connected to each other, a plurality of adjacent FETs are integrated. Thus, the semiconductor circuit can be further miniaturized.
[0056]
According to the tenth invention, the drain electrode or the source electrode of the FET according to any one of the first to seventh inventions is connected to each of the two output terminals to which the power of the hybrid coupler is distributed. As a result, it is possible to reduce the reflection to the input side by using the power combiner characteristics of the hybrid coupler. As a result, even when multiple phase states are realized, there is no influence between FETs, and a small semiconductor circuit with low reflection is possible. Become.
[0057]
According to the eleventh invention, the FET according to any one of the first to seventh inventions is provided in the reference phase side transmission line and the delay phase side transmission line of the line switching type semiconductor phase shifter. Thus, it is possible to increase the number of bits of the phase shifter without substantially increasing the pattern occupation area of the line switching type semiconductor phase shifter.
[0058]
Further, according to the twelfth invention, the two FETs according to the seventh invention are used and the drain electrodes or the source electrode fingers are connected to each other. A low-pass or high-pass circuit can be formed so that impedance matching can be achieved, a small filter can be realized, and the pass amplitude characteristics and pass phase characteristics can be switched by switching the applied bias A circuit can be realized.
[0059]
According to the thirteenth invention, the loading reactance or the loading susceptance can be switched stepwise within an arbitrary range by using the FET according to any one of the first to seventh inventions as a part of the matching circuit. The semiconductor circuit can be provided with a function capable of adjusting and controlling the matching characteristics of an amplifier, a mixer, or a complex module combining these by means of electrical means.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a first embodiment of an FET according to the present invention;
FIG. 2 is an equivalent circuit diagram showing the operation of the FET according to the first embodiment.
FIG. 3 is a block diagram showing a second embodiment of the FET according to the present invention.
FIG. 4 is an equivalent circuit diagram showing the operation of the FET according to the second embodiment.
FIG. 5 is a configuration diagram showing a third embodiment of the FET according to the present invention;
FIG. 6 is an equivalent circuit diagram showing the operation of the FET according to the third embodiment.
FIG. 7 is a block diagram showing a fourth embodiment of the FET according to the present invention.
FIG. 8 is an equivalent circuit diagram showing the operation of the FET according to the fourth embodiment.
FIG. 9 is a configuration diagram showing a fifth embodiment of an FET according to the present invention;
FIG. 10 is a configuration diagram showing a sixth embodiment of the FET according to the present invention;
FIG. 11 is a block diagram showing a seventh embodiment of the FET according to the present invention.
FIG. 12 is a configuration diagram showing an eighth embodiment of an FET according to the present invention;
FIG. 13 is a block diagram showing a ninth embodiment of the FET according to the present invention.
FIG. 14 is a configuration diagram showing a tenth embodiment of an FET according to the present invention;
FIG. 15 is a configuration diagram showing an eleventh embodiment of an FET according to the present invention;
FIG. 16 is an equivalent circuit diagram showing the operation of the FET according to the eleventh embodiment.
FIG. 17 is a block diagram showing Embodiment 12 of an FET according to the present invention.
FIG. 18 is an equivalent circuit diagram showing the operation of the FET according to the twelfth embodiment.
FIG. 19 is a block diagram showing a semiconductor circuit according to a thirteenth embodiment of the present invention.
FIG. 20 is a configuration diagram showing a fourteenth embodiment of a semiconductor circuit according to the present invention.
FIG. 21 is a block diagram showing a fifteenth embodiment of a semiconductor circuit according to the present invention.
FIG. 22 is a block diagram showing a sixteenth embodiment of a semiconductor circuit according to the present invention.
FIG. 23 is a block diagram showing a seventeenth embodiment of a semiconductor circuit according to the present invention.
FIG. 24 is an equivalent circuit diagram showing an operation of the semiconductor circuit according to the seventeenth embodiment;
FIG. 25 is a block diagram showing a semiconductor circuit according to an eighteenth embodiment of the present invention.
FIG. 26 is an equivalent circuit diagram showing the operation of the semiconductor circuit according to the eighteenth embodiment;
FIG. 27 is a configuration diagram showing a nineteenth embodiment of a semiconductor circuit according to the present invention.
FIG. 28 is a circuit diagram showing a configuration of a conventional semiconductor phase shifter according to a conventional example.
FIG. 29 is a configuration diagram of a conventional FET in a conventional example.
FIG. 30 is an equivalent circuit diagram showing the operation of a conventional FET.
[Explanation of symbols]
1 input line, 2 output line, 3, 4 conventional SPDT switch, 5 reference transmission line, 6 delay transmission line, 7 resonance inductor line, 8 gate bias terminal, 9 drain electrode finger, 10 source electrode finger, 11 gate electrode Finger, 12 gate connection wiring, 13 air bridge, 14 equivalent resistance, 15 equivalent capacitance, 16 first waveguide finger, 17 first adjacent gate electrode finger, 18 second adjacent gate electrode finger, 19 first gate bias terminal, 20 Second gate bias terminal, 21 Independent waveguide conductor, 22 Open-ended stub, 23 First divided waveguide finger, 24 Second divided waveguide finger, 25 Third gate bias terminal, 26 Fourth gate bias terminal, 27 Second Waveguide finger, 28 third adjacent gate electrode finger, 29 fourth adjacent gate electrode field , 30 Third waveguide finger, 31 Fourth waveguide finger, 32 Fifth waveguide finger, 33 Fifth adjacent gate electrode finger, 34 Sixth waveguide finger, 35 Seventh waveguide finger, 36 Third divided conductor Waveguide finger, 37 Fourth divided waveguide finger, 38 Outermost source electrode finger, 39 External electrode finger, 40 External gate electrode finger, 41 Equivalent inductor, 42 First line, 43 Hybrid coupler, 44 Output terminal of hybrid coupler , 45 via hole, 46 amplifying FET, 47 first matching line, 48 second matching line, 49 matching stub, 50 input matching circuit.

Claims (7)

  One end is connected to one of the drain electrode and the source electrode by a wiring method that does not cause competition or contact with the gate wiring, and the other end is connected or extended in the same manner as the one end. A gate electrode finger having a waveguide finger connected to the other electrode in the structure and having a gate electrode finger divided into two in the length direction between the waveguide finger and a drain electrode finger or a source electrode finger adjacent to the waveguide finger. A field effect transistor characterized in that a bias is applied independently to the divided gate electrode fingers.   The waveguide finger is divided into two in the length direction to form a stub shape, and the length of the divided waveguide finger and the length of the divided gate electrode finger provided adjacent to the waveguide finger are expressed as follows. 2. The field effect transistor according to claim 1, wherein the field effect transistors are formed so as to be substantially equal to each other.   2. The field effect transistor according to claim 1, wherein a plurality of waveguide fingers are provided, and the lengths of the divided gate electrode fingers provided adjacent to the respective waveguide fingers are different from each other. .   There are three waveguide fingers extending from one of the drain electrode and the source electrode and connected to the other by a wiring method that does not cause competition or contact with the gate wiring, and between the waveguide fingers In addition, a gate electrode finger having a configuration in which a bias can be applied from the outside is provided, and the width of the other waveguide finger is wider than the width of the central waveguide finger. Comprising a plurality of field effect transistor according to any one of claims 1 to 3, a semiconductor circuit in which the gate electrode fingers of the field effect transistor, characterized in that connected to each other. 4. A semiconductor circuit comprising: a drain electrode or a source electrode of a field effect transistor according to claim 1 connected to each of two output terminals to which power of a hybrid coupler is distributed. The line switching type semiconductor phase shifter reference phase side transmission line and the delay phase side transmission path, a semiconductor circuit, characterized in that a field effect transistor according to claim 1.

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