JPS6072263A - Writing system for insulation breakdown type memory - Google Patents

Writing system for insulation breakdown type memory

Info

Publication number
JPS6072263A
JPS6072263A JP58178080A JP17808083A JPS6072263A JP S6072263 A JPS6072263 A JP S6072263A JP 58178080 A JP58178080 A JP 58178080A JP 17808083 A JP17808083 A JP 17808083A JP S6072263 A JPS6072263 A JP S6072263A
Authority
JP
Japan
Prior art keywords
voltage
type semiconductor
layer
film
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58178080A
Other languages
Japanese (ja)
Inventor
Takaharu Nawata
名和田 隆治
Noriaki Sato
佐藤 典章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58178080A priority Critical patent/JPS6072263A/en
Publication of JPS6072263A publication Critical patent/JPS6072263A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To enable the reduction in the write voltage by a method wherein a positive voltage is impressed on the Al electrode side, in the titled device having an Si oxide layer, a poly Si film, its oxide film, and the Al electrode on the surface of a substrate. CONSTITUTION:A P type semiconductor diffused layer 2 is provided on the N type semiconductor substrate 1, and an N type semiconductor diffused layer 3 is provided in the layer 2. The Si oxide layer 4, poly Si film 5, and its oxide film 6 are provided thereon, and further the Al electrode 7 is provided. With the electrode 7 side as the positive side, a voltage is impressed by means of a power source 9 in order to utilize the semiconductor device of this construction as the titled device. This system enables the reduction in the breakdown voltage and the decrease in the strength of electric field. In other words, this system can reduce the write voltage for the titled device.

Description

【発明の詳細な説明】 技術分野 本発明は半導体記憶装置の書込み方式に関し、特に、F
ROM(プログラマブルメモリ)として用いるポリシリ
コン酸化膜の絶縁破壊を利用した絶縁破壊形メモリの書
込み方式に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a writing method for a semiconductor memory device, and in particular to a write method for a semiconductor memory device.
The present invention relates to a write method for a dielectric breakdown type memory that utilizes dielectric breakdown of a polysilicon oxide film used as a ROM (programmable memory).

従来技術と問題点 第1図は従来の絶縁破壊形メモリ (以下BICメモリ
と称す)の断面とこれに印加する電圧の電源を示す図で
あシ、第2図はその等価回路図である。従来知られるよ
うに、この構造は、N形半導体基板1上にP形半導体の
拡散層2を設けさらにP形波散層2の中にN形半導体拡
散層3を設け、この上に酸化シリコン(SiO,)4の
層と4000〜5000Aの厚みのドーピングされたポ
リシリコン膜5と該ポリシリコン膜5の酸化膜6を設け
、さらに電極としてアルミニウム電極7を設ける。
Prior Art and Problems FIG. 1 is a diagram showing a cross section of a conventional dielectric breakdown type memory (hereinafter referred to as BIC memory) and the power source of the voltage applied thereto, and FIG. 2 is an equivalent circuit diagram thereof. As is conventionally known, in this structure, a P-type semiconductor diffusion layer 2 is provided on an N-type semiconductor substrate 1, an N-type semiconductor diffusion layer 3 is provided in the P-type scattering layer 2, and a silicon oxide layer is formed on top of the N-type semiconductor diffusion layer 3. A layer of (SiO,) 4, a doped polysilicon film 5 having a thickness of 4000 to 5000 Å, and an oxide film 6 of the polysilicon film 5 are provided, and an aluminum electrode 7 is further provided as an electrode.

BICメモリとして利用するために従来は図に示すよう
な極性にて電圧を印加する電源8が設けられ、負の印加
電圧を徐々に上昇し成る電圧にてポリシリコン酸化膜6
に絶縁破壊を起こさせることによシメモリとして利用す
る方式が行われてきた。
Conventionally, in order to use it as a BIC memory, a power supply 8 is provided that applies a voltage with the polarity shown in the figure, and the polysilicon oxide film 6 is heated by gradually increasing the negative applied voltage.
A method has been used to use it as a memory by causing dielectric breakdown.

これは第2図に等何回路で示すように、NP接合部分を
等価的にダイオード21で、ポリシリコン部分を等価的
に寄生抵抗22で、ポリシリコン酸化膜を等価的に容量
23で示すならは、電源8の印加電圧の極性はダイオー
ド21に対して順方向に加えられることを示している1
、シかしながら、すでに知られるように、ダイオードの
インパクト・アイオニゼイシ冒ンは正の印加電圧に対し
てかなシ高い値にあシ、これがためにメモリへの書込み
電圧がかな夛高くなるという問題があった。
As shown in the circuit diagram in Fig. 2, if the NP junction part is equivalently represented by a diode 21, the polysilicon part is equivalently represented by a parasitic resistance 22, and the polysilicon oxide film is equivalently represented by a capacitor 23. 1 indicates that the polarity of the voltage applied to the power supply 8 is applied in the forward direction to the diode 21.
However, as is already known, the impact ionization of diodes tends to be quite high for positive applied voltages, which causes the problem that the write voltage to the memory becomes considerably high. was there.

発明の目的 本発明の目的は絶縁破壊形メモリにおけるポリシリコン
酸化膜の絶縁破壊電圧を低くする、即ち書込み電1圧を
低くすることが可能な絶縁破壊形メモリの書込み方式を
提供することにある。
OBJECTS OF THE INVENTION An object of the present invention is to provide a write method for a dielectric breakdown type memory that can lower the dielectric breakdown voltage of a polysilicon oxide film in the dielectric breakdown type memory, that is, it is possible to lower the write voltage 1 voltage. .

発明の構成 この目的は、本発明によれば、N形半導体基板上にP形
半導体拡散層を設けさらにP形半導体拡散層中にN形半
導体拡散層を有し、さらに酸化シリコン層とポリシリコ
ン膜とその酸化膜とアルミニウム電極によυ構成される
絶縁破壊形メモリに記憶させる書込み方式において、該
アルミニウム電極側に正の電圧を印加することを特徴と
する絶縁破壊形メモリの1込み方式、を提供することに
よシ達成される。
Structure of the Invention According to the present invention, a P-type semiconductor diffusion layer is provided on an N-type semiconductor substrate, an N-type semiconductor diffusion layer is provided in the P-type semiconductor diffusion layer, and a silicon oxide layer and a polysilicon layer are formed. In a writing method for storing data in a dielectric breakdown memory composed of a film, its oxide film, and an aluminum electrode, a single write method of the dielectric breakdown memory is characterized in that a positive voltage is applied to the aluminum electrode side. This is achieved by providing the following.

実施例 第3図は本発明による絶縁破壊形メモリの書込み方式を
示す図である。第3図において絶縁破壊形メモリを構成
する各構成要素(1〜7)は第1図に示す従来形と全く
同様であるが、電源9は従来の方式による極性とは逆に
アルミ電極7側を正側にして電圧印加することを特徴と
する。
Embodiment FIG. 3 is a diagram showing a write method of a dielectric breakdown type memory according to the present invention. In FIG. 3, each component (1 to 7) constituting the dielectric breakdown type memory is exactly the same as the conventional type shown in FIG. The feature is that the voltage is applied with the voltage on the positive side.

第4図は第3図の電気的等価回路図であり、前述したよ
うにNP接合部分を等測的にダイオード21で、ポリシ
リコン部分を等測的に寄生抵抗22で、ポリシリコン酸
化膜を等測的に容量23で示すならば、電源9の印加電
圧の極性はダイオード21に対して逆方向に加えられる
ことを示している。
FIG. 4 is an electrical equivalent circuit diagram of FIG. 3, and as mentioned above, the NP junction part is isometrically connected to a diode 21, the polysilicon part is isometrically connected to a parasitic resistor 22, and the polysilicon oxide film is connected isometrically to the diode 21. Isometrically representing the capacitance 23 indicates that the polarity of the voltage applied by the power source 9 is applied in the opposite direction to the diode 21.

第5,6図は本発明による書込み方式の効果を示すグラ
フである。第5.6図において横軸は各温度に於けるポ
リシリコン酸化膜の厚みTを示し、縦軸は第5図は゛絶
縁破壊の生ずるブレイクダウン電圧(yolt)V、第
6図はそのときの電界強度(MY^)Sを示す。点線社
従来方式を示しアルミ電極側に負の電圧を印加した場合
であり、実線は本発明による方式を示しアルミ電極側に
正の電圧を印加した場合である。グラフより明らかなよ
うに、本発明による方式は酸化膜6の各厚みTにおいて
ブレイクダウン電圧を従来に比べて低くすることができ
、又、電界強度も低く力ることかわかる。即ち本発明の
方式はBICメモリへの書込み電圧を低くすることがで
きる。
5 and 6 are graphs showing the effects of the writing method according to the present invention. In Figure 5.6, the horizontal axis shows the thickness T of the polysilicon oxide film at each temperature, and the vertical axis shows the breakdown voltage (yolt) V at which dielectric breakdown occurs; Electric field strength (MY^)S is shown. The dotted line shows the conventional method and shows the case where a negative voltage is applied to the aluminum electrode side, and the solid line shows the method according to the present invention and shows the case where a positive voltage is applied to the aluminum electrode side. As is clear from the graph, the method according to the present invention can lower the breakdown voltage at each thickness T of the oxide film 6 than the conventional method, and also lowers the electric field strength. That is, the method of the present invention can lower the write voltage to the BIC memory.

発明の効果 本発明によれば絶縁破壊形メモリの絶縁破壊電圧を低く
することができるので書込み電圧を低くすることができ
る。
Effects of the Invention According to the present invention, the dielectric breakdown voltage of the dielectric breakdown type memory can be lowered, so that the write voltage can be lowered.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の1込み方式を示す図、 第2図は第1図の等価回路図、 第3図は不発り」による書込み方式を示す図、第4図は
第3図の等価回路図、および 第5,6図は本発明による書込み方式の効果を示すグラ
フである。 (符号の説明) 1ma、N竪?b道伏其坦 2・・・P形半導体拡散層 3・・・N形半導体拡散層 4・・・酸化シリコン 5・・・ポリシリコン膜 6・・・ポリシリコン酸化膜 7・・・アルミニウム電極 8.9・・・電 源 21・・・等価夕゛イオード 22・・・等価抵抗 23・・・等価容量 特許出願人 富士通株式会社 特許出願代理人 弁理士 青 木 朗 弁理士西舘和之 弁理士内田幸男 弁理士 山 口 昭 之 第1図 :め2図 第3図 第4図 第5図 850850900900(0C) 6図 850850 (6)9霞(0C)
Figure 1 is a diagram showing the conventional 1-input method, Figure 2 is an equivalent circuit diagram of Figure 1, Figure 3 is a diagram showing a writing system based on "unfired", and Figure 4 is an equivalent circuit diagram of Figure 3. , and FIGS. 5 and 6 are graphs showing the effects of the writing method according to the present invention. (Explanation of code) 1ma, N vertical? b Dobukuro 2...P type semiconductor diffusion layer 3...N type semiconductor diffusion layer 4...Silicon oxide 5...Polysilicon film 6...Polysilicon oxide film 7...Aluminum electrode 8.9... Power supply 21... Equivalent diode 22... Equivalent resistance 23... Equivalent capacitance Patent applicant Fujitsu Limited Patent application representative Patent attorney Akira Aoki Patent attorney Kazuyuki Nishitate Patent attorney Yukio Uchida Patent Attorney Akira Yamaguchi Figure 1: Figure 2 Figure 3 Figure 4 Figure 5 850850900900 (0C) 6 Figure 850850 (6) 9 Kasumi (0C)

Claims (1)

【特許請求の範囲】[Claims] 1、N形半導体基板上にP形半導体拡散層を設けさらに
P形半導体拡散層中にN形半導体拡散層を有し、さらに
酸化シリコン層とポリシリコン膜とその酸化膜とアルミ
ニウム電、極によシ構成される絶縁破壊形メモリに記憶
させる書込み方式において、該アルミニウム電極側に正
の電圧を印加することを特徴とする絶縁破壊形メモリの
書込み方式。
1. A P-type semiconductor diffusion layer is provided on an N-type semiconductor substrate, and an N-type semiconductor diffusion layer is provided in the P-type semiconductor diffusion layer, and a silicon oxide layer, a polysilicon film, the oxide film, and an aluminum electrode are formed. A method for writing data into a dielectric breakdown type memory constructed as described above, characterized in that a positive voltage is applied to the aluminum electrode side.
JP58178080A 1983-09-28 1983-09-28 Writing system for insulation breakdown type memory Pending JPS6072263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58178080A JPS6072263A (en) 1983-09-28 1983-09-28 Writing system for insulation breakdown type memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58178080A JPS6072263A (en) 1983-09-28 1983-09-28 Writing system for insulation breakdown type memory

Publications (1)

Publication Number Publication Date
JPS6072263A true JPS6072263A (en) 1985-04-24

Family

ID=16042268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58178080A Pending JPS6072263A (en) 1983-09-28 1983-09-28 Writing system for insulation breakdown type memory

Country Status (1)

Country Link
JP (1) JPS6072263A (en)

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