JPS6072250A - Resin-sealed type semiconductor device - Google Patents
Resin-sealed type semiconductor deviceInfo
- Publication number
- JPS6072250A JPS6072250A JP58181844A JP18184483A JPS6072250A JP S6072250 A JPS6072250 A JP S6072250A JP 58181844 A JP58181844 A JP 58181844A JP 18184483 A JP18184483 A JP 18184483A JP S6072250 A JPS6072250 A JP S6072250A
- Authority
- JP
- Japan
- Prior art keywords
- latex
- resin
- chip
- sealed
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000004816 latex Substances 0.000 claims abstract description 21
- 229920000126 latex Polymers 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000011347 resin Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 150000001732 carboxylic acid derivatives Chemical class 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 15
- 239000003822 epoxy resin Substances 0.000 abstract description 12
- 229920000647 polyepoxide Polymers 0.000 abstract description 12
- 150000001735 carboxylic acids Chemical class 0.000 abstract description 11
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000010306 acid treatment Methods 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 239000000806 elastomer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- BVKZGUZCCUSVTD-UHFFFAOYSA-N carbonic acid Chemical compound OC(O)=O BVKZGUZCCUSVTD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000006082 mold release agent Substances 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、樹脂封止形半導体装置に係り、特に絶縁基
板上に形成された所定回路の全体あるいは一部にラテッ
クスを塗布し、絶縁樹脂で封止される事前に当該部のラ
テックス表面に弾性硬化皮膜を形成させるようにしたも
のである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and in particular to a resin-encapsulated semiconductor device in which latex is applied to all or part of a predetermined circuit formed on an insulating substrate. An elastic hardened film is formed on the latex surface of the part before it is sealed.
一般に、集積回路、トランジスタ、ダイオードおよびこ
れらの部品Ｚセラミック等の絶縁基板上に集積した混成
集積回路は、その回路形成後その全体あるいは一部が熱
硬化性樹脂で封止されており、この封止材料としてはエ
ポキシ樹脂がその特性と価格の面から最も多く用いられ
ている。そして、これらの封止方法としては、例えば集
積回路。In general, hybrid integrated circuits in which integrated circuits, transistors, diodes, and their components are integrated on insulating substrates such as ceramics are encapsulated in whole or in part with a thermosetting resin after the circuit is formed. Epoxy resin is the most commonly used stopper material due to its properties and cost. Examples of these sealing methods include integrated circuits.
トランジスタ、ダイオードはトランスファ成形法、混成
集積回路は粉体樹脂を用いた流動浸漬法が主流となりて
いる。The mainstream is the transfer molding method for transistors and diodes, and the fluidized dipping method using powder resin for hybrid integrated circuits.
一般に市販されている半導体制止材料の組成は。What is the composition of commonly available semiconductor blocking materials?
上記したエポキシ樹脂の他に、硬化剤、充てん剤。In addition to the epoxy resins mentioned above, curing agents and fillers.
着色剤、難燃剤および離型剤等が混成されており。Contains a mixture of colorants, flame retardants, mold release agents, etc.
その熱変形温度が１５０℃〜１８０℃と高く、しかも無
機質光てん剤が全体の７０重量％も混合されているため
、非常に硬い硬化物になっている。The heat deformation temperature is as high as 150°C to 180°C, and 70% by weight of the inorganic photonic agent is mixed in, making it a very hard cured product.
一方、絶縁封止される半導体回路側は、その集積度か年
々あがり複雑な形状のものが多く、比較的弱い力で破壊
されることが多くなってきている。On the other hand, the degree of integration of semiconductor circuits to be insulated and sealed has increased year by year, and many of them have complex shapes, so they are more likely to be destroyed by relatively weak force.
このように複雑な半導体回路側を、上記の硬いエポキシ
樹脂で封止すると、封止時の硬化収縮。When such a complex semiconductor circuit is sealed with the above-mentioned hard epoxy resin, curing shrinkage occurs during sealing.
熱収縮等によりその内部に大きな応力が加わり、部品の
破壊、金線の切断、チップの割れ、あるいは部品か絶縁
基板からはく離する等の問題が起こる。A large stress is applied inside the device due to thermal contraction, causing problems such as destruction of the component, cutting of the gold wire, cracking of the chip, or separation of the component from the insulating substrate.
この発明は、上記問題点罠かんがみて、上記した封止時
の絶縁樹脂の硬化収縮や熱収縮による応力緩和手段とし
℃、封止前に絶縁基板上の所定回路の全体あるいは一部
にラテックスを塗布し、しかも、例えばカルボン酸蒸気
中でその表面を急速に硬化させた後、この弾性硬化皮膜
を封止絶縁樹脂間に介装させることにより、前記応力に
よる部品破壊のない樹脂封止形半導体装置を提供するも
のである。In view of the above-mentioned problems, the present invention uses latex as a means of relieving stress by curing and thermal contraction of the insulating resin during sealing. After applying the coating and rapidly curing the surface in, for example, carboxylic acid vapor, this elastic hardened film is interposed between the sealing insulating resins, thereby producing a resin-sealed semiconductor that does not cause parts to break due to the stress. It provides equipment.
以下、この発明の一実施例について説明する。 An embodiment of the present invention will be described below.
第１図はフラットパッケージ用集積回路の正面図で、こ
の図において−１は銅等のリード、２はチップ４を接着
させるためのダイパッド、３は接続用の金線を示す。FIG. 1 is a front view of an integrated circuit for a flat package. In this figure, -1 indicates a lead made of copper or the like, 2 indicates a die pad for bonding a chip 4, and 3 indicates a gold wire for connection.
また、第２図において、５は前記チップ４の裏面に滴下
したラテックス、６は処理容器Ｉ内に入れたカルボン酸
で、処理容器７内にカルボン酸蒸気（例えば、酢酸蒸気
）６ａが充満されるようになっている。Further, in FIG. 2, 5 is the latex dropped on the back surface of the chip 4, 6 is the carboxylic acid put into the processing container I, and the processing container 7 is filled with carboxylic acid vapor (for example, acetic acid vapor) 6a. It has become so.
第３図は処理容器７で滴下したラテックス５を硬化した
後、絶縁基板Ａ上の回路全体をエポキシ樹脂で絶縁封止
した状態を示す断面図で、この図において、８は封止用
エポキシ樹脂である。要約すれば、エポキシ樹脂による
従来の封止時には、金線３の接続後全体ケ直ちに封止す
るのであるか、この発明の場合は、チップ４０表面に塗
布されたラテックス５を、第２図に示すように処理容器
Ｔ内のカルボン酸６０カルボン酸蒸気６ａに短時間接触
させてラテックス５の裏面を硬化させた後、第３図のよ
うに封止用エポキシ樹脂８で封止する点に特徴がある。FIG. 3 is a cross-sectional view showing the state in which the entire circuit on the insulating substrate A is insulated and sealed with epoxy resin after the latex 5 dropped in the processing container 7 is cured. In this figure, 8 is the epoxy resin for sealing. It is. In summary, in conventional sealing with epoxy resin, the entire body is sealed immediately after the gold wire 3 is connected, but in the case of the present invention, the latex 5 applied to the surface of the chip 40 is sealed as shown in FIG. As shown in FIG. 3, after the back surface of the latex 5 is hardened by contacting the carboxylic acid 60 carboxylic acid vapor 6a in the processing container T for a short period of time, it is sealed with a sealing epoxy resin 8 as shown in FIG. There is.
すなわち、この発明の場合にも、封止用エポキシ樹脂８
の硬化収縮および熱収縮によりチップ４に応力が加わる
ものであるが、チップ４の裏面に塗布したラテックス５
０弾性硬化皮膜が封止用エポキシ樹脂８間に介装され、
かつ、全体がゴム状で軟らかいため、ここで上記の応力
が緩和され、金ＭＡ３の切断やチップ４の割れが防止さ
れることになる。That is, also in the case of this invention, the sealing epoxy resin 8
Stress is applied to the chip 4 due to curing shrinkage and heat shrinkage of the latex 5 applied to the back surface of the chip 4.
0 elastic cured film is interposed between the sealing epoxy resin 8,
In addition, since the entire piece is rubber-like and soft, the above-mentioned stress is alleviated, and cutting of the gold MA 3 and cracking of the chip 4 are prevented.
次に、上記したこの発明による樹脂封止形半導体装置の
実験結果について説明する。Next, experimental results of the resin-sealed semiconductor device according to the present invention described above will be explained.
すなわち、第１図から第３図のようにＬ℃作られラテッ
クス５としてニポール４８５０ （日本ゼオン株式会社
製品）をチップ４の裏面にＯ，Ｏ］ ｇ〜００２ｇ滴下
させ、カルボン酸蒸気６ａ中で５秒間硬化したものと、
ラテックス５を使用しない従来どおりのものｔ、成形圧
力２０ｋｇ／傭２．成形時間３分、成形温度１８０°Ｃ
２後硬化温度１７０℃、硬化時間１６時間の条件下での
トランスファ成形により、各試料２０個について一５０
℃〜＋１８０℃のヒートサイクルを１０回行って得られ
たその時の累積不良結果が第１表に示されている。That is, as shown in FIGS. 1 to 3, Nipole 4850 (product of Nippon Zeon Co., Ltd.) made at L°C and used as a latex 5 was dropped in an amount of O, O] to 0.002 g onto the back surface of the chip 4, and was heated in carboxylic acid vapor 6a. One that was cured for 5 seconds,
Conventional type that does not use latex 5, molding pressure 20 kg / 2. Molding time: 3 minutes, molding temperature: 180°C
2 After transfer molding under the conditions of a post-curing temperature of 170°C and a curing time of 16 hours, 150
Table 1 shows the cumulative failure results obtained by carrying out 10 heat cycles from .degree. C. to +180.degree.
第１表
この第１表から明らかなごとく、ラテックス５を適用し
た試料は、２０個とも全く不良が出てないことが分かる
。なお、採用した不良解析方法として、発煙硝酸により
封止用エポキシ樹脂８を分解して調べたものであり、ま
た、不良個所は金線３の切断であった。Table 1 As is clear from Table 1, none of the 20 samples to which Latex 5 was applied had any defects. The failure analysis method adopted was to decompose the sealing epoxy resin 8 with fuming nitric acid and investigate the failure, and the failure location was the cutting of the gold wire 3.
なお、上記の実施例では、ラテックス５欠塗布後１、そ
の表面をカルボン酸６で硬化させた場合について説明し
たが、これは急速硬化を行わせるための手段であり、し
たがって、特に急速硬化を必要としない場合は、ラテッ
クス５そのものはその水分が蒸発すると、互いに接触融
着する性質を有するので、この性質を応用すれは、必ず
しもカルホン酸６に接触させることはなく、それ自体の
保有する水分の蒸発ヲ行わせれば同様の硬化弾性体皮膜
を得ることができる。In the above example, the case where the latex 5 was not applied 1 and then the surface was cured with carboxylic acid 6 was explained, but this is a means for rapid curing, and therefore, it is particularly important to cure rapidly. If it is not necessary, the latex 5 itself has the property of contacting and fusing with each other when its moisture evaporates, so if you apply this property, you do not necessarily have to bring it into contact with the carbonic acid 6, but rather release the moisture it has. A similar cured elastomer film can be obtained by evaporating the elastomer.
硬化収縮や熱収縮による応力で、半導体回路中の金線の
断線やチップの割れを簡単に防止することができ、それ
だけ歩留りの向上につながるものである。Stress caused by curing shrinkage and thermal shrinkage can easily prevent gold wire breakage and chip cracking in semiconductor circuits, leading to improved yields.
第１図はこの発明の樹脂封止か適用される半導体装置の
要部を示す平面図、第２図はカルボン酸処理状態を示す
この発明の装置の製造途中を示す断面図、第３図はカル
ボン酸処理後の封止樹脂による絶縁封止状態を示す部分
拡大断面図である。
図中、Ａは絶縁基板、５を士ラテックス、６ａはカルボ
ン酸蒸気、８は封止用エポキシ樹脂である。
なお、図中の同一符号は同一または和尚部分を示す。
代理人 大岩増雄 （外２名）
第１図
第２図FIG. 1 is a plan view showing the main parts of a semiconductor device to which the resin sealing method of the present invention is applied, FIG. 2 is a cross-sectional view showing a state of carboxylic acid treatment, and the device of the present invention is in the process of being manufactured. FIG. 3 is a partially enlarged sectional view showing an insulating sealing state with a sealing resin after a carboxylic acid treatment. In the figure, A is an insulating substrate, 5 is latex, 6a is carboxylic acid vapor, and 8 is a sealing epoxy resin. Note that the same reference numerals in the figures indicate the same or similar parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2
Claims (1)
は一部にラテックスを塗布し、その表面に形成させた弾
性硬化皮膜を介して絶縁樹脂で封止したことヲ特徴とす
る樹脂封止形半導体装置。 （２） 所定回路の全体あるいは一部に塗布したラテッ
クスの表面９弾性硬化皮膜は、前記ラテックスをカルボ
ン酸蒸気で硬化させ形成したことを特徴とする特許請求
の範囲第（１）項記載の樹脂封止形半導体装置。[Claims] (]) The circuit is characterized in that latex is applied to all or part of a predetermined circuit formed on an insulating substrate, and the latex is sealed with an insulating resin via an elastic hardened film formed on the surface. A resin-encapsulated semiconductor device. (2) The resin according to claim (1), wherein the elastic cured film on the latex surface 9 applied to the whole or a part of the predetermined circuit is formed by curing the latex with carboxylic acid vapor. Sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58181844A JPS6072250A (en) | 1983-09-28 | 1983-09-28 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58181844A JPS6072250A (en) | 1983-09-28 | 1983-09-28 | Resin-sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6072250A true JPS6072250A (en) | 1985-04-24 |
Family
ID=16107800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58181844A Pending JPS6072250A (en) | 1983-09-28 | 1983-09-28 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6072250A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541617U (en) * | 1991-11-14 | 1993-06-08 | 株式会社タブチ | Drill for lining pipe |
-
1983
- 1983-09-28 JP JP58181844A patent/JPS6072250A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541617U (en) * | 1991-11-14 | 1993-06-08 | 株式会社タブチ | Drill for lining pipe |
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