JPS607176A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a switching element having high withstand voltage, by selecting impurity concentration and intervals so that depletion layers extending to a collector region, become a pinch-OFF state before the occurrence of breakdown phenomenon. CONSTITUTION:The concentration of impurities and the thickness of an epitaxial layer 2 are selected as follows: a low resistivity embedded region is not provided in a well; depletion layers are extended from a collector region 21 in the inside under an emitter region 4 toward a collector contact region 5; and a collector voltage is not directly applied to the collector region 21 in the inside. Namely, when the collector voltage is high, the depletion layers extended from a base region 3 and from a substrate 1 are contacted each other. The depletion layers are further extended and the voltage drop is generated between the collector contact region 5 and the collector region 21 in the inside by the depletion layers. Therefore, the potential of the collector region 21 in the inside becomes lower than the collector voltage by the amount of the voltage drop due to the depletion layers. Even though a high voltage is applied to the collector, avalanche breakdown in not generated at the lower part of the emitter region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for a high voltage switching element.

Many bipolar integrated circuit semiconductor devices are fabricated within a semiconductor wafer with an epitaxial layer formed on the substrate. The epitaxial layer is of opposite conductivity type to the substrate, I)n
It is electrically isolated from the substrate by bonding. In the bi-taxial layer, an isolation region and an insulator isolation region of the same conductivity type as the substrate are further provided to form regions or wells for each element electrically isolated from the surroundings.

Since the bottom surface (interface with the substrate) and side surfaces of each well are electrically isolated by a p-n junction, etc., the emitter electrode, base electrode, and collector electrode of the bipolar junction transistor are all formed on the top surface (the surface of the engineered taxial layer). . Therefore, carriers flowing from the emitter electrode to the collector electrode must also flow laterally (in a direction parallel to the surface of the epitaxial layer) within the epitaxial layer. When a well is formed in a region with high resistivity (low impurity concentration), lateral resistance (collector series resistance, etc.) within the well increases.

An increase in the collector series resistance causes a decrease in operating speed due to an increase in the RO time constant. For this reason, in many bipolar integrated circuits, in each transistor well, a localized implant with a high impurity concentration that is electrically continuous and of the same conductivity type as the epitaxial layer is implanted on the substrate surface or near the interface between the substrate and the epitaxial layer. An area (sub-collector area) is provided. Since the sub-collector region has a high impurity concentration (low resistivity) and extends laterally within the well, it substantially reduces the lateral resistance within the well, enabling high-speed operation of the transistor, etc.

The emitter-collector breakdown voltage of a bipolar junction transistor with such a buried region is mainly determined by the breakdown voltage of the pace-collector junction, that is, the impurity concentration of the epitaxial region sandwiched between the pace region and the sub-collector region below the emitter region. and thick pace/subcollector distance)
It is determined by The shape (curvature, etc.) of the pace area also affects the pressure resistance. The breakdown phenomenon in the silicon region below the impurity temperature of about 1018 cm-3 is mainly due to avalanche breakdown. Avalanche breakdown can usually be explained by critical electric field strength, which is said to be about 105 to 10' V/crn. If there is a portion within a transistor where the critical electric field strength is exceeded, a breakdown phenomenon occurs there. In order to obtain a high breakdown voltage, it is necessary to prevent the critical electric field strength from being exceeded and to increase the voltage drop.

Therefore, it is effective to lower the impurity concentration in the region between the pace and the subcollector (ie, the epitaxial layer) and increase the thickness.

However, growing a thick engineered taxial layer with a low impurity concentration poses difficulties in process control and tends to lower the yield. It also increases the thickness of the epitaxial layer in other parts of the integrated circuit, since the thickness of the epitaxial layer is typically uniform within the wafer.

Furthermore, it is necessary to increase the depth and width of the separation region, which leads to a decrease in the degree of integration and a complicated process. For this reason, the epitaxial layer cannot be made very thick, and the breakdown voltage of bipolar transistors that can be practically obtained is about 60V.

One of the objects of the present invention is to provide a semiconductor device suitable for a high voltage switching element.

According to one embodiment of the invention, a low resistivity buried region is not provided in the well, and the depletion layer extends from the internal collector region under the emitter region toward the collector contact region, so that the collector voltage is directly applied to the internal collector region. The impurity concentration and thickness of the engineered taxial layer are selected such that no voltage is applied. That is, when the collector voltage is high, the depletion layer extending from the space region and the substrate touch each other and extend further, creating a voltage drop across the depletion layer between the collector contact region and the internal collector region. Therefore, the potential of the internal collector region is lower than the collector voltage by the voltage drop caused by the depletion layer.
Even if a high voltage is applied to the collector, avalanche breakdown will not occur below the emitter region.

Other objects, features, advantages, etc. of the present invention will become apparent from the following description.

FIG. 1A shows a schematic cross-section of a bipolar junction transistor for an integrated circuit with a buried region. N-type taxial layer 2 serving as a high resistivity collector region on p-type substrate 1
is formed, and a p-type base region 3 is formed in the epitaxial layer 2.
, an n++ collector contact region 5, a p++ isolation region 11, and an n++ emitter region 4 within the p-type base region 3.
is formed. In order to reduce the series resistance between the n-type internal collector region 21 under the emitter region 4 and the n+-type collector contact region 5, the surface of the p-type substrate 1 is filled with n++ (
A sub-collector region 13 is formed. Due to impurity redistribution during mechanical taxial growth, etc., the impurities have also entered the D+ type buried region 13 into the epitaxial layer 2. 12 is an insulating protective film 3', 4', and 5' are electrodes of a pace, an emitter, and a collector.

1B, 1(,, ID diagram shows the n- right below the emitter region 4)
The impurity distribution, electric field strength distribution, and potential distribution in the collector region 21 inside the mold are schematically shown.

In Figure 1B, p+ n-r n+ is 3.2 for each region.
It shows an impurity concentration of 1.13. Hereinafter, n+)p>Σ-. Since the buried region 13 and the collector contact region 5 are electrically connected to each other by the same conductivity type region, they are considered to have approximately the same potential as long as the collector current is not large.

When a positive voltage with respect to the pace electrode 3' is applied to the collector electrode 5', the pace-collector pn junction is reverse biased, and a depletion layer spreads on both sides of the pn junction.

However, due to the law of charge neutrality, υ base region 3. The width W2 of the depletion layer inside the collector region 21 is much narrower than the width W1 of the depletion layer inside the collector region 21. When the depletion layer expands, an electric field intensity distribution as shown by the solid line E1 in FIG. 1C occurs depending on the charge within the depletion layer.

As the reverse bias increases.

The depletion layer reaches the buried region 13 and enters therein.

At this time, the electric field strength is a broken line]1ii2. It will look like E3. Critical electric field strength Ecr at which the maximum electric field strength is avalanche breakdown
When it reaches , avalanche surrender is thought to occur from that part. A potential distribution corresponding to the electric field intensity distribution E2 in FIG. 1C is shown in FIG. 1D. Most of the applied voltage will be applied to the high resistivity internal collector region 21. The lower the impurity density n- of the internal collector region 21, the wider its width W.
21 can be made large to increase the voltage drop in that region (thus increasing the withstand voltage. For example, as an abrasive planar junction, n-x 10]5am-3, W21~
If it is 20 tim, it will be possible to withstand a voltage of about 300v.

However, if the impurity concentration n- and width w21 of the engineered taxial layer 2, and thus the internal collector region 21, are limited by process conditions, the width of the depletion layer is also limited, and the breakdown voltage is limited. For example, when a voltage of 30 V is applied to a width of 1 μm, even when a uniform electric field is generated, E=3×10 δv/c1n, which is sufficient to cause avalanche breakdown. When the impurity concentration becomes n-=10" cm-3, no matter how thick the thickness is, a breakdown voltage of less than 100cm will be obtained. Uneven impurity distribution and curvature of the pn junction surface will further reduce the breakdown voltage. It can be done.

The usual withstand voltage of about 60 mm for conventional bipolar junction transistors for integrated circuits can be explained by the above-mentioned reasons.

In order to obtain a high breakdown voltage with the structure shown in Figure 1A, the internal collector region 2
It is essential to lower the impurity concentration of No. 1 and increase the thickness, which inevitably increases manufacturing costs and other inconveniences.

However, the above discussion is for the case where there is almost no voltage drop between the collector and subcollector.

If the internal collector region 21 can be electrically isolated from the collector contact region 5, it is sufficiently possible to prevent the internal frefter region 21 from breakdown even if a high voltage is applied to the collector contact region 5.

FIG. 2A shows an embodiment of a bipolar junction transistor based on the above idea. The same symbols as in Figure 1A are in Figure 1A.
Indicates something that is the same as or similar to the one in the figure. In this embodiment, there is no low resistivity buried region, and the n-type internal collector region 21 is sandwiched between the p-type base region and the p-type substrate.

The impurity density n- and the thickness t of the internal collector region 21 are set to a predetermined value (■) for the collector. The base region 3 and the depletion layer extending from the substrate 1 are selected so as to be in contact with each other when the above voltage is applied. Assuming that the base region 3 and the substrate 1 are now grounded, the width Wd of each depletion layer must be approximately the same in order to satisfy the above conditions. 8o is the dielectric constant of vacuum, Ks is the relative dielectric constant, q is the elementary charge, and n is the impurity concentration. For silicon (xs; 12), nn=1015
If C, t=6 μm, the voltage required to bring the depletion layers into contact with each other is approximately 8V.

If n=101' am-3, the depletion layers will come into contact with each other at vo; 50V.

In other words, a depletion layer is a region where a potential gradient exists.

If a depletion layer crosses between the internal collector region 21 under the base region 3 and the collector contact region 5, the maximum potential in the internal collector region 21 will naturally be lower than the potential in the collector contact region 5.

The sum of the voltage in the internal collector region 21 and the voltage drop between the internal collector region 21 and the collector contact region 5 is therefore the collector voltage of this composite transistor. Even if the potential of the internal collector region 21 is limited to the same level as the conventional value, the collector voltage can be increased if the voltage drop due to the depletion layer is increased.

Note that the distance W between the base region 3 and the collector contact region 5. Alternatively, it is obvious that if the distance d between the collector contact area 5 and the substrate 1 is short, avalanche precipitation may occur there. Wo needs to be at least y2 or more. The values of Wo and d depend on the desired breakdown voltage.

The specific resistance of the epitaxial layer 2 is set to about 306In (1 to n-
．． 5x'10'5crn-"), distance between base region and substrate tz7μm1 base diffusion depth approximately 1.6pm
(Surface concentration approximately 1018 cm-'', base width at the surface approximately 5 μm), the base-collector breakdown voltage BVo.

I was able to increase the voltage to over 210v. Traditionally, BvoBo
Compared to the previous case, which was about 6' OV, this was a huge improvement. Note that the emitter region 4 to base region 3 to collector regions 2 and 5 in the horizontally arranged portions mainly related to breakdown voltage.
substantially forms a bipolar transistor, (β<
0.1), BV to BV. Conventionally, BVo.

Compare CEO and CBO The difference is even bigger.

FIG. 2B schematically shows the shape of the depletion layer when the collector voltage is low and when it is high. When the dashed line shows low collector voltage,
This is the case where the dotted line is high. Note that the illustrated shape is simplified for the sake of explanation, and changes depending on the voltage drop R due to the resistance component, etc. More precisely, it can be determined by solving the equation of current continuity and the 6-dimensional Poisson phallic equation.

Note that the lateral distance between the emitter-base pn junction and the base-collector pn junction is sufficiently large, and the bipolar transistor is formed only in the emitter region 4 and its lower part. For example, base region 3 has a surface concentration pz of 1018 cm.
3. When the longitudinal base width is about 0.4 μm, the distance between the joints on the surface is 5 μm or more.

As shown in FIG. 2B, both the substrate 1 and the base 3 are grounded or at a low potential. In the following, it is assumed that both are grounded. Collector voltage V. When increasing , the internal collector region 21 also decreases as long as the collector current is zero. Therefore, the pn junction between the substrate 1 and the base region 3 is reverse biased to grow a depletion layer.

An example of the electric field strength distribution at this time is shown in Fig. 2o.

Collector voltage V. As becomes higher, the depletion layer also lengthens, and eventually the depletion layers extending from the base region 3 and the substrate 1 touch and further extend toward the collector contact region 5.

An example of the potential distribution is shown in FIG. 2D. Internal collector area 21
and the collector contact area 5 are the base area 3 and the substrate 1
The depletion layer extending from the top creates a valley-like potential distribution shape and continues toward the collector contact region 5 as shown by the broken line in FIG. 2D. In other words, the structure is similar to that of junction FIT,
It becomes an action. The internal collector region 21 acts as a source, the substrate 1 and base region 3 act as a date, and the collector contact area 5 acts as a drain.Even if the drain voltage of the junction FFtT changes, the source side does not change much and maintains a constant current. As can be understood from the flow of , after the depletion layers touch each other (pinch-off), the potential of the internal collector region 21 is not affected by changes in the collector potential V0.The channel length of the pseudo junction FIICT is In the above example, the channel length is 5 μm or more. The droop breakdown mainly occurs in the p-type base (date) region 3 (or p-type,
It is determined by the relationship between the substrate 1) and the n-type epitaxial layer 2. Since the impurity concentration ratio p/n- is usually 100 or more, the breakdown voltage is mainly determined by the impurity concentration of the epitaxial layer 2 and the lateral distance between the base region 3 and the collector contact region 5. Note that leaving a neutral region with a higher resistivity than necessary around the collector contact region 5 will increase the collector resistance and increase the transistor dimensions, so it is preferable to set the value to a necessary and sufficient value.

FIG. 3 shows a top view of an embodiment having a multi-emitter structure.

An elongated p-type base region 3 and an n+-type collector region 5 that face each other are formed, and five n+-type emitter regions 4 are formed in the p-type base region 3.

Effective for multi-mounted crab mitter follower circuits, etc.

FIG. 4 shows a circuit diagram of an embodiment of an integrated circuit. logic circuit 4
A logic output of 1 is supplied to the load drive circuit 42 and drives the load 43 via the output terminal. The other end of load 43 is connected to a voltage source. The load drive circuit 42 includes a first series connection of bipolar transistor TR-1, junction FIT, and rFmT-1, and bipolar transistor TR-2 and junction FBT:
a second series connection with rFmr-2 to form a Darlington connection.

Note that a plurality of TR-2s and a plurality of rpmT-2s are provided, and a plurality of second series connections are connected in parallel to one first series connection. Emitter of TR-1 (T
The base of R-2) is connected to the emitter of TR-2 via a resistor Ri, and is connected to the ground terminal. The Darlington connection is provided to enable the TR-2 to operate with a weak signal current from the logic circuit 41.

In addition, TR-1 and TR-2 formed on the integrated circuit
And, TFET-1 and JF'ET-2 each have the same performance l), and the emitter of TR-1 has multiple T'R-2
Since they are connected in parallel to each other, if the number of TR-2s connected to one TR-1 is selected appropriately, each T
The current value supplied to the R-2 pace can be set to a predetermined value. Since the current value supplied to the pace of each TR-2 can be set to a predetermined value in this way, a decrease in the operating speed of each TR-2 can be prevented, as will be described later.

Moreover, the load 43 can also be connected to the emitter of TR-2. In the case of an emitter load, it is convenient to use a multi-emitter structure as shown in FIG. 6 to obtain a plurality of outputs.

The logic circuit 41 and the load 43 can be of various known types. The integrated circuit includes a logic circuit 41 and a drive circuit 4.
2, but it is obvious that part of the logic circuit 41 can be an external component. It is also obvious that the conductivity types of the transistors can all be reversed. When viewed as a circuit: One purpose of providing rF'wT-1 and 2 is to
This is to enable the voltage value of the power supply upstream of the load to be set high. In other words, it is provided to improve the withstand voltage of the load drive circuit 42. The collectors of TR-1゜TR-2 are connected to a high potential via JFKT-1 and JFBT-2, so the load (power supply) terminal voltage is reduced by the voltage drop within JFKT-1゜JFII-2. -1,T
The collector breakdown voltage of R-2 can also be increased.

TR-1 and rFI! Each of the first series circuit with iT-1 and the second series circuit with TR-2 and TFET-2 can be formed by one composite transistor of the embodiment of FIG. 2A.

Therefore, in terms of an equivalent circuit, even two transistors, a bipolar junction transistor and a junction FET, can be realized in a single transistor structure within a semiconductor wafer, and a high breakdown voltage can be obtained. If a multi-emitter is used, a plurality of series circuits, etc. can be realized within one well.

The resistor R-1 serves to adjust the pace current of the transistor TR-2 and to extract carriers from the transistor TR-2 when the transistor TR-1 is turned off. R-1 Gana (
When the emitter current of TR-1 is two or more times larger than the current required to drive TR-2, a so-called saturated switching state occurs and an excessive pace current flows into TR-2. In this case, excess carriers are accumulated at the pace of TR-2. Fourth
In the case shown, electrons are depleted in the n-type emitter of TR-1 and become excess holes in the p-type base of TR-2, positively charging the pace. When the collector current of TR-2 is limited, excess holes in the pace also flow to the collector. TR-
When the TR-2 is turned off, the collector current of the TR-2 will not become zero unless this excess carrier disappears. However, as mentioned above, if a plurality of second By providing series connections in parallel, the current supplied to the pace of TR-2 is selected to a predetermined value so as not to accumulate a large amount of excess carriers in the pace of TR-2, and R-1 is provided. Therefore, during off-time, excess holes in the pace region do not flow to the emitter, and the pace accumulated carriers are quickly drawn to ground.

FIG. 5A shows an example of a basic circuit used in the logic circuit 41 including the flip-flop circuit shown in FIG. Emitter-coupled bipolar junction transistor TR-5, TR
-6 and load resistances IR-5 and R-6 are so-called lIC0
It constitutes an L logic circuit.

The polarity of the power supply, the polarity of the transistors TR-5 and TR-6, etc. are determined depending on the relationship with other circuits. The basic logic circuits are not limited to FIOL, but also TTL and EEL.

Other bipolar logic circuits such as NTL, 5TIJ (Schottky t-transistor logic), and even MO8 logic circuits may also be included. It is also obvious that memories may be integrated.

Figures 5B, 50, and 5D show examples of structures of bipolar junction transistors and resistors used in these logic circuits.

A surface protective film and electrodes are omitted. Reference numerals common to FIGS. 1a and 2A indicate the same or similar elements.

An n-type etched taxial layer 2 is formed on a p''' type substrate 1, and a well is formed by a p++ isolation region 11.In each well, an n+ type layer 2 is formed near the interface between the substrate 1 and the epitaxial layer 2. A mold buried region 13 is formed.The power supply voltage of the logic circuit is usually as low as 5V or less, so the withstand voltage is not a problem.5th E.

The buried region 13 shown in FIG. 50 substantially reduces collector resistance and base resistance, respectively, and is useful for realizing high-speed operation. In other words, within the same chip, drive circuit transistors are formed in wells with no buried regions to achieve high breakdown voltage, and logic circuit transistors are formed in wells with low resistivity buried regions to achieve low voltage and high speed. Realize the action.

The npn transistor in FIG. 5B is formed with an n++ emitter region 4, a p-type base region 3, an n-type collector region 2, an n+-type buried region 13 and an n+-type collector contact region 5.

pnp in Figure 5C) The transistor is a lateral type,
It is formed of a central p++ emitter region 14, a surrounding p++ collector region 15, an intermediate n-type base region 2, an n+-type buried region 13 and an n++ space contact region 16.

The resistor of FIG. 5D is formed by a p-type resistance region 17 in the n-type engineered taxial layer 2 and p++ electrode contact regions 18.19 formed in its ends.

According to the above configuration, even if the withstand voltage of the load drive circuit is increased, the thickness of the epitaxial layer can be made smaller. Therefore, the epitaxial thickness of the transistor portion constituting the logic circuit can also be reduced, making it possible to form a small well. This stray capacitance can also be reduced. On the other hand, by forming the buried region, the collector series resistance or the space series resistance can be reduced.

Therefore, logic circuit transistors can operate at high speed.

Furthermore, since the thickness of the engineered taxial layer can be reduced, the depth of the separation region between the wells can also be reduced, and therefore the width of the separation region can be reduced, and the integration density can be improved.

[Brief explanation of the drawing]

FIG. 1A is a cross-sectional view of a bipolar transistor with a buried region, FIGS. 1B, 1C, and 1D are schematic diagrams explaining the operation of the transistor in FIG. 1A, and FIGS. 2A and 2B.
20 and 2D are diagrams showing the electric field strength distribution and potential distribution inside the composite transistor, and FIG. 6 is a top view and a sectional view of the multi-emitter composite transistor, FIGS. 5C and 5D are cross-sectional perspective views of a pnp transistor and a resistor. 1... Substrate 2... Epitaxial layer, 21...
Internal collector region, 3... p-type base region, 4...
n++ emitter region, 5... n medium collector contact region, 13... low resistance buried region 1.14... p++ emitter region, 15... p++ collector region, 41... logic circuit, 43. ...Load, 42...Load drive circuit. Agent Akira Asamura

Claims (1)

[Claims] (1) A semiconductor substrate of a first conductivity type, a collector region of a second conductivity type formed on the semiconductor substrate and having a predetermined impurity concentration, and a collector region provided in the collector region at a predetermined distance from the semiconductor substrate, to which a signal voltage is applied. a base region of a first conductivity type,
In a semiconductor device including an emitter region of a second conductivity type provided in a space region, when the collector voltage is increased when the signal voltage is at a low level, the semiconductor device A semiconductor device characterized in that the impurity concentration and spacing are selected so that a depletion layer extending from the substrate and the space region to the collector region is in a pinch-off state.