JPS6070735A - Semiconductor element mounting substrate - Google Patents
Semiconductor element mounting substrateInfo
- Publication number
- JPS6070735A JPS6070735A JP58179802A JP17980283A JPS6070735A JP S6070735 A JPS6070735 A JP S6070735A JP 58179802 A JP58179802 A JP 58179802A JP 17980283 A JP17980283 A JP 17980283A JP S6070735 A JPS6070735 A JP S6070735A
- Authority
- JP
- Japan
- Prior art keywords
- zno
- sio2
- substrate
- sintering
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子、特に大規模集積回路（ＬＳＩ）素
子を収納、搭載するための半導体素子用実装基板（ＩＣ
パッケージや多層配線基板等）の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device mounting board (IC) for housing and mounting semiconductor devices, particularly large scale integrated circuit (LSI) devices.
(packages, multilayer wiring boards, etc.).
近時、情報処理装置の高性能化に伴い、これを構成する
半導体素子も高速度化、高集積化が急激に進んでいる。2. Description of the Related Art In recent years, as information processing devices have become more sophisticated, the speed and integration of semiconductor elements constituting these devices have also rapidly increased.
そのため、これら半導体素子を収納する半導体パッケー
ジや半導体素子を搭載取着する多層配線基板も、その内
部に形成された配線パターンの信号伝搬速度を高速度化
することが要求されている。この配線パターンの信号伝
搬速度は、半導体パッケージや多層配線基板等半導体素
子用実装基板を構成する材料の誘電率によって決定され
、従来、電気絶縁性に優れ、かつ機械的強度が大である
ことから多用されているアルミナ（Ａ１２０５ ）の場
合、誘電率が９〜１０と大きいため。Therefore, semiconductor packages that house these semiconductor devices and multilayer wiring boards that mount and attach semiconductor devices are also required to increase the signal propagation speed of the wiring patterns formed therein. The signal propagation speed of this wiring pattern is determined by the dielectric constant of the material that makes up the semiconductor package, multilayer wiring board, or other semiconductor device mounting board. Alumina (A1205), which is widely used, has a high dielectric constant of 9 to 10.
信号伝）般速度が極めて遅いという欠点を有していた。The disadvantage was that the signal transmission speed was extremely slow.
本発明者等は上記欠点に鑑み種々の実験の結果、５ｉＯ
ｚ（α−石英）にＺｎＯ及びＢＪ、＋を添加して焼成す
ると電気絶縁性に優れ、かつ誘電率が極めて小さい半導
体素子用実装基板が得られることを知見した。In view of the above drawbacks, the present inventors have conducted various experiments and found that 5iO
It has been found that when ZnO and BJ, + are added to z (α-quartz) and fired, a mounting board for semiconductor elements with excellent electrical insulation and an extremely low dielectric constant can be obtained.
本発明は上記知見に基づき、内部に形成されろ配線パタ
ーンの信号伝搬速度が極めて速い、電気絶縁性に優れ、
かつ低誘電率の半導体素子用実装基板を擢供することを
その目的とするものである、本発明の半導体素子用実装
基板は、 ５ｉ（ｂ５６．５０〜８６．９５ ｗｔ％、
ＺｎＯ９，３０〜３１．００ ｗｔ％、 Ｂ２０Ｊ３
７５〜１２．５０ ｗｔ％の焼結体からなることを特徴
とする。The present invention is based on the above findings, and the wiring pattern formed inside has extremely high signal propagation speed, excellent electrical insulation,
The mounting substrate for semiconductor elements of the present invention, which aims to provide a mounting substrate for semiconductor elements with a low dielectric constant, has the following properties: 5i (b56.50 to 86.95 wt%,
ZnO9, 30-31.00 wt%, B20J3
It is characterized by consisting of a sintered body of 75 to 12.50 wt%.
本発明の半導体素子用実装基板の主成分はＳｉＣｈ（α
−石英）であり、 ＺｎＯ、Ｂよ０３は焼結助剤である
。The main component of the semiconductor element mounting substrate of the present invention is SiCh (α
- quartz), and ZnO and B 03 are sintering aids.
前記ＺｎＯ及びＢ２Ｏ３は主成分であるＳｉＯユの一部
と反応し、ガラス相を形成して液相焼結させる。焼結助
剤である前記ＺｎＯ、Ｂ工ＯＪの含有量は、 ＺｎＯが
９、Ｂ０旧％未満、Ｂ工０３が３．７５１９ｔ％未満の
場合、 ５ｉＯｚとの反応によって形成されるガラスが
不十分であり、 Ｓｉｎ、の完全な液相焼結ができず、
緻密な焼結体が得られない。またＺｎＯが３１．００
ｔｙｔ％以上＋ Ｂ：Ｌ０３が１２．５０ ｗｔ％以上
の場合、 ＳｉＯ２，との反応によって形成されるガラ
スが過剰となり、焼結の際、基板が軟化して基板表面に
形成した配線パターンが断線して実用に供しなくなる。The ZnO and B2O3 react with a portion of SiO, which is the main component, to form a glass phase and undergo liquid phase sintering. The content of ZnO and B-OJ, which are sintering aids, is as follows: When ZnO is less than 9%, B0-03 is less than 3.7519t%, the glass formed by the reaction with 5iOz is insufficient. Therefore, complete liquid phase sintering of Sin is not possible,
A dense sintered body cannot be obtained. Also, ZnO is 31.00
tyt% or more + B: When L03 is 12.50 wt% or more, the glass formed by reaction with SiO2 becomes excessive, and during sintering, the substrate becomes soft and the wiring pattern formed on the substrate surface becomes disconnected. It becomes useless for practical use.
したがってＺｎＯ＋及びＢ２Ｏ３の含有量はそれぞれＺ
ｎ０９．３０〜３１．ＯＯｗｔ％、 Ｂ２Ｏ３３，７５
〜１２．５０訂％の範囲に設定される。Therefore, the contents of ZnO+ and B2O3 are respectively Z
n09.30-31. OOwt%, B2O33,75
It is set in the range of ~12.50%.
本発明の半導体素子用実装基板は、 ５ｔＯａ＋ Ｚｎ
Ｏ及びＢ２０〕を上述した所定範囲に設定することによ
り１基板の電気絶縁性を極めて高いものに維持しつつ誘
電率を低い値となすことができ、その結果。The semiconductor element mounting board of the present invention has 5tOa+Zn
O and B20] within the above-mentioned predetermined ranges, the dielectric constant can be made to a low value while maintaining the electrical insulation of one substrate to be extremely high, and as a result.
内部に形成される配線パターンの信号伝搬速度を極めて
速いものとすることができる。The signal propagation speed of the wiring pattern formed inside can be made extremely high.
次に本発明を実施例に基づいて説明す。Next, the present invention will be explained based on examples.
出発原料としてＳｉＯよ（α−石英） ＋ Ｚ ｎ Ｏ
及びＢ。SiO (α-quartz) + Z n O as a starting material
and B.
島の粉末をそれぞれ下表となるように秤量し、これに例
えばトルエン、メチルエチルケトン等の適当な溶剤、ポ
リイソブチルツタアクリレ−１−等の適当な結合剤、及
びＤＢＰ （ジブチルフクレ−１）等の適当な可塑剤を
加えて混合する。混合終了後、これらをテープ成形法に
より厚さ１ｍｍのシー１−に成形し、その後、該グリー
ンシートを長さ５０ｍｍ、幅５０ｍｍの二枚に切断する
とともに一方のグリーンシート表面にＮｉからなる導体
ペーストをスクリーン印刷する。そして次に二枚のグリ
ーンシートを導体ペーストを挟持する如く積層、熱圧着
し。Weigh each of the powders as shown in the table below, add a suitable solvent such as toluene or methyl ethyl ketone, a suitable binder such as polyisobutyl ivy acrylate-1, and DBP (dibutyl fucre-1). Add a suitable plasticizer and mix. After mixing, these were formed into a sheet 1-thickness 1 mm by tape molding method, and then the green sheet was cut into two pieces with a length of 50 mm and a width of 50 mm, and a conductor made of Ni was placed on the surface of one of the green sheets. Screen print the paste. Next, the two green sheets were laminated with the conductive paste sandwiched between them and bonded together under heat.
空気中３００ ’Ｃで仮焼成を行った後、Ｎ１雰囲気ｌ
］月１４０℃で１時間本焼成して基板試料を得た。After pre-calcining in air at 300'C, N1 atmosphere l
] A substrate sample was obtained by main firing at 140° C. for 1 hour.
尚、試料番号８は本発明品と比較するための比較試料で
あり、従来一般に使用さ５でいるアルミナからなる基板
である。Incidentally, sample number 8 is a comparative sample for comparison with the product of the present invention, and is a substrate made of alumina, which is commonly used in the past.
か（して得られた基板試料の誘電率を誘電率測定装置（
Ｑメーター）を使用して測定するとともに次式によりＮ
ｉ導体を伝搬する信号の伝搬時間を算出した。The permittivity of the substrate sample obtained by
N
The propagation time of the signal propagating through the i-conductor was calculated.
Ｔｄ−０，０３３３丁
また、同時に基板試料の体積固有抵抗を抵抗測定装置（
テスター）により測定した。Td-0,0333 At the same time, the volume resistivity of the substrate sample was measured using a resistance measuring device (
tester).
上記の結果を下表に示す。The above results are shown in the table below.
＊を付し幻Ｍ斗番号のものは本発明の範囲外のものであ
る。Items marked with * and phantom numbers are outside the scope of the present invention.
上記実験結果からも判るように、従来のアルミナからな
る半導体素子用実装基板は、その誘電率が９〜１０で信
号伝搬時間が０．１００〜０．１０５ ｎｓ／ ｃｍで
あるのに対し２本発明の半導体素子用実装基板は誘電率
が４．０〜５．２で信号伝搬時間が０．０６７〜０．０
７６ ｎｓ／ ｃｍであり、信号伝搬時間が従来品に比
し３０％以上も短縮することが可能となる。As can be seen from the above experimental results, conventional alumina mounting substrates for semiconductor devices have a dielectric constant of 9 to 10 and a signal propagation time of 0.100 to 0.105 ns/cm. The semiconductor device mounting substrate of the invention has a dielectric constant of 4.0 to 5.2 and a signal propagation time of 0.067 to 0.0.
76 ns/cm, making it possible to reduce signal propagation time by more than 30% compared to conventional products.
また１本発明の半導体素子用実装基板は体積固有抵抗が
６．５ｘｌＯ［上であり、従来のアルミナからなる半導
体素子用実装基板と同等の電気絶縁性も有している。Furthermore, the semiconductor element mounting substrate of the present invention has a volume resistivity of 6.5xlO[or higher, and has electrical insulation properties equivalent to a conventional semiconductor element mounting substrate made of alumina.
従って１本発明は高速度化が進む半導体素子を収納、搭
載する半導体素子用実装基板として極めて有用である。Therefore, the present invention is extremely useful as a mounting board for semiconductor elements that accommodates and mounts semiconductor elements whose speeds are increasing.
尚１本発明は上述した実施例に限定されるものではな（
１本発明の要旨を逸脱しない範囲であれば種々の変更は
可能である。Note that the present invention is not limited to the above-mentioned embodiments (
1. Various modifications can be made without departing from the gist of the present invention.
特許出願人 京セラ株式会社patent applicant Kyocera Corporation
Claims (1)
，３０〜３１．００會ｔ％、Ｂ、Ｏａ３．７５〜１２．
５０ ｗｔ％の焼結体からなる半導体素子用実装基板。SiO, 56,50-86.95 wt%, ZnO9
, 30-31.00 t%, B, Oa3.75-12.
A mounting board for semiconductor elements made of a 50 wt% sintered body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58179802A JPS6070735A (en) | 1983-09-27 | 1983-09-27 | Semiconductor element mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58179802A JPS6070735A (en) | 1983-09-27 | 1983-09-27 | Semiconductor element mounting substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6070735A true JPS6070735A (en) | 1985-04-22 |
| JPH0455988B2 JPH0455988B2 (en) | 1992-09-07 |
Family
ID=16072148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58179802A Granted JPS6070735A (en) | 1983-09-27 | 1983-09-27 | Semiconductor element mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6070735A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287558A (en) * | 1988-09-24 | 1990-03-28 | Murata Mfg Co Ltd | Ic chip |
| JPH10297960A (en) * | 1997-04-25 | 1998-11-10 | Kyocera Corp | Ceramic composition baked at low temperature and production of porcelain baked at low temperature |
-
1983
- 1983-09-27 JP JP58179802A patent/JPS6070735A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287558A (en) * | 1988-09-24 | 1990-03-28 | Murata Mfg Co Ltd | Ic chip |
| JPH10297960A (en) * | 1997-04-25 | 1998-11-10 | Kyocera Corp | Ceramic composition baked at low temperature and production of porcelain baked at low temperature |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0455988B2 (en) | 1992-09-07 |
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