JPS6070590A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the number of data lines or the number of common data lines and common output lines and to suppress the increment of parasitic capacity by constituting a sense amplifier group by multi-stages. CONSTITUTION:The common output of each group of the divided 1st sense amplifier is connected to the 2nd sense amplifier to be exclusively used for each group so that common data lines 50, 51 are connected to a sense amplifier 53. Two kinds are selected by address signals A2, A2' in the 1st sense amplifier and four kinds are selected by the combination of address signals A0, A0', A1, A1' in the 2nd sense amplifier, so that eight kinds of selection and combination can be attained and the functions of a sense amplifier can be completely performed by the circuit. The number of sense amplifiers (2 and 4 amplifiers) is low, the parasitic capacity is low and high speed reading can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor memory vrtζ having an improved sense amplifier configuration.

[Prior art]

The configuration of a sense amplifier in a conventional semiconductor memory, such as a kiOs memory, will be explained by taking the static MOS memory shown in FIG. 1 as an example. Here, 1.2 is a memory cell group, and 3 is a memory cell consisting of its unit circuit. This memory cell is accessed by a decoder 5 driving word line 4.

The output signal appears on data lines 6 and 7, and the switch MOS
Common data line 10.11 through transistors 8, 9
appears in

In the conventional example, the common data line is divided into four blocks, and the common data lines 10 and 11 are connected only to the sense amplifier 12.

In order to select these four divided sense amplifiers, any one of four sets of address signals consisting of the first address signals AQ, A, () and the second address signals AI, AI is selected. A set of signals is applied to each sense amplifier. In the sense amplifier, these address signals allow only one
is selected, its output appears on the common output lines 13 and 14 of these four sense amplifiers, is further amplified by the sense amplifier 15, and an output OUT appears at the output terminal 16.

In this conventional example, by dividing the common data line into four parts, the parasitic capacitance can be reduced and the speed can be increased.

However, in recent years, as the capacity of static MO8 memory has increased, the number of data lines has increased, and the number of data lines connected to each four-divided common data line in the conventional example shown in Figure 1 has increased. In particular, the parasitic capacitance continues to increase, making high-speed reading difficult. To give a specific example, a 4 kilobit memory usually has a configuration of 64 rows x 64 columns, and has 64 sets of data lines. Therefore, when the configuration shown in FIG. 1 is adopted, 16 sets of common data lines are connected per set. On the other hand, a 64 kilobit memory usually has a configuration of 256 rows x 256 columns, so there are 256 sets of data lines. Therefore, when taking the configuration shown in Figure 1,
If υ64 sets are connected per set of common data lines, the parasitic capacitance increases and high-speed reading becomes difficult.

In order to solve this problem, it is conceivable to increase the division of the common data line. In other words, in a 64 kilobit memory, by increasing the number of divisions to 16, 916 sets of data lines are connected per set of common data lines, and an increase in the parasitic capacitance of the common data lines can be suppressed. I can do it.

However, the disadvantage of this multi-division is that sense amplifiers are required for each common data line.
In a kilobit memory, 16 sense amplifiers are required, which in turn increases the parasitic capacitance of the common output line of the sense amplifiers. In other words, when dividing a 64 kilobit memory from 4 to 16, the parasitic capacitance of the sense amplifier's output, that is, the common data line, can be reduced to about 1/4, but the parasitic capacitance of the sense amplifier's output, that is, the common data line, can be reduced to about 1/4. However, the problem is that the capacity is about 4 times larger), so the improvement in speed is not measurable.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor memory having a sense amplifier configuration capable of high-speed reading for a large-capacity semiconductor memory.

[Structure of the invention]

A semiconductor memory of the present invention includes a plurality of memory cells arranged two-dimensionally in the X-Y direction and a plurality of data lines commonly connecting the memory cells arranged on the same Y axis. The first sense amplifier is composed of (rl (m42) sense amplifiers, and each sense amplifier is connected to one set (or one) of the plurality of data lines). a second sense amplifier group consisting of n (m) n≧1) sense amplifiers, in which any one set (or one) of the common output lines of the first sense amplifier group is connected to the human power; L (L≧2) sense amplifier groups connected in cascade in the following order, such as the sense amplifier groups, and at least one sense amplifier from each of the sense amplifier groups are manually operated. and activating means for selecting υ and activating f according to a predetermined Y-axis selection signal.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention, and FIG. 3 is a partially detailed circuit diagram thereof.

In this embodiment, j, N are arranged two-dimensionally in the X-Y direction.
Memory cell groups 31 and 32 consisting of memory cells 36 of X M bits and memory cells 3 arranged on the same Y axis
A plurality of data lines 60, 61 . ...
In a semiconductor memory having eight sense amplifiers 42 to 49, each sense amplifier is connected to one set of common data lines among the plurality of data lines 60, 61... Output lines 50, 51 and one set of common output lines 50, 51... are cascaded like a second sense amplifier group 63 consisting of four sense amplifiers 53 to 56 connected to the human power. Two connected sense amplifier groups 62 and 63 and these two sense amplifiers 7
Each sense of group 62.63 $22. The amplifier group is at least -83, . . . and transistors 93, 94, . . . . and further activation means. Note that in the figure, DIN is a data human power line.

This embodiment uses a 2NxM bit star r4 type MO
This figure shows the sense-up configuration when the S memory has a 2NXM word 1-bit configuration. Memory cell group 31
．． 32 is, for example, a forward line 34.3 to the X decoder blade.
5 is selected and becomes high level, and the memory cell 36 is read. The read signal is selected by the Y decoder and turned on.
The application of the Yo (= sign) to terminal 37 from a transistor, for example a Y decoder, causes it to appear on common data line 40.41 through transistor 38.39.

In this embodiment, the common data line is divided into eight blocks, for example, and the common data line 40.degree. Furthermore, the eight divided first sense amplifiers 42 to 49 are, for example,
Sense amplifiers 42 and 43, sense amplifiers 45, sense amplifiers 46, 47 . Like sense amplifiers 48 and 49, groups of two are created to form a total of four sense amplifier blocks. The sense amplifier outputs in each group are connected in common to the second sense amplifiers 53 to 56 as a common output.
connected to. Then, in order to select one sense amplifier from each set of the divided first sense amplifiers, a third sense amplifier is used.
address signal A2. A2 is added to each sense amplifier 42-491. In this embodiment, the sense amplifier 42 is selected by the address signal 2, and data appears on the common data lines 50 and 51.

Here, the common output of each set of the divided first sense amplifiers is connected to the common data line 50, 51t sense amplifier 53
The first sense amplifier is connected to a second sense amplifier dedicated to each group. In order to select the four divided second sense amplifiers 53 to 56, one of the four combinations of the first address signals AQ, AQ and the second address signals AI, Al is selected. address signals are applied to sense amplifiers 53-56. Second sense amplifiers 53 to 56
Then, only 1q of them are selected based on these signals, and outputs OUT are provided to these output terminals 52.

In the case of this embodiment, when the combination of address signals AO and AI is at the selection level, the second sense amplifier 53 is selected, data appears on the common output lines 57 and 58, and is further amplified by the sense amplifier 59. Data of the selected memory cell 36 is output to the output terminal 52.

Next, the operation of this embodiment will be explained in detail using a specific circuit example of the first and second sense amplifiers shown in FIG.

In FIG. 3, reference numeral 71 indicates a first sense amplifier circuit including a first sense amplifier and its activation means, and reference numeral 72 indicates a second sense amplifier circuit including a second sense amplifier and its activation means. n-MQS) transistors 81 and 82 form a differential pair, and resistors 84 and 85 serve as a load.

The n-MQS) transistor 83 constitutes a transistor switch that puts these differential amplifier circuits into operation only when the address signal A2 is at a high level. By turning on this switch, the signal on the common data line 40.41 is amplified, and the signal on the common output line 50.41 of the first sense amplifier is amplified.
A signal appears at 51. n-MQS) transistor 91.
92 constitutes another differential pair, and resistors 95 and 96 serve as a load.

The n-M□s transistors 93 and 94 constitute a transistor switch that brings these differential amplifier circuits into operation only when the address signals AC and AI are at high level. By turning on these switches, the signal on the common output line 50.51 is amplified, and the signal is applied to the common output line 57.58 of the second sense amplifier.

That is, in the first sense amplifier, the address signal A2. A2 is selected twice, and in the second sense amplifier, address signals AAo, Ao, A1 . A
Four selections are made depending on the combination of I, and in the end eight selections and combinations are possible, and this circuit can completely perform the function of the sense amplifier shown in FIG. In addition,
In FIG. 3, Vcc is the power supply.

As a result, in this embodiment, the first sense amplifier 4
The parasitic capacitance at the input terminals 2 to 49 is, for example, about 1/2 that of the conventional example shown in FIG. This is because the number of memories required by one sense amplifier is equivalent to half a season. Furthermore, in this embodiment, the parasitic capacitances on the common output lines of the first and second sense amplifiers are as small as two sense amplifiers and four sense amplifiers, respectively, so the parasitic capacitance is small and high speed can be achieved.

On the other hand, compared to the conventional example shown in Figure 1, the number of sense amplifiers is 1.
The increase in the sense amplifier stage from one stage to two stages may result in a decrease in speed, but in general MOS memory, the overall sense amplifier has a three to four stage configuration, so the increased sense amplifier stage The speed delay can be avoided by adjusting the number of sense amplifiers in the third and subsequent stages.

In the embodiment shown in FIG. 2, address signals A2 . A
However, the address signal A2. Address signal person instead of fm 2. Asu A1. Kotoni Yoba uses decoded signals of Ai, Ao, and AO.By activating only one sense amplifier out of the 4 sets of sense amplifiers with a total of 8 words, the power consumption of this part can be reduced to 174K.
7. c.

Further, in the above embodiment, the first sense amplifier group and the second sense amplifier group
I gave an example of separating the sense amplifier #t, but in addition, the second
The parasitic capacitance of the common output line of the second sense amplifier can be reduced by dividing the sense amplifier group into two groups and adding a third sense amplifier group (two in this case). However, it is also possible to further increase the speed.

Furthermore, the above explanation deals with static type MO8 memory, but in dynamic type MQS memory, upper Wb
It goes without saying that the present invention can be applied to transistors other than MQS type by using only one data line and one common data line to be connected to the sense amplifier instead of one set.

〔Effect of the invention〕

As described above in detail, according to the present invention, by configuring the sense amplifier group in multiple stages, the data line or common data line, that is, the input section of the sense amplifier, and the common output section, that is, the output section of the sense amplifier By reducing the number of connection lines and suppressing an increase in parasitic capacitance, it is possible to obtain a semiconductor memory having a sense amplifier configuration capable of high-speed reading.

4. Brief explanation of the drawings FIG. 1 is a circuit diagram showing the main parts of an example of a conventional semiconductor memory device, FIG. 2 is a circuit diagram showing the main parts of an embodiment of the present invention,
FIG. 3 is a partially detailed circuit diagram.

1.2...Memory cell group, 3...Cell, 4...Word line, 5...Decoder,
6, 7...Data line, 8.9...MQ
S) Transistor, 10, 11...Common data line, 12...Sense amplifier, 13゜14...
...Common output line, 15...Sense amplifier,
31.32...Memory group, 33...X
Decoder, 34.35...Word line, 36...
...Memory cell, 37...Selection signal input terminal, 38,39...11-MOS transistor, 40.41...Common data line, 42,43
, 44, 45, 46, 47゜48.49...First sense amplifier 7", 50.51...Common output line, 52...Output terminal, 57.58...
...Common output M, 53, 54, 55.56...
...Second sense amplifier 7', 59...Sense amplifier, 6Q.

61...Data a, 62...First sense amplifier path, 81, 82.83=...n-MOS
? 7 resistor, 84.85...resistance, 91.
92. 93. 94...n-MOS) U/
Resistor, 95.96...Resistance AO, AO, AI
, Al, A2. A2...7)"Response signal, DI
N... Data power line, Vcc... Power supply.

Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) In a semiconductor memory having a plurality of memory cells arranged two-dimensionally in the X-Y direction and a plurality of data lines commonly connecting the memory cells arranged on the same Y axis, m (m42) sense amplifiers; a first sense amplifier group in which each sense amplifier is connected to one set (or one) of the plurality of data lines; A second sense amplifier group consisting of n (m) n ≧ 1) sense amplifiers whose inputs are connected to any one set (or one) common output line of the common data output lines of the sense amplifier group. L (L≧2) sense amplifier groups connected in cascade in the following order as shown below, and at least one sense amplifier group for each of the corresponding sense amplifier groups.
1. Activation means for selecting and activating each of the sense amplifiers by a predetermined Y-axis selection signal input manually. (2) Each sense amplifier of the first sense amplifier group is connected to any one set (or one line) of the common data i of a plurality of data lines. The semiconductor memory described.