JPS60695A - Memory circuit - Google Patents

Abstract

PURPOSE:To realize a large capacity and high speed RAM by inserting an IF circuit taking a column decoder output as gate timing between a sense amplifier and an input/output dat bus and adopting a static register as the IF circuit. CONSTITUTION:A register 32 saving temporarily a digit line potential is provided as the IF circuit coupling dynamic logic and static logic, and the random access of the column system is conducted in high speed by isolating a digit line of the dynamic logical system and the static register after data saving. A sense amplifier 31 amplifies a potential difference of the digit line. Then a signal amplified by energizing write signals phiL, phiL' is written in a register RG1. Then a data of each digit is extracted sequentially buses D, D' by energizing the read signal REY and the deenergizing the signal. A static differential amplifier 35 outputs this data. At write a data input buffer 36 is activated by an external write control signal, an input data is received and a data complementary signal appears on a bus 33.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit configuration between a dynamic logic memory cell and a static logic data input/output circuit.

In the following, for convenience of explanation, we will discuss a circuit using an N-channel M (J8FET).

For dynamic RAM, a 2-clock multi-address system is adopted from the 16th bit onwards.

) LA8 (H+ow Address 5trobe)
and CAS (Colurnn Address 5t
There are two tree blocks called ``robe'', the former of which controls the refresh operation of a one-transistor memory cell array, and the latter of which contributes to control of data input/output operations such as reading and writing.

The operation of the dynamic RAM will be explained below using all drawings. First, the timing waveform of the read cycle is shown in Figure 1. After RAS, CAS and sequential device are activated.
Using the former as a reference, set-up time and hold time are taken to input row addresses, and using the latter as a reference, all column addresses are input in 19 ways.

There are two types of definitions for the access time of output data (1) A'l'A (JUT) depending on the time interval tROD of activation of RAS and CAS. For this reason, tRoD(
A maximum standard value of tB(,D<
When tRoD(■■), it is defined by the access time tRAo measured from the activation time of l(, As. 1
(By activating As, the information of one transistor memory cell on the word line specified by the row address input from external ?415 is placed on each digit line and refreshed by the sense amplifier.) CAS is RAS.
Determine the connection point of the data input/output circuit to the refresh-related circuit operation by performing a read or read operation on the selected digit line, that is, the memory cell,
From the perspective of a dynamic RAM user, it is necessary to switch from a row address to a column address during the stROD period, and it is necessary to switch between multiple multi-address inputs (8Ke
W), so extra time is required. therefore,
In most cases, the access time is accepted as toAO in terms of %X. The basic requirements are that the collision % tROD be large and that toAo change at 6th gear.

In addition to normal read and write operations, an operation called page mode is incorporated into dynamic ILAM, so what is the timing waveform of a page read cycle? : Shown in Figure 2.

In FIG. 2, % R
AS remains activated, that is, at a low level, and CAS
By applying a pulse 7 and giving a column address to l' 4 based on the activation change from high level to low level, random reading or writing is performed for the memory cell on word U specified by the row address. It can be performed. This page mode cycle time is normal R
It takes about 2/3 of the AS/CAS cycle and is effective in making connections. The access time is the same as the regular cycle. Defined by AO. However, in actual use, higher speed operation is a problem in both cycle time and access time, and it is difficult for current dynamic RAMs to satisfy the Yasugi characteristics.

As mentioned above, for custom improvements in normal RA8/CAS cycle and page mode cycle, s t
Faster OAO and page mode cycle times are essential. This reflects the current dynamic
(In AM, this means that the challenge is to increase the speed of the circuit section controlled by CAS.

An object of the present invention is to provide a RAM f with large capacity and high speed operation.

In case of unforeseen circumstances, the dynamic logic is switched from the dynamic logic to the static logic at 7ζ when the cylinder speed is set to %CAS thread turn I+: 8'f and the cylinder speed is set to 7ζ, while taking advantage of the large capacity characteristics of the AM. If high-speed state, cycle time and access time performance of tsukuL(, hM) are realized by CAS circuits, the capacity of dynamic RAM will be longer than that of dynamic RAM.

lj AM with the high speed of static RAM
According to the present invention, 1 transistor type memory cells 34 arranged in 1M rows and N columns, N glueless amplifier arrays 31, and N
In the read/write data bus 33, which includes a register 32 composed of 11vA differential amplifiers, a static differential amplifier 35, and an input data generation circuit 36; a pair of transistors that are driven and have their drains connected to the digit line and their sources connected to the static register; By arranging a pair of transistors and a pair of transistors whose gates are driven by the write control signal, whose drains are connected to the data bus and whose sources are connected to the previous MdN valley digit lines, respectively, the l-transistor type dynamic memory Cell information can be quickly read out from the readout circuit 35 in the state and operation, and when writing, the data bus and digit line can be directly connected without using a static register that is activated at the time of reading. By doing so, it becomes possible to write at an unprecedented high speed.f: A memory circuit with characteristics can be obtained.

FIG. 3 shows a circuit block of l(AM) according to the invention, RAS is input to the RAS timing generation circuit 40,
This outbreak IL! 1 path 40 to row address inverter 37
A control signal (not shown) for energizing all of the row decoder 39, memory cell array 34, and sense amplifier 31 is generated (not shown), and the CAS timing source regeneration circuit 41 receiving CAS is brought into an operating state. CAS timing generation circuit 4
From 1 onwards, there are a register 32, an input/output data verse, a column address buffer 38, a column decoder 43, a pull-in timing generation circuit 42. Each issue that controls the data manual buffer 36 and the data output cover 35 is generated.

In order to realize high-speed state logic, it is essential to insert an interface between the sense amplifier 31 and the input/output data bus 33 that uses the column decoder output as the gate timing.
The basic configuration of the present invention will be explained with reference to FIG. 4.

Digit 1) uLt, 1) Sense amplifier 31 in Ll
-1 is combined, digit line 1)L2.1)L2 v
A C sense amplifier 31-2 is coupled thereto. Other sense amplifiers and digit lines (not shown) are similarly configured. In the present invention, data save register blocks 32-1, 32-2 are provided for each sense amplifier 31-1 and 31-2.
ffi will be established. A transistor Q1. Q3, and transistors Q2, Q4, which read out data held in the register RG1 to the data node 33-1, 33-2 in response to read signals R and EY1. Digit line 1) Ll, 1) Ll and No (S 33-1.33-2
Transistor Q20. Q21 is the signal WE
The connection and separation of the digit line and the bus are controlled in response to Y1. The basic internal operations of the one-transistor type dynamic memory and static memory are already known and detailed explanations will be omitted. In dynamic logic, after selection of memory cells by word lines and amplification of memory cell information by sense amplifier 8A.

The potentials of the valley digit lines DL and IJL are set to the power supply level and the ground potential so that the difference in level between them is maximized.

On the other hand, in static logic, memory cell selection,
When the sense amplifier 31 amplifies memory cell information, the load transistor introduced between the digit line and the power supply terminal, the digit line selection gate transistor, the memory cell selection gate transistor driven by the word line, and the memory cell are configured. In order to enable even higher speed operation using a static ratio circuit formed by a Noribu flop, the ratio is usually set so that the potential difference between each digit line is approximately several tens of QmV at most. For this reason, it is impossible to directly connect dynamic logic and static logic, and some kind of interface is recommended.

As this interface, the present invention provides registers 32-1 and 32-2 for temporarily saving the gauge and the line potential.
After data is saved to the register, the dynamic and logic digit lines are insulated from the status and registers, making column-related random access faster than the conventional page mode. This is the basics.

A specific example of the configuration of the circuit shown in FIG. 4 is shown in FIG.

Resistor RGI is load resistor 1111. kL2,)
yinshixriQ23*Q24. 7S1 composed of Q28. This is realized with a J-flop. Transistor Q2
1. (, l, 30 is for bus 33-1.33-2t pre-charge. Word AWL and Daijitsu)
At the intersection with NLIL, a memory cell MC is connected to a dummy word line DWL and a digit I? 5! ] A dummy cell DC is arranged at the intersection with JL. Sense amplifier 31 is composed of transistors Q1t to Qta.

FIG. 6 shows the operating waveforms of the circuit of FIG. 5. First, the word selection signals WL and DWL are activated and a digital signal is selected.

ff1fil) The potentials of the memory cells and dummy cells are read to L and DL.Then, by activating the latch signal SEt, the sense amplifier 31t is operated.The potential difference of the digit line is amplified.Then, the mourning signal φL
φ1' is applied to write the amplified signal on the digit line to register RG(1).

Next, the rye output signal EY1'i is energized → deenergized, and 1 (EY2 energized → deenergized...) EYN is energized → deenergized, so that the data of each digit is sequentially Take it out to the bus (1), l)). Bus 33- (0
)' potential is VDD - VT (VDD: power supply voltage * VT
: M U 8 transistor threshold) level, 33
-2(0) is transistor Q30. Q2 s, Q2
4 and the level determined by the ratio of Q28, and as a result, the differential voltage of 33-1°33-2 is the optimum cooling number 1.
It becomes OOmV. After this, transistors Q32 to Q3
Static differential amplifier 35 consisting of 6 operates upon receiving this potential difference, and is further amplified by two stages of static differential amplifiers to quickly transmit memory cell information to the output terminal.

On the other hand, when writing U, external write control No. 1R WE (
In response to the restriction i41f of [li not shown], the data person cover 7a 36 is activated, receives external input data, and the data true correction number 1g is transferred to the data bus 33-1. : Appears in 33-2.

Generally speaking, the worst case for data writing is when data opposite to the read data is written to the same memory cell after a read cycle.

This will be explained using FIG.

When the read cycle is completed, the read static 1↑111 signal 1 (, EY is lowered to 14L, the register, data bus, and gold insulation M i' Four WEs are applied.When the dynamic memory cell 1W signal is turned on, it is essential to keep the physical "'1" level as low as possible (usually the power supply level).

The input data generation circuit generates outputs completely separated into power level and ground level. At this time, the load transistor Q29. Q3G control black, ri L
S is set to fall in order to cause the potential change of the data bus to occur as quickly as possible. In this bale, the fertilization control clock WEYI rises, turns it on, and transistor Q20.
Q27 (JNL) transfers the write data on the data bus to the digit line without going through the register.The potential of the clock wgy'i should be at least the VDD+vT level to sufficiently increase the memory cell write level. It will be set up so that it will become.After this, W
Energize EYi and write data sequentially in the same way.

As described above, according to the present invention, the large capacity configured by the one-transistor type memory cell and sense amplifier array of the existing dynamic MO8RAM is combined with the interface circuit that connects the data bus system of the existing static M (JS RAM). By combining these, a completely new RAM that has both high speed and high speed can be realized.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams showing the operation timing of the current dynamic IW4, and Figure 1 is a diagram showing the operation timing of the current dynamic IW4.
AS cycle, Figure 2 shows page mode, Figure 3
The figure shows an interface between a one-transistor memory cell series amplifier based on the VC of the present invention and a static logic data bus.
FIG. 4 is a block diagram of the RAM using the interface, FIG. 4 is a diagram showing the configuration of its interface circuit, FIG. 5 is a diagram showing a specific embodiment of the present invention, and FIG. 6 is a diagram showing its operating waveforms. Figure 7 is the operating wave in the write mode of the present invention]
This is a diagram of all I.

Claims (1)

[Claims] One-transistor memory cells arranged in M rows and N columns (!
: A dynamic memory cell array consisting of s and Nm refresh sense amplifiers, a register consisting of N static differential amplifiers, another static differential amplifier, and an input data source generation circuit. a first pair of transistors connected between the digit line and the register; Driven by the protrusion control signal,
a second pair of transistors connected between the data bus and the register, and a third pair of transistors having gates driven by the write control signal and connected between the data bus and the N valley digit lines. A one-transistor type dynamic memory cell with a pair of transistors can read out information at high speed using a readout circuit that operates in a static state.In addition, when writing data, data can be read directly without using a static register that operates during reading. A special feature of this memory circuit is that it connects the bus and digit lines.