JPH0340291A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To allow the sure reading out of data without the collision of the data of a dynamic memory cell and a static memory cell at the time of data transfer by providing means for stopping the power source supply to the static memory cell before the data of the dynamic memory cell is transferred to the static memory cell. CONSTITUTION:The above-mentioned memory is so constituted as to stop the power source supply to the static memory cell 60 by the power source supply control means 110, 120 before the data of the dynamic memory cell 40 is transferred to the static memory cell 60. The state of the static memory cell 60 is, therefore, put into a blank state at the time of the transfer of the data and the influence of the static memory cell 60 on the data state of the dynamic memory cell 40 is obviated. The collision of the data is averted without dropping the driving capacity of the static memory cell in this way and the erroneous reading out is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a large-capacity, high-speed semiconductor memory.

(Prior Art) A dynamic memory has a high bit storage density per unit area in that a storage cell is composed of two elements: a transfer FET and a storage capacitor. For example, it is possible to achieve a bit density that is approximately three times that of a static memory in which the memory cell is composed of six elements. In this respect, dynamic memories are mainly used as large-capacity semiconductor memories. On the other hand, static memory is suitable for high speed and low power consumption, and is therefore used in the field of small-capacity, high-speed memory and low-power memory.

As a specific example of a conventional large-capacity dynamic memory, the circuit described in Japanese Patent Application Laid-open No. 186289/1983 is
As shown in the figure. Bit line B and white each have a PMO for transfer.
A dynamic memory cell consisting of an S FET QM and a storage capacitor C8 is connected. Word line WN is connected to the gate of each transfer PMOSFET Q.
' WN+1 is connected, and this word line WN ' W
Nil is connected to row decoder RD. word line WN,
WN+1. is driven by row decoder RD. Bit line B.

A parasitic capacitance CB is associated with the voltage.

Bit line B and 100 are further connected to a precharge circuit and a sense amplifier circuit.The precharge circuit is
Consists of NMO8FET NPI, NF2°NF2.

The sense amplifier circuit is composed of six FETs: a cross-coupled NMO8FET pair N1, N2, a latch NMO3FET N3, a cross-coupled PMOS FET pair PI, P2, and a latch PMO3FET P3. Each of the bit line pairs B and white is selectively connected to a data line pair I10 . I10 respectively. Data line pair I10. I10 is connected to the data input terminal DIN via the manual buffer B1, and to the data output terminal via the output buffer BO. Connected to ut. Address signal ARc applied from the outside is sent to address buffer ADS.
The row address AR is strobed in synchronization with the row address rope signal φ and sent to the row decoder RD, and the column address Ac is strobed in synchronization with the column address strobe signal φAC and sent to the column decoder CD.

The operation of this dynamic memory will be explained next.

Before row address strobe signal φAR is input, φ
Po is input, and the precharge circuit operates to precharge the bit lines B and [3 to the intermediate potential VD. When the row address strobe signal φAR is made aqua-live, precharging is completed, the row address is strobed in synchronization, and the row WN at the address selected by the row decoder RD changes from the H level to the L level, and the row WN The connected transfer FET QM becomes conductive, and the information in the storage capacitor C8 of the selected memory cell is transferred to the bit line B.
Hail above. That is, when the information in the storage capacitor C8 is "1", the potential of the bit line 100 changes from VD to VD+.
When the information in the storage capacitor Cs is "0", the potential of the bit line 100 changes from VD to VD-ΔV. Here, ΔV-CV/2 (CB+C8). After that, the sense amplifier latch FET N3. The latch phase signals φN and φP are manually applied to the gate of P3, and the latch FET
N3. P3 becomes conductive. As a result, the minute signal ΔV
is amplified, and if the information in the storage capacitor C8 is "1", the bit line 100 becomes the potential ■co, and the bit line color becomes the potential O. Conversely, if the information in the storage capacitor C8 is rOJ, the bit line 100 has a potential of 0, and the bit line 0 has a potential of V. It becomes 0. After row address strobe signal φAR is activated, column address strobe signal φAC is activated and a column address is input to column decoder CD.

The selected column Y is selected according to the selected column address,
NMO3FET pair for transfer gate in selected column T□I' Td
conduction, data line pair I10°Ilo and bit line pair 8
1 day is connected. According to read control signal φ and write control signal φW, output buffer BO1 and input buffer B1 are activated, respectively, and a read operation or a write operation is performed. While row address strobe signal φAR is active, column address strobe signal φAC is continuously changed, column addresses are changed one after another, and read or write operations are continuously performed within the same row. This kind of read/write operation is called page mode operation.
The maximum number of cycles in this page mode is limited because refresh operations must be performed at regular intervals. For example, in a 256-bit memory, the refresh cycle is 256 cycles/4 ms, and refresh is required at a rate of about every 16 μS, but the page mode cycle is 160 ns, which requires refreshing about every 100 cycles. The maximum number of modes is limited to 100 or less.

Also, for example, Yamada et al. rAuto/5ell'Rel'
64Kbit MOS dynamic RA with built-in resh function
MJ (Transactions of the Institute of Electronics and Communication Engineers, Vol. JGG-C)
No. 1, page 62, January 1983) describes a device that has a built-in timer and refresh counter, and performs self-refreshing based on refresh counter information counted and mapped by the timer. However, in this semiconductor memory, the sense amplifier is used for refresh operation during self-refresh, so during the self-refresh period, it is not possible to perform read/write operations by externally specifying addresses not only in the row direction but also in the column direction. Ta.

Such conventional semiconductor memories have the following problems. ■Since the parasitic capacitance of bit lines and data lines is large,
access time and cycle time for read/write operations,
Page mode requires long cycle times and is slow. There is a maximum value for the number of refresh cycles in page mode for a column address change with the 0 row address fixed.

■Read/write access to memory is not possible during self-refresh. ■Power consumption is high because it is necessary to repeat the row selection operation every certain repetition of the page mode cycle even though the same row is being accessed.

In order to solve these problems, a semiconductor memory that combines the high bit density of dynamic memory and the high speed of static memory has been proposed by Komyosha (
(Japanese Patent Application No. 113924/1982).

In this memory, data for one row of dynamic memory is transferred to a static memory row, and reading is performed by taking advantage of the high speed of the static memory, thereby improving the overall access speed.

(Problem to be Solved by the Invention) However, when transferring data from one row of cells in a dynamic memory to a corresponding static memory cell, both are directly connected by a bit line. will collide. For example, when the dynamic memory stores “1” and the static memory is in the “0” state at the time of reading,
Data collides and a large current (through current) that is more than twice the normal flow flows. If such a data collision occurs,
- Data from the side that has the ability to supply current within the membrane will be retrieved. As a result, there is no problem when data from the dynamic memory is retrieved, but erroneous reading occurs when information from the static memory is retrieved.

Therefore, it is an object of the present invention to provide a semiconductor memory that can prevent such data collisions from occurring and prevents erroneous reading by Vj +l=.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor memory according to the present invention includes a dynamic memory cell array in which dynamic memory cells for storing information are arranged in a matrix in the row direction and column direction, and dynamic memory cells in the dynamic memory cell array. A word line that is commonly connected in the row direction, a bit line that is commonly connected to the dynamic memory cells in the dynamic memory cell array in the column direction, and the bit line are paired, and the potential difference between the paired bit lines is sensed. A semiconductor memory comprising: a sense amplifier circuit row comprising a plurality of sense amplifier circuits for amplification; and a static memory cell row comprising static memory cells corresponding to dynamic memory cells in the row direction in the dynamic memory cell array; Transfer gate means for transmitting information between static memory cells in a cell row and their corresponding bit lines, and row selection means for selecting a word line in a dynamic memory cell row consisting of dynamic memory cells at a desired row address. a column selection means for selecting a static memory cell at a desired column address in the static memory cell row and transferring information between the static memory cell and a data line; and controlling power supply to the static memory cell. power supply control means, wherein the power supply control means stops power supply to the static memory, and the dynamic memory cells commonly connected to the word line selected by the row selection means When the row information is transferred to the static memory cell row by the transfer gate means, the power supply control means supplies power to the static memory, and the desired information is transferred via the data line selected by the column selection means. It is characterized in that it performs an operation to read information from a static memory cell at a column address.

Further, according to the semiconductor memory according to the present invention, a dynamic memory cell array in which dynamic memory cells for storing information are arranged in a matrix in the row direction and column direction;
The bit line is paired with a word line to which the dynamic memory cells in the dynamic memory cell array are commonly connected in the row direction, and a bit line to which the dynamic memory cells in the dynamic memory cell array are commonly connected in the column h'' direction, In a semiconductor memory comprising a sense amplifier circuit row consisting of a plurality of sense amplifier circuits that sense and amplify the potential difference between the paired bit lines, static memory cells corresponding to dynamic memory cells in the row direction in the dynamic memory cell array a dynamic memory comprising a static memory cell row consisting of a static memory cell row, a transfer gate means for transmitting information between the static memory cell in the static memory cell row and its corresponding bit line, and a dynamic memory cell at a desired row address. row selection means for selecting a word line of a cell row; column selection means for selecting a static memory cell at a desired column address in the static memory cell row and transmitting information between the static memory cell and the data line; power supply control means for controlling power supply to the static memory cells, wherein the power supply control means stops the power supply to the static memory, and the word lines selected by the row selection means When the information of the connected dynamic memory cell row is transferred to the static memory cell row by the transfer gate means, the power supply control means supplies power to the static memory, and the column selection means selects the column selected by the column selection means. A read and/or write operation of information in a static memory cell at a desired column address is performed via a data line, and the information in the static memory cell row after the read and/or write operation is transferred by the transfer gate means. ,
It is characterized in that data is transferred and rewritten to the dynamic memory cell row commonly connected to the word line selected by the row selection means.

(Function) In the semiconductor memory according to the present invention, power supply to the static memory cell is stopped before data in the dynamic memory cell is transferred to the static memory cell. Therefore, when data is transferred, the state of the static memory cell becomes a blank state, and the static memory does not affect the state of data in the dynamic memory. Therefore, data collisions can be avoided without reducing the driving performance of the static memory.

[Embodiments of the invention]

A semiconductor memory according to an embodiment of the present invention is shown in FIGS. 2 to 4.
As shown in the figure. FIG. 2 shows the layout on a chip of the semiconductor memory according to this embodiment. This semiconductor memory has an IM word x 1 bit configuration, and has 10 address signal terminals A. - Add 6 to A9. This address signal terminal A1
An address signal obtained by multiplexing a row address and a column address is input to ~A9. In addition, this semiconductor memory has a chip enable signal terminal CE, a human power data signal terminal D, an output data signal terminal D, and an IN'.
out-read/write signal terminal W1 has row address strobe signal terminal RAS, refresh enable and ready signal terminal RRDY. It also has a power terminal 1g, a terminal terminal VDD, and a ground terminal V38.

This embodiment has a redundant configuration including 20 spare rows and 02 spare columns, with (512Xn) rows and (10
Two dynamic memory cell arrays 40 each consisting of 24+n 2 ) columns of dynamic memory cells 400 are arranged on the left and right. Bit line pairs B and 9 of the dynamic memory cell array 40 each have (1024+n 2 )
A sense amplifier circuit 20 consisting of sense amplifiers is provided.

Further, in this embodiment, a static memory cell row 60 consisting of (1024+n 2 ) static memories 600 is provided via the left and right dynamic memory cell arrays 40 and the transfer gate means 50, respectively. Static memory cell row 60 is located at the center and is arranged adjacent to data line pairs 151 and 152 arranged on the left and right sides, with column decoder 90, which is column selection means, in between.

Static memory cells 600 in a selected column selected by column decoder 90 are connected to data line pair 151, 152. The word line 11i constituting the row line of the dynamic memory cell array 40 is connected to a row selection circuit 11 which is a row selection means.
Selectively driven by 0.

Further, a noise killer 100 is provided on each of the word lines 11i for the purpose of preventing a floating potential state. An address buffer circuit 120 is provided to supply external address signals to the row selection circuit 110 and column decoder 90. Further, a refresh counter 170 for supplying an internal address signal for auto-refresh or self-refresh to the row selection circuit 110, and a timer circuit 160 for manually inputting power to the refresh counter 170 are provided. Data line pair 151
, 152 have a data input circuit 141 and a data output circuit 1.
A data circuit 140 consisting of 42 is provided.

Furthermore, the semiconductor memory according to this embodiment includes a control circuit 130 that controls all of these circuits in synchronization.
has. The control circuit 130 has a clock generator and controls various operations such as read, write, and refresh. In this embodiment, the left and right dynamic memory cell arrays 40 are activated and operated at the same time, but the refresh cycle is such that one row each of the left and right dynamic memory arrays 40 is refreshed synchronously, and each memory cell is refreshed every 4 ms. , the overall semiconductor memory is 512 refresh cycles/4m
The number of refresh cycles is s.

FIG. 3 is a block diagram showing the semiconductor memory according to this embodiment by functional block. In FIG. 2, the dynamic cell array 40 and the sense amplifier enclosure 2 are divided into left and right sides.
0, static memory cell row 60, data line pair 151
, 152, and the row selection circuit 110, one blower is shown in FIG. Also, the sense amplifier circuit 20
, dynamic memory cell 400, transfer gate circuit 50
, static memory cell 600 and data line pair 151 .
A concrete circuit of the m-th column including 152 is shown in FIG. Also, a precharge circuit 10 for precharging the bit line pair B, 3, a dummy cell 30, and a static memory cell 40.
0 precharge circuit 70, static memory cell 6
A column selection gate circuit 80 is provided for selectively connecting data line pair 151 and 152 to data line pair 151 and 152 using column decoder output signal Y.

The concrete circuit of the m-th column is as shown in FIG. has been done. This N.M.O.
3FET II.

12 constitutes a precharge circuit 10.

The bit line pair B, 100 is provided with a sense amplifier circuit 20 consisting of a cross-coupled circuit consisting of PMOS FETs 23 and 24 whose drains and gates are cross-coupled to each other, and a cross-coupled circuit consisting of NMO3 FETs 21 and 22. It is being Bit line B is connected to the drains of PMOS FET23 and NMOS FET21,
The bit heath is PMOS FET24, NMO8, FE
Connected to the drain of T22. cross-linked P
The sources of MOS FET23 and 24 are connected to the positive polarity sense signal 1jl132H, and the cross-coupled NMO5FET2
The sources of signals 1 and 22 are connected to a negative sense signal line 132b. The sense signals are connected to these sense signal lines 132a.
, 132b, the sensing operation is controlled. Also, bit line B.

One end of a dummy capacitor 31 constituting a dummy cell 30 is connected to each of the dummy capacitors 31 and 31.
The other ends are connected to dummy words m101 and m102, respectively. These dummy cells 30 are used when sensing the dynamic memory cells 400. Bit line pair B
, 100 are provided with a dynamic memory cell 400, the drain of a transfer FET 41 is connected to the bit lines B, 13, and the gate is connected to the words 111, 112.

Bit line B, 100 is NMO5FET5 for transfer gate
1.52 static memory bits llBs,
Connected to BS. Static memory bit line B
600 static memory cells are provided in S and BS. The static memory cell 600 consists of an NMO3FET 61.62 and a PMO3FET 63.64 whose drains and gates are cross-coupled. NMO5F
The drains of ET61 and PMOS FET63 are connected to the static memory bit line BS, and the drains of NMO3FET
62, the drain of PMOS FET 64 is connected to static memory bit line BS. PMOS
The sources of FET63 and FET64 are commonly connected to the positive polarity static memory control line 136a, and NMO3FET61
．． 62 sources are commonly connected and connected to a static memory control line 136b of negative polarity. Each of the static memory bit lines BS and BS is a PMOS FE.
Connected to @source line 8 via T71.72. Furthermore, the static memory bit lines BS and BS are made of NMO3FE.
data line pair 151.15 via T81.82 respectively
Connected to 2. The gates of the NMO3FETs 81 and 82 are commonly connected and connected to the Y decoder output line 91.

The entire semiconductor memory shown in FIG. 3 is constructed by arranging the circuits shown in FIG. 4 in (1,024+n2) columns in the column direction.

The row selection circuit 110 receives a row address signal ARO from the outside.
= Al? 8 or internal refresh address CRO”-CR8 specified by refresh counter 170
are decoded, and the (512+n) word lines 111, 112 . . . . selects one of the mountains and outputs a selection signal. Column decoder 9
0 indicates column address signals Aco to AC9 and block selection address AI? 9 selects a predetermined column Y, and selectively connects the data line pair 151, 152 to the only static memory cell 600 of the left and right static memory cell rows 60 by the column selection gate circuit 80. data line pair 1
51 and 152 are connected to data input terminals via a data buffer circuit 141, and to data output terminals via a data output buffer circuit 142. 1. connected to. The timer circuit 160 is connected to the human power line 6 of the row address strobe signal RAS, and the row address strobe signal Iτ controls the count human power signal 161 from the timer circuit 160 to the internally provided refresh counter 170. . refresh counter 170
It also exchanges signals with the control circuit 130. For example, the control circuit 130 controls the counting operation of the refresh counter 170 using a signal 1317. Conversely, refresh counter 170 notifies control circuit 130 of its operating state through status signal 172. The address buffer circuit 120 is
External address A by signal 1312 from control circuit 130. -A9wo, row address ARO=AR8
and column address Aco~A and block selection address A
I? The data is divided into 9 parts and output to the row 9 selection circuit 110 and the column decoder 90, respectively.

The control circuit 130 receives the address signal Ao-A9, generates a clock pulse synchronized with the change in address 1=, and also generates an address strobe signal RA.
S, chip enable signal CE, read/write (:
No. W, refresh enable and ready signal RR
Upon receiving DY, it generates various control signals. These control signals include a signal 1310 that controls the noise killer 100, a signal 1317 that controls the timer circuit 160, a bit line B, a hundred precharge control signal 131, sense signals 132a and 132b to the sense amplifier circuit 20, and a row selection signal. Signal 1311 to circuit 110, transfer gate signal 135 to transfer gate circuit 50, control signal 1 to static memory cell 600
'36 a.

136b, static memory bit iBS.

There are a precharge control signal 137 for the BS, a control signal for the address buffer circuit 120, a control signal 1314 for the data manual buffer 141, a control signal 1315 for the data output buffer 142, and the like.

Next, the operation of this embodiment will be explained using FIGS. 5 to 7.

5 and 6 show the timing of the operation of this embodiment. Row address strobe (during a period T4 after a certain period T3 has elapsed after the number 1X becomes H level,
Except for the refresh period T6, the bit line B [3 is in a precharged state. Row address strobe signal RAS
In synchronization with the falling from H level to L level, address signal amount o -A ta becomes external row address signal A.
It is taken into the address balance circuit 120 as Ro to AR8 and the block selection address AR9. When external row address signal ARo-AR8 is input, row selection circuit 1
10 decodes row address signals ARO to AR8 while being clock-controlled by a control circuit 130 to select a predetermined word line.

Information stored in the dynamic memory cell 400 of the selected row is amplified by the sense amplifier circuit 20 in synchronization with the row address strobe signal RAS. In this way, a total of 2 × (1024 + n 2 ) memory cells 4 on the left and right
00 information is amplified by 2X (1024+n2) sense amplifier circuits 20. Thereafter, the gate of the transfer gate circuit 50 is opened in synchronization with the row address strobe signal RAS, and the left and right 2
The signal amplified by the sense amplifier circuit 20 is transferred to n 2 ) static memory cell rows 60 at once.

Let T be the period from when the row address strobe signal RAS shifts from the H level to the L level until the row selection, sense amplifier operation, and transfer operation are completed. T+
is approximately 40 n5cc.

After the period T1, during the period when the row address strobe f≦RAS is at L level, that is, during the period T2, this semiconductor memory operates as a static memory consisting of 2×(1024+n 2 ) static memory cells 600. This static memory is external address signal amount.

-A9 to column address: AA,. - Operates as Ac9, block selection address AR9 and column address ACO = A
Information is exchanged between the static memory cell 600 of the column designated by C9 and the data line pair 151.degree. 152, and read/write operations are performed. During this period T2, the transfer gate circuit 50 remains completely closed, and the static memory cell row 60 is read/written completely independently of the dynamic memory cells 40 and the sense amplifier circuit 20.
Performs a write operation. That is, when the chip enable signal CE is at L level and this chip is selected, and the read/write signal amount is at H level, a read operation is performed and the information of the static memory cell 600 is transferred to the data output terminal DoUT.
When the read/write signal amount is at L level, the information at the data input terminal DIN is output to the static memory cell 60.
Performs a write operation to 0. During this period T2, the timer circuit 160 instructs the setting of the self-refresh period T5 and the count-up operation of the refresh counter 170. The timer circuit 160 performs a refresh operation once every 6 μsec, for example. That is, the western refresh address signal CRo of the refresh counter 170
～CR8 is decoded, one word line of the (512+ n l ) tree of the left and right dynamic memory cell arrays 40 is selected, and the information of the selected dynamic memory cell row is read and the sense amplifier circuit 20 reads out the information of the selected dynamic memory cell row. Sense, amplify and refresh.

When the refresh operation is completed, the word line is closed, the refresh counter 170 is counted up by one, and the bit line pair B, 9 is precharged. Approximately 6 μSee after the g-th row is refreshed in this way, (N+
1) The row is refreshed, but even during this refresh period, this semiconductor memory exchanges information between the static memory cell row 60 and the data line pair 151, 15.2, and the read/write as a semiconductor memory The write operation is performed independently of the refresh operation. During this refresh period T5, this semiconductor memory outputs an L-level refresh signal RRDY to the signal terminal 9. This ready signal RRDY is for informing the outside whether this semiconductor memory is in a refresh state or not.When it is at L level, it indicates that it is in a refresh state, and the row address strobe signal RAS must not be changed. Inform you of the condition. Note that it is also possible to provide a refresh enable signal and forcibly set this signal to a low level from the outside to start auto-refresh without relying on the timer circuit 160 by slightly changing the circuit design.

Next, row address strobe signal RAS is changed from L level to H level.
When the static memory cell row 60 changes to the level, the information in the static memory cell row 60 is synchronized with the transition of the row address strobe signal RAS, and is transferred to the sense amplifier circuit 20 via the transfer gate circuit 50.
are transferred simultaneously.

External row address signal AI? which was last strobed when row address strobe signal RAS was at H level? 0~A
By decoding R8, one word line of the dynamic memory cell array 40, which is the contents of the static memory cell row 60, is selected. In this way, the information in the static memory cell row 60 is written as is into this selected dynamic memory cell row, and then the word line is closed.

In period T3, the information in the static memory cell row 60 is transferred to the sense amplifier circuit 20, and the information is written into the dynamic memory cell array 40 until the word line is closed. Then the row address strobe (
A self-refresh operation is performed approximately every 6 μSee during the period T4 in which the a-number RAS is at H level. In this way, the semiconductor memory according to this embodiment can perform the same operation as a static memory for the row to which the row address has been strobed, and can independently perform self-refreshing of the read/write operations to the static memory to the dynamic memory cells. can perform actions.

Therefore, this semiconductor memory has both the advantages of static memory, such as high speed and low power consumption, and the advantages of dynamic memory, which has high bit density packaging.

Next, the operation of the circuit shown in FIG. 4 will be explained using FIGS. 7(a) and 7(b). Initially, the precharge IM line 131 is at H level, the precharge signal line 137 of the static memory cell 600 is at L level, and the precharge circuit 1
The NMOS FETs 11 and 12 of 0 become conductive, and the bit line B and 100 are precharged to L level, and the PMO3FE of the precharge circuit 70 of the static memory cell 600
T71.72 becomes conductive and static memory bit line B
S and TT are precharged to H level. Next, when the row address strobe signal RAS transitions from H level to L level at time to, external row address signals AR8-AR8 and block selection address AI?
9 is read, and at time 11, the precharge signal 131 goes to L level, and the precharge signal 1 of the static memory
37 becomes H level, NMOS FETl1.12
, the PMO3FETs 71 and 72 become non-conductive and the precharging ends.

Next, at time t2, the dummy word line 11 i'(i'-
1, 2) transitions from L level to H level, and word line 11 selected by external row address ARO=AR8
i' (i-1, 2, . . . , 512) transitions from H level to L level. Now i' is 1 when l is an odd number
, 2 when i is an even number. As a result, the transfer FET 41 of the dynamic memory cell 400 in the first row is made conductive, and the information on the storage capacitor 42 is read out to the bit line B or white. Here, the capacitance of the dummy capacitor 31 connected to the dummy word line 101' is equal to that of the storage capacitor 4.
2, and the information in the dynamic memory cell 400 is read out as the potential difference between the bit line B or bit line pair.

Now, for example, if word line 111 is selected, dummy word line 101 is selected.

The capacity of the storage capacitor 42 is CM, and the dummy capacitor 3 is
The capacitance of 1 is CD, the bit line B is B, and the capacitance of 100 is CB.

The information of the selected dynamic memory cell 400 is "1"
Notogi, that is, transfer FET 41 and storage capacitor 4
Assuming that the potential at the connection point 43 with the bit lines B and 13 is V, the potentials V(B) and V(day) of the bit lines B and 13 are as follows. Here, it is CD-1/2CM. If cM<CB, then

Conversely, when the information in the dynamic memory cell 400 is "0", that is, when the potential at the connection point 43 is 0, V (B). =0 Next, at time t3, the sense signal line 1 of the sense amplifier circuit 20
32a and 132b respectively go from L level to H level,
When the H level changes from the H level to the L level and a sensing operation is started, the minute potential difference between the bit line pair B and the bit line B is sensed and amplified, and when the information in the dynamic memory cell 400 is "1", the bit line pair B, The potential of 13 is (V (B), V (day)) - (Vo, 0), which is "0" and Kiha (V (B
).

V (B))-(0, VC), and is rewritten into the dynamic memory cell 400. Thereafter, at time t3, the dummy word line 10i' returns to the L level, and the word line 11
i returns to H level.

Next, at time t5, the transfer gate signal 1 of the transfer gate circuit 50
35 transitions from L level to H level, and transfer gate F
ET51 and ET52 are rendered conductive, and the potential signals of the static memory bit lines BS and BS heavy node line 21B are transferred. After that, the static memory control line 136a is marked t6.
, 136b change from L level to H level and from H level to L level, respectively, and the dynamic memory cell 4
Information of 00 is read into the static memory cell 600 through the sense amplifier circuit 20 and the bit line 82. That is, 136b>136a before time t6
In the state of , power is not supplied to the static memory cell 600, so it does not operate as a static RAM, or in the state of 136b<136a after time tG, the static memory cell 600 is supplied with 713rln. Operates as static RAM. By doing this, when the data in the dynamic memory cell is transferred to the static memory cell, the storage state of the static memory cell is a blank slate, so the data in both cells will not collide, and erroneous reading will not occur. Only that will happen.

Next, at time t7, the transfer gate circuit 50 becomes non-conductive, and then at time t8, sense (: line 132a.

132b changes from H level to L level/\ and from L level to H level/\, respectively, and the sense amplifier circuit 20 becomes disabled. Furthermore, at time t9, the precharge signal 13
1 changes from L level to H level, and bit line pair B100 are both precharged to OV by the precharge circuit 10. In this way, the operation of period T1 from time t to time tlo is realized.

Next, the refresh operation during period T5 will be explained. When the timer circuit 160 issues one self-refresh command every 6 μsec, the ready number RRDY is activated at time tl.
Changes from H level to L level at l. In synchronization with this, the precharge signal 131 changes from H level to L level at time t12.
level, the precharge operation is stopped, and time t
13, the internal refresh address signal CI? generated by the refresh counter 70? 0=CI? Word line 11j of the row selected by H (j=1.2...
, 512) and the dummy word line 10j'(j' is j
1 when is an odd number and 2 when it is an even number), and the information of the j-th row dynamic memory cell 400 is read out to the bit line pair B, 100 as a minute potential difference. Time t
At 14, the sense signal lines 132a and 132b are activated, the sense amplifier circuit 20 is latched, and the bit line pair B, 100 is sense-amplified and rewritten to the guiminac memory cell 400 at the beginning of row j.

That is, the information in the j-th row dynamic memory cell 400 is refreshed. Next, at time t15, the word line 11
j1 dummy word line 10j' is deselected, and when full
Sense signal line 132a at tt6.

132b are set to L level and H level, respectively, to release the latch of the sense amplifier circuit 20, and at time t17, the precharge signal 131 becomes H level, and bit line pair B, 100 is precharged to OV. Ready signal R at time tlg
RDY changes from L level to H level. time tll
The period from the time tlg to the opening of the precharge state is defined as a period T5 for the refresh operation.

Next, the row address strobe signal RAS changes from L level to H level.
When the level changes, the semiconductor memory according to this embodiment operates as follows. When the row address strobe signal RAS changes to H level at time t1°, the precharge signal 131 changes to L level at time t20, and the bit line 81
The precharge circuit 10 stops the precharge operation. Next, at time t21, the transfer gate signal 135 changes from L level to H level, and the static memory cell 600
information is transferred to bit line B, which is in a precharged state. After that, at time t2°, sense signal lines 132a and 1B2
b are respectively activated, and the sense amplifier circuit 2
0 is latched, and the information in the static memory cell 600 is amplified and latched by the sense amplifier circuit 20. Next, at special t23, the transfer gate signal 135 changes to L level and the transfer operation ends, and n, 'ff
1l External row address signal AI taken in to? o
= AI? The j-th row word line 11j selected in step 8 and the dummy word line 101' are selected. In this way, information in the static memory cell 600 is written to the dynamic memory cell 400 in the selected row j on the bit line 81 through the sense amplifier circuit 20. Next, at time t25, the word line 1111 and dummy word line 10i' return to their original states, and at time t2, the sense signal line 132
a and 132b go to L level and H level, respectively, and the sense amplifier circuit 20 is unlatched. At the same time, static memory control lines 136a and 136b go to L level and H level, respectively, so that power supply to static memory cell 600 is stopped, and writing to static memory cell 600 is started.

Next n! At j time t27, the precharge signal line 131 of the bit line 81st becomes H level, the precharge signal line 137 of static memory bit lines BS and BS becomes L level, and the precharge signal line of static memory bit lines BS and BS becomes L level. 137 goes to L level, bit line pair B
, 3 goes to L level, static memory bit line BS
, BS starts precharging to H level. Time t1
During the period T3 from 9 to time t28 following time t, information transfer from the static memory cell row 60 to the dynamic memory cell row is realized as described in 7 above.

After period T3, during period T4 in which the row address strobe signal RAS is at H level, period T5 occurs as shown in FIG. 7(b).
The same self-refresh operation is performed from time t' to t18' in the refresh operation period T6 during the period T4.
It will be done in the meantime.

1 This self-refresh operation is also performed by the internal timer circuit 160.
The internal refresh address CI? is updated approximately every 6 μsec by the command of 0= Perform CR9 by counting.

A specific configuration example of the address balance circuit 120 and row selection circuit 10 used in the semiconductor memory according to this embodiment is shown in FIG. 8(a). External address signal A is applied to external address signals approximately 3a to 3k. ~A9 is input. Of these, the external address signal A o -A s is inputted to the row address latch circuit 1200 and is input to the row address strobe signal RA.
It is latched by the latch signal 1312a disclosed to S.

The external address signal A o -A 9 is also input to the address balance circuit 120, and the control signal 1312b
The address balance circuit 120 is controlled by this, and the column address Aco-Ac9 can be obtained. The block selection phase address signal AR9 is a latch signal 13 that synchronizes the external address signal AR9 with the row address strobe signal RAS.
12a.

The row selection circuit 110 includes a multiplexer circuit 1100 and a row decoder and word line drive circuit 1110.

Multiplexer circuit 1100 is row address latch circuit 1
200 output signal 121 and refresh counter 17
Output No. 13 171 of 0 is selected as -h' by multiplexer control signals 1311a and 1311b and output to the row decoder and word line drive circuit 1110. Row decoder and word line driving circuit 1110 drives the row decoder and word line under the control of control signal 1311c.

The operation is as shown in FIG. 8(b), when the latch signal 1
312a rises from L level to H level, external address signal A. -A8 is the row address latch circuit 120
0 Heratsuchi is applied. Similarly, column address latch circuit 121
0 is the external address signal A at the rising edge of the latch signal 1312b.

~Latch A9. The latch signal 1312b is the falling edge of the row address strobe signal RAS or the external address signal A. - Output in synchronization with changes in A9. signal 131
1g is output in synchronization with the falling edge of the row address strobe signal RAS and the rising edge of the ready signal RRDY.
The multiplexer circuit 1100 continues to output the external address signal 121 in synchronization with the rise of this signal 1311a. The signal 1311b is outputted in synchronization with the output of the timer circuit 160, and therefore in synchronization with the fall of the ready signal RRDY. The multiplexer circuit 1]00 continues to output the peak refresh address signal 171 in synchronization with the rising edge of the signal 131lb. The row decoder and word line drive circuit 1110 is a control circuit.
The falling and rising edges of the row address (row address)/lobe signal RAS and the ready signal RR are determined by the row signals 131 and 1c.
Controlled in synchronization with the falling edge of DY.

As described above, according to this embodiment, the external address signal A1? selected by the row address strobe signal RAS? .

After information is transferred from the dynamic memory cell row selected by ~AR8 to the static memory cell row, it can be operated as a static memory in response to column address changes. At the same time, the dynamic memory cell array 40 and the four sense amplifiers 20 can independently perform a refresh operation.

〔Effect of the invention〕

As described above, according to the semiconductor memory according to the present invention,
Before transferring data from a dynamic memory cell to a static memory cell, there is a means to stop power supply to the static memory cell, so the storage state of the static memory cell is a blank slate, and when data is transferred, both There is no collision of data in memory cells, and reliable data reading becomes possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional semiconductor memory, FIG. 2 is a layout diagram on a semiconductor chip of a semiconductor memory according to an embodiment of the present invention, FIG. 3 is a block diagram of a quantity rate conductor memory, and FIG.
The figures are circuit diagrams of the retaining part of the same semiconductor memory, Figures 5, 6,
7(a) and 7(b) are time charts showing the operation of the same semiconductor memory, FIG. 8(a) is a circuit diagram showing a specific example of the address buffer circuit and row selection circuit of the same semiconductor memory, and FIG. Figure (b) is a time chart showing the operation of the same specific example. DESCRIPTION OF SYMBOLS 10... Precharge circuit, 20... Sense amplifier circuit, 30... Dummy cell, 40... Dynamic memory cell array, 50... Transfer gate circuit, 60...
... Static memory cell row, 70 ... Precharge circuit, 80 ... Column selection gate circuit, 90 ... Column decoder, 100 ... Noise killer, 110 ... Row selection circuit, 120 ... Address buffer 7 circuits, 10...
・Control circuit, 151, 152...data line,
160... Timer circuit, 170... Refresh counter, 400... Dynamic memory cell, 600
. . . Static memory cell, 1100 . . . Multiplexer concave path, 1110 . . . Drive circuit, 1200 .
- Row address latch circuit, 1210... Column address latch circuit.

Claims (1)

[Claims] 1. A dynamic memory cell array in which dynamic memory cells for storing information are arranged in a matrix in the row and column directions, and a word line that commonly connects the dynamic memory cells in the dynamic memory cell array in the row direction;
A sense amplifier comprising a bit line commonly connecting the dynamic memory cells in the dynamic memory cell array in the column direction, and a plurality of sense amplifier circuits that pair the bit lines and sense and amplify the potential difference between the paired bit lines. a static memory cell row consisting of static memory cells corresponding to the dynamic memory cells in the row direction in the dynamic memory cell array; and a static memory cell row in the static memory cell row and its corresponding one. transfer gate means for transmitting information to and from the bit line; row selection means for selecting a word line in a dynamic memory cell row consisting of dynamic memory cells at a desired row address; Column selection means for selecting a static memory cell of a column address and transmitting information between the static memory cell and a data line; and power supply control means for controlling power supply to the static memory cell, The power supply to the static memory is stopped by the supply control means, and the information of the dynamic memory cell row commonly connected to the word line selected by the row selection means is transferred to the static memory cell row by the transfer gate means. supplying power to the static memory by the power supply control means when transferring the data to the static memory;
A semiconductor memory characterized in that information read from a static memory cell at a desired column address is performed via the data line selected by the column selection means. 2. A dynamic memory cell array in which dynamic memory cells for storing information are arranged in a matrix in the row and column directions, and a word line that commonly connects the dynamic memory cells in the dynamic memory cell array in the row direction;
A sense amplifier comprising a bit line commonly connecting the dynamic memory cells in the dynamic memory cell array in the column direction, and a plurality of sense amplifier circuits that pair the bit lines and sense and amplify the potential difference between the paired bit lines. a static memory cell row consisting of static memory cells corresponding to the dynamic memory cells in the row direction in the dynamic memory cell array; and a static memory cell row in the static memory cell row and its corresponding one. transfer gate means for transmitting information to and from the bit line; row selection means for selecting a word line in a dynamic memory cell row consisting of dynamic memory cells at a desired row address; Column selection means for selecting a static memory cell of a column address and transmitting information between the static memory cell and a data line; and power supply control means for controlling power supply to the static memory cell, The control means stops power supply to the static memory, and the transfer gate means transfers information of the dynamic memory cell rows commonly connected to the word line selected by the row selection means to the static memory cell row. When transferring data to the static memory cell, the power supply control means supplies power to the static memory, and reads and/or writes information in the static memory cell at a desired column address via the data line selected by the column selection means. The transfer gate means transfers the information of the static memory cell row after the read and/or write operation to the dynamic memory cell row commonly connected to the word line selected by the row selection means. A semiconductor memory characterized in that it can be transferred and rewritten.