JPS6068728A - Digital-analog converter - Google Patents
Digital-analog converterInfo
- Publication number
- JPS6068728A JPS6068728A JP17771383A JP17771383A JPS6068728A JP S6068728 A JPS6068728 A JP S6068728A JP 17771383 A JP17771383 A JP 17771383A JP 17771383 A JP17771383 A JP 17771383A JP S6068728 A JPS6068728 A JP S6068728A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- emitter
- temperature
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は電流加算形I)/Aコンバータに於て特に精度
の艮いl)/Aコンバータに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current adding type I)/A converter, and particularly to a current adding type I)/A converter.
従来、第1図に示す様に電流加算形のD/I1.コンバ
ータは、■−2几のシダー抵抗用2及び足電流発生用ト
ランジスタ群1.各重み付けされた電流の出力部3およ
びベース駆動回路7/T、含んでいる。温度に対して電
流は定電流発生用トランジスタ群l内のトランジスタの
温度特性とルー2凡のラダー抵抗網2内の抵抗との温度
特性により影響される・これらの温度特性を全く保償し
ない場合電流の温度変化は数千ppml0ともなり、チ
ング内部や周囲の温度変化の影響を著しく受ける。Conventionally, as shown in FIG. 1, a current adding type D/I1. The converter consists of ■-2 cedar resistors 2 and a group of transistors for current generation 1. Each weighted current output 3 and a base drive circuit 7/T are included. The current with respect to temperature is affected by the temperature characteristics of the transistors in the constant current generation transistor group 1 and the temperature characteristics of the resistances in the ladder resistance network 2 of 2. If these temperature characteristics are not guaranteed at all Temperature changes in the current amount to several thousand ppml0, and are significantly affected by temperature changes inside and around the chip.
この電流はまた、基板のそりによるピエゾ効果に迭゛
よっても変化する。このように出力電流は稍KH悪く、
外からの影響で変化しやすいという欠点があった。This current also changes due to piezoelectric effects due to substrate warpage. In this way, the output current is a little KH bad,
The drawback was that it was easily subject to change due to outside influences.
本発明はかかる問題点を解決し精度の良い1)/A変換
装置上提供する事にある。The object of the present invention is to solve these problems and provide a highly accurate 1)/A converter.
不発明の1)/Afm装置は1足電流発生回路に於て基
準となる第1のトランジスタと、重み付は電流に比例し
た第lのトランジスタのエミッタ面積よりn倍のエミッ
タ面積°全も°踵 コレクタとベースが、第1のトラン
ジスタのコレクタとベースが共通で、かつエミッタが抵
抗1%2通して、第1のエミッタと接続された第2のト
ランジスタとを−aし、w2のトランジスタのエミ、り
面積と抵すLRで出力電流の補償がなされている事を特
徴とする。The uninvented 1)/Afm device has a first transistor that serves as a reference in a one-leg current generating circuit, and an emitter area that is n times larger than the emitter area of the first transistor whose weighting is proportional to the current. The collector and base of the first transistor are common, and the emitter is connected to the first emitter through a resistor 1%2, and the second transistor is connected to -a, and the transistor w2 is The output current is compensated by the LR which resists the emitter and rear area.
第2図は不発明の一実施例である0足電流発生用トラン
ジスタ群4を構成するq!r要素は、基準となる第1の
トランジスタ8と第1のトランジスタのエミッタ面積よ
り重み付は電流に比例したn倍のエミッタ面積をもつ第
2のトランジスタ9と抵抗RIOと葡宮んで構成されて
いる。各要素の第。FIG. 2 shows the q! The r element is composed of a first transistor 8 serving as a reference, a second transistor 9 having an emitter area that is weighted n times larger than the emitter area of the first transistor and is proportional to the current, a resistor RIO, and a resistor RIO. There is. No. of each element.
1のトランジスタ8のエミ、りはR−2Rのラダー抵抗
網5の所属の抵抗に接続され、各抵抗には定電流が与え
られている。谷トランジスタのベースはベース駆動回路
7からベース駆動のための足電圧が共通に与えられてい
る。6第1のトランジスタのコレクタは出力回路6内で
人力デジタル信号に応じてスイッチ全通して出力端子に
与えられ、出力端子でアナログ信号に合成されて出力さ
れる。The emitter of the transistor 8 of No. 1 is connected to the resistor of the R-2R ladder resistor network 5, and a constant current is applied to each resistor. The bases of the valley transistors are commonly supplied with a foot voltage for driving the bases from the base drive circuit 7. 6 The collector of the first transistor is supplied to the output terminal through a switch in accordance with the human input digital signal in the output circuit 6, and is synthesized into an analog signal at the output terminal and output.
第3図は定電流発生用トランジスタ群4の各要素を示し
たもので基準となる第1のトランジスタ8に流れる′電
流■crefはベース−エミッタ亀圧VBB に関係し
、次式で表わされる。FIG. 3 shows each element of the constant current generating transistor group 4. The current ``cref'' flowing through the first transistor 8 serving as a reference is related to the base-emitter voltage VBB and is expressed by the following equation.
温度に対して1crefはVBB VC依存するため負
の温度係数をもつ事は、すでに良く知られている−
(b)式はさらに次のよりに表わすことができる。It is already well known that 1cref has a negative temperature coefficient because it depends on VBBVC with respect to temperature. Equation (b) can be further expressed as follows.
ここで、Toは基準温度で例えば常温である。Here, To is a reference temperature, for example, room temperature.
■Go は絶対温度零度におけるノくンドギャップの電
圧、θは製造工程に依仔するノくラメータ、■BBOは
基準温就TOでのベース・エミッタ間福二である。■Go is the voltage across the gap at absolute zero temperature, θ is a parameter depending on the manufacturing process, and ■BBO is the base-emitter Fukuji at the reference temperature TO.
第2のトランジスタ9は、第1のトランジスタ8のエミ
ッタ面積エフn倍大きいので、ベース・エミッタ間電圧
V、Bはこれらのトランジスタ8と9とで差(ΔVBB
)が生じる。Since the second transistor 9 has an emitter area Fn times larger than the first transistor 8, the base-emitter voltages V and B between these transistors 8 and 9 are different (ΔVBB
) occurs.
=■、lnn、、、、、、、、、(Cl式(C)よハ第
2のトランジスタに流れる電流1゜□は
温度に刻してl。nは
上式(e)より正の温度係数をもつ事がわかる0式(b
)又は(b)′及び式(e) ffi用いて、温度係数
全かえる事ができる。= ■, lnn, , , , , , (from Cl equation (C)) The current 1゜□ flowing through the second transistor is expressed by the temperature, and n is a positive temperature from the above equation (e). Equation 0 (b
) or (b)′ and formula (e) ffi can be used to change the temperature coefficient completely.
第1のトランジスタ8と抵抗RIOの他端との共通点1
1の温度係舷は、次式(flでまる。Common point 1 between the first transistor 8 and the other end of the resistor RIO
The temperature berth of 1 is calculated by the following formula (fl.
すなわち式(f)の右辺全零とおき、几及びnvf−設
定すれば温度に対して保償される事になる。That is, if the right-hand side of equation (f) is set to zero, and the value is set to 几 and nvf-, the temperature can be guaranteed.
さらに温度分布kJ慮して各トランジスタのレイアウト
上では、第4図にボした様に、基準となる第1のトラン
ジスタ8全中心として、その両側に第2のトランジスタ
9及び9′全配置するとさらに温度に対して保償は良く
なシ、ピエゾ効果に対しても対策ができる。Furthermore, in consideration of the temperature distribution kJ, in the layout of each transistor, as shown in Fig. 4, it is possible to place the first transistor 8 as a reference in the center, and the second transistors 9 and 9' to be placed on both sides. It has good guarantee against temperature and can also take measures against piezo effect.
これまでに詳細に説明した様に、温度の変化によフ誤差
も著しく増加するが、不発明の補償回路を加え各トラン
ジスタを配置する事により、容易に精度の良いD/A変
換装置ができるという効果がある−As explained in detail so far, the error increases significantly due to temperature changes, but by adding an inventive compensation circuit and arranging each transistor, a highly accurate D/A conversion device can be easily created. There is an effect that
第1図は従来のD/A変換装置を示す回路図、第2図は
、不発明の一実施例によるi)/A変換装置を示す回路
図、第3図は本発明の一実施例による定流発生用トラン
ジスタの構成回路図、第4図は本発明の一実施例全具体
化したトランジスタ配置を示す平面図である。
1.4・・・・・・定電流発生用トランジスタ群、2゜
5・・・・・・几−2几ラダー抵抗綱、3.6・・・・
・・出力部。
7・・・・・・ベース駆動回路、8・・・・・・基準ト
ランジスタ。
9・・・・・・基準トランジスタのn倍の面積葡もつト
ランジスタ、10・・・・・・抵抗R% 11・・・・
・・端子。
〈二二
第3図FIG. 1 is a circuit diagram showing a conventional D/A converter, FIG. 2 is a circuit diagram showing an i)/A converter according to an embodiment of the invention, and FIG. 3 is a circuit diagram showing an i)/A converter according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a constant current generating transistor. FIG. 4 is a plan view showing the arrangement of transistors embodying an embodiment of the present invention. 1.4... Transistor group for constant current generation, 2゜5... 几-2㇠ ladder resistance wire, 3.6...
...Output section. 7...Base drive circuit, 8...Reference transistor. 9...Transistor with area n times that of the reference transistor, 10...Resistance R% 11...
...Terminal. <Figure 22 3
Claims (2)
回路に於て、基準となる第1のトランジスタと重み付は
電流に比例した第1のトランジスタのエミツタ面fI*
より1倍のエミッタ面積全もち、コレクタとベースが前
記第1のトランジスタのコレクタとペースと共通で、エ
ミッタが抵抗R[通して第1のエミ、りと接続された第
2のトランジスタとを有する4!を特徴とする1)/A
変換装置・(1) In the constant current generating circuit of the current force 1'' nose-shaped L)/A converter, the first transistor serves as a reference and the weighting is based on the emitter surface fI* of the first transistor which is proportional to the current.
has a total emitter area 1 times larger than that of the first transistor, the collector and base are common to the collector and the base of the first transistor, and the emitter has a resistor R [through which the first emitter is connected to the second transistor]. 4! 1)/A characterized by
Conversion device/
し、前記第12工び第2の部分トランジスタを前記第2
のトランジスタとなる↓うに配線した事t%徴とする特
許請求の範囲第1項記載のl)/A変換装置。(2) Same emitters on both sides of the first transistor. The first and second partial transistors each have a total area, and the twelfth and second partial transistors are connected to the second partial transistor.
The l)/A conversion device according to claim 1, wherein the wiring is arranged in such a manner that the transistor becomes a transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17771383A JPS6068728A (en) | 1983-09-24 | 1983-09-24 | Digital-analog converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17771383A JPS6068728A (en) | 1983-09-24 | 1983-09-24 | Digital-analog converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6068728A true JPS6068728A (en) | 1985-04-19 |
Family
ID=16035804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17771383A Pending JPS6068728A (en) | 1983-09-24 | 1983-09-24 | Digital-analog converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6068728A (en) |
-
1983
- 1983-09-24 JP JP17771383A patent/JPS6068728A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH011288A (en) | Temperature Compensated Integrated Circuit Hall Effect Device | |
US4618833A (en) | Operational amplifier offset trim that does not change the offset potential temperature drift | |
GB1592856A (en) | Semiconductor devices | |
GB2263831A (en) | Integrated circuit high frequency input attenuator circuit | |
DE2312085A1 (en) | LOGARITHMIC AMPLIFIER CIRCUIT | |
JPH07335828A (en) | Semiconductor device | |
JPS6068728A (en) | Digital-analog converter | |
US4358752A (en) | Analog-to-digital converter | |
JP3028420B2 (en) | Semiconductor integrated device | |
JPH0567083B2 (en) | ||
JPH0438602Y2 (en) | ||
JPH04290B2 (en) | ||
JPS58171843A (en) | Semiconductor integrated circuit device | |
JP3442092B2 (en) | Integrated circuit | |
JP2653046B2 (en) | Linear array | |
JPH0786949A (en) | Digital/analog converter | |
JPH0731303Y2 (en) | Voltage generation circuit | |
JPS6412103B2 (en) | ||
JP2994069B2 (en) | Electronic volume circuit | |
JPH0448308A (en) | Constant current source circuit | |
JP2823743B2 (en) | Semiconductor integrated device | |
JPH0330828B2 (en) | ||
JPS5487489A (en) | Integrated-resistance circuit for ad/da converter | |
JPH0573274B2 (en) | ||
SU1451833A1 (en) | Voltage-to-current converter |