JPS6068617A - Ion milling method for semiconductor device - Google Patents

Ion milling method for semiconductor device

Info

Publication number
JPS6068617A
JPS6068617A JP17743383A JP17743383A JPS6068617A JP S6068617 A JPS6068617 A JP S6068617A JP 17743383 A JP17743383 A JP 17743383A JP 17743383 A JP17743383 A JP 17743383A JP S6068617 A JPS6068617 A JP S6068617A
Authority
JP
Japan
Prior art keywords
substrate
ion milling
junction
filament
milling device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17743383A
Other languages
Japanese (ja)
Inventor
Tomio Nakamura
中村 登美雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17743383A priority Critical patent/JPS6068617A/en
Publication of JPS6068617A publication Critical patent/JPS6068617A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/2633Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to prevent generation of junction breakdown by a method wherein a substrate having a P-N junction of scribe line is electrically insulated from the substrate holder of an ion milling device. CONSTITUTION:An ion milling device has a filament 3 incide an anode 2 which is surrounded by a coil 1, and the ions sent from the filament 3 pass through a cathode 4 and a neutralized filament 5 and they are made to irradiate on the substrate 6 which is placed on a semiconductor substrate 7. In order to electrically insulate the semiconductor substrate 7 from the earth potential which is given to a substrate 6, a silicon oxide film 24 is formed on the back side of an N type substrate 16 whereon P-layers 17 and 19 and an N layer 18 are formed. As a result, no current runs on the substrate holder 6 of the ion milling device, thereby enabling to prevent generation of junction breakdown and to stabilize the yield of production remarkably.

Description

【発明の詳細な説明】 本発明は加速されたイオンにより半導体装置をエツチン
グするいわゆる。半導体装置のイオンミリング方法に−
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention involves etching a semiconductor device using accelerated ions. Ion milling method for semiconductor devices
It is something to do.

加速されたアルゴンイオメトク種々の物質全エツチング
する際物質表面上でイオンによる電荷蓄積が生じクーロ
ン反発力によりエツチング割カ合いが低下する。これを
防止するため、イオンミリング装置では熱フィラメント
がら熱電子全放出して、基板上で電気的に中和するよう
に考慮しである。
When accelerated argon ions are used to completely etch various materials, charge accumulation by ions occurs on the surface of the material, and the etching rate decreases due to Coulomb repulsion. To prevent this, the ion milling device is designed to emit all thermionic electrons from the hot filament and electrically neutralize them on the substrate.

しかし被エツチング物質の表面がP−型を示すP/N接
合を有する時、プラスイオンのアルゴンはP/N接合に
おいて順方向゛電流が流れる。このように電流はP/N
接合の電気的に流れやすい部分に集中的に流れる為接合
破壊が生じる0通常の半導体装置はスクライプ線がP/
N接合で形成されておタイオンミリング全行うと前述の
接合破壊がスクライプ線において発生し製造上大きな問
題となる。
However, when the surface of the material to be etched has a P/N junction exhibiting P-type, positive ion argon causes a forward current to flow in the P/N junction. In this way, the current is P/N
Junction breakdown occurs because the flow is concentrated in the electrically easy-to-flow parts of the junction.In normal semiconductor devices, the scribe line is P/
If the N-junction is formed and all tie ion milling is performed, the aforementioned junction breakdown will occur in the scribe line, causing a major manufacturing problem.

不発明の目的は、これらの接合破壊を改善するものであ
V安定にイオンミリングが実行する方法を提供すること
にある・ 接合破壊の原因は前述のようにP/N接合のある極部に
集中的にイオン電流が流れる為でめハこの電流の流れを
防ぐことに、l:り接合破壊を防止出来る。
The purpose of the invention is to improve these junction breakdowns and to provide a method for performing ion milling in a V-stable manner.As mentioned above, the cause of junction breakdown is at the extreme part of the P/N junction. Since the ionic current flows in a concentrated manner, by preventing this current flow, it is possible to prevent junction breakdown.

そこで本発明によれば#!−導体装置のスクライプ線の
P/N接合を有する基板t1イオンミリング装置の基板
ホルダーから電気的に絶縁すること全特徴とする半導体
装置のイオンミリング方法を得る・ 次に、図面?参照して不発明をより詳細に説明する・ 本発明の一実施例によれば、第1図に示すよう、イオン
ミリング装置はコイルlで囲まれたアノード2内にフィ
ラメント3上層しており、フィラメント3からのイオン
はカソード4お工び中性化フィラメント5全通して千尋
体基板7の載置された基板6に照射される。半導体基板
7は基板6に与えられている接地電位から電気的に絶縁
させるために、第2図に示すように、2層17. 19
,20およびN7輪18の形成されたN型基板16の裏
面にシリコン酸化膜24vf−形成しておく、尚21は
表面酸化膜、22.23は金属配線層である。このよう
IcN型基板16の裏面を酸化膜24でおおっておくこ
とにより、イオンミリング装置ン板ホルダー6に電流が
流れず、従って接合破壊は発生せず歩留が非常に安定す
る。イオノミリング終了後、牛導体基板表面全レジスト
膜で保1ウェトエッチ法でシリコン酸イト膜24′I!
−エツチング除去することで半導体装置の選択エツチン
グが完成する。
Therefore, according to the present invention, #! - To obtain an ion milling method for a semiconductor device, which is characterized in that the substrate t1 having a P/N junction of the scribe line of the conductor device is electrically insulated from the substrate holder of the ion milling device. Next, what about the drawings? The invention will be explained in more detail with reference to: According to an embodiment of the present invention, as shown in FIG. Ions from the filament 3 pass through the cathode 4 and the neutralized filament 5 and are irradiated onto the substrate 6 on which the chihiro body substrate 7 is placed. In order to electrically insulate the semiconductor substrate 7 from the ground potential applied to the substrate 6, as shown in FIG. 2, two layers 17. 19
, 20 and the N7 ring 18 are formed on the back surface of the N-type substrate 16, a silicon oxide film 24vf- is formed. Reference numeral 21 is a surface oxide film, and 22 and 23 are metal wiring layers. By covering the back surface of the IcN type substrate 16 with the oxide film 24 in this manner, no current flows through the plate holder 6 of the ion milling device, and therefore, no junction breakdown occurs and the yield is extremely stable. After the ionomiring is completed, the entire resist film on the surface of the conductor substrate is wet-etched to form a silicon oxide film 24'I!
- Selective etching of the semiconductor device is completed by etching removal.

このように不発明によるイオンミリングによれば、接合
破壊が起きないでイオンミリングによるエツチング?す
ることが出来る。
In this way, according to the uninvented ion milling, it is possible to perform etching by ion milling without causing junction breakdown. You can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はイオンミリング装置を闇単に示した図である。 第2凶は不発明の一実施例に用いられる半導体装置の断
面図である。 1・・・・・・コイル、2・・・・・・アノード、3・
・・・・・フイラメ/ト、4・・・・・・カソード、5
・・・・・・中1生化フィラメント、6・・・・・・基
板ホルダー、7・・・・・・半導体装置。 16・・・・・・へ型基板、17・・・・・・P層、1
8・・・・・N鳩、19.20・・・・・・P/N接合
スクライプ線、21゜24・・・・・・シリコン酸化膜
、22.23・・・・・・メタル層。
FIG. 1 is a schematic diagram of an ion milling device. The second example is a cross-sectional view of a semiconductor device used in an embodiment of the invention. 1... Coil, 2... Anode, 3.
...Film/G, 4...Cathode, 5
. . . Medium bioplastic filament, 6 . . . Substrate holder, 7 . . . Semiconductor device. 16...Hem-shaped substrate, 17...P layer, 1
8...N pigeon, 19.20...P/N junction scribe line, 21°24...silicon oxide film, 22.23...metal layer.

Claims (1)

【特許請求の範囲】[Claims] 加速されたイオンにより半導体装置金工、チングする方
法においてP/N接合’11する半導体装置を絶縁膜を
フ「シて接地を位に保持された基板上におき、加速され
たイオンでエツチングすることを特徴とするイオンミリ
ング方法。
In a method of metalworking and etching semiconductor devices using accelerated ions, a semiconductor device forming a P/N junction is placed on a substrate held at ground level with the insulating film removed, and then etched using accelerated ions. An ion milling method characterized by:
JP17743383A 1983-09-26 1983-09-26 Ion milling method for semiconductor device Pending JPS6068617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17743383A JPS6068617A (en) 1983-09-26 1983-09-26 Ion milling method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17743383A JPS6068617A (en) 1983-09-26 1983-09-26 Ion milling method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS6068617A true JPS6068617A (en) 1985-04-19

Family

ID=16030853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17743383A Pending JPS6068617A (en) 1983-09-26 1983-09-26 Ion milling method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS6068617A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104334A (en) * 1986-10-21 1988-05-09 Nec Corp Manufacture of semiconductor device
KR100706788B1 (en) 2005-11-17 2007-04-12 삼성전자주식회사 Filament member and ion source of an ion implantation apparatus having the filament member
KR100706799B1 (en) 2005-10-07 2007-04-12 삼성전자주식회사 Filament member and ion source of an ion implantation apparatus having the filament member

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104334A (en) * 1986-10-21 1988-05-09 Nec Corp Manufacture of semiconductor device
KR100706799B1 (en) 2005-10-07 2007-04-12 삼성전자주식회사 Filament member and ion source of an ion implantation apparatus having the filament member
KR100706788B1 (en) 2005-11-17 2007-04-12 삼성전자주식회사 Filament member and ion source of an ion implantation apparatus having the filament member

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