JPS6067556U - クロツク再生回路 - Google Patents

クロツク再生回路

Info

Publication number
JPS6067556U
JPS6067556U JP1983157935U JP15793583U JPS6067556U JP S6067556 U JPS6067556 U JP S6067556U JP 1983157935 U JP1983157935 U JP 1983157935U JP 15793583 U JP15793583 U JP 15793583U JP S6067556 U JPS6067556 U JP S6067556U
Authority
JP
Japan
Prior art keywords
phase difference
circuit
controlled oscillator
output
voltage controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983157935U
Other languages
English (en)
Other versions
JPH0510278Y2 (ja
Inventor
富沢　祀夫
青島　新治
Original Assignee
ヤマハ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ヤマハ株式会社 filed Critical ヤマハ株式会社
Priority to JP1983157935U priority Critical patent/JPS6067556U/ja
Priority to US06/658,263 priority patent/US4594703A/en
Publication of JPS6067556U publication Critical patent/JPS6067556U/ja
Application granted granted Critical
Publication of JPH0510278Y2 publication Critical patent/JPH0510278Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1461—8 to 14 modulation, e.g. the EFM code used on CDs or mini-discs

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図はこの考案の一実施例を示す回路図、第２図は第
１図の回路の動作波形図である。 Ｌ１〜Ｌ４・・・ラッチ回路、３・・・平滑回路、４・
・・バッファアンプ、５・・・可変容量ダイオード、６
・・・ＶＣＯ（電圧制御発振器）。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電圧制御発振器と、前記電圧制御発振器の出力に基づき
    クロックを生成する回路と、入力パルス信号を前記クロ
    ックでラッチする第１のラッチ回路と、前記第１のラッ
    チ回路の入出力間の位相差を検出する第１′位相差検出
    手段と、前記入力パルス信号を前記２０ツクのタイミン
    グで整合した信号を前記クロックでラッチする第２のラ
    ッチ回路と前記第２のラッチ回路の入出力間の位相差を
    検出する第２位相差検出手段と、前記第１位相差検出手
    段と第２位相差検出手段で検出される２つの位相差が所
    定の関係になるように、前記電圧制御発振器を制御する
    手段を具えたクロック再生回路。
JP1983157935U 1983-10-14 1983-10-14 クロツク再生回路 Granted JPS6067556U (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1983157935U JPS6067556U (ja) 1983-10-14 1983-10-14 クロツク再生回路
US06/658,263 US4594703A (en) 1983-10-14 1984-10-05 Clock-signal reproducing circuit including voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983157935U JPS6067556U (ja) 1983-10-14 1983-10-14 クロツク再生回路

Publications (2)

Publication Number Publication Date
JPS6067556U true JPS6067556U (ja) 1985-05-14
JPH0510278Y2 JPH0510278Y2 (ja) 1993-03-12

Family

ID=15660691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983157935U Granted JPS6067556U (ja) 1983-10-14 1983-10-14 クロツク再生回路

Country Status (2)

Country Link
US (1) US4594703A (ja)
JP (1) JPS6067556U (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62175969A (ja) * 1986-01-28 1987-08-01 Mitsubishi Electric Corp 記憶装置
US4949197A (en) * 1988-09-08 1990-08-14 Aspen Peripherals Corp. Dead track acquisition for phase-locked loop control
DE4343252A1 (de) * 1993-12-17 1995-06-22 Thomson Brandt Gmbh Schaltung zum Dekodieren von 2T-vorkodierten Binärsignalen

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57124260A (en) * 1980-12-12 1982-08-03 Philips Nv Phase detector
JPS5919456A (ja) * 1982-07-24 1984-01-31 Pioneer Electronic Corp クロツク再生回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671856A (en) * 1979-11-15 1981-06-15 Sony Corp Playback device of disc
GB2065395B (en) * 1979-11-29 1983-07-06 Sony Corp Frequency controlled signal generating circuit arrangements
NL8000124A (nl) * 1980-01-09 1981-08-03 Philips Nv Inrichting voor het weergeven van digitaal gecodeerde informatie die op een optisch uitleesbare schijfvormige registratiedrager is aangebracht.
US4404530A (en) * 1980-10-22 1983-09-13 Data General Corporation Phase locked loop with compensation for loop phase errors
JPS58220226A (ja) * 1982-06-15 1983-12-21 Toshiba Corp 位相ロツクル−プ制御回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57124260A (en) * 1980-12-12 1982-08-03 Philips Nv Phase detector
JPS5919456A (ja) * 1982-07-24 1984-01-31 Pioneer Electronic Corp クロツク再生回路

Also Published As

Publication number Publication date
US4594703A (en) 1986-06-10
JPH0510278Y2 (ja) 1993-03-12

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