JPS6066519A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To make a high-speed operation and a low power consumption possible by introducing an impedance element, which changes the impedance in accordance with a potential difference between both ends, to a transistor transistor logic (TTL) input circuit. CONSTITUTION:Field effect transistors T1 and T2 are used as impedance elements Z1 and Z2. In a conventional circuit, resistances R1 and R2 are used. The resistance between a gate G and a source S to the potential of a drain D is shown in a figure when the gate G and the source S are set to +5V; and for the purpose of equalizing the switching speed to that of the conventional circuit, the field effect transistor T1 is set to the same 20kOMEGA as the resistance R1 of the conventional circuit at the bias point, where the drain D is 3Vf=2.4V, so that a large quantity of base current of a transistor Q2 is supplied when transistors Q2 and Q3 start turning on. The field effect transistor T2 is set to the same 5kOMEGA as the resistance R2 of the conventional circuit with the base of a transistor Q4 where the potential of a terminal OUT is a threshold voltage 1.5V of the TTL. That is, the transistor T1 is set to 5kOMEGA with D=3.1V. At this time, current consumption Icc is 0.11mA for IN=0.4V and is 0.39mA for IN=2.4V, and thus, the power consumption is reduced to a half of that of the conventional circuit.

Description

[Detailed description of the invention] The present invention is transistor transistor logic.

(hereinafter referred to as TTL) input circuit.

Conventionally, TTL is widely used in various electronic devices. 1st
The figure shows an example of a conventionally used TTL circuit. This circuit uses a small number of elements and can operate at high speed.
) during operation! It is characterized by a large degree of leeway for 11 tones. The operation of the circuit will be briefly explained.

A voltage of 0V is applied to GND, and a voltage of 5V is applied to Vca.

If a voltage higher than the TTL threshold voltage of approximately 1.5 V is applied to the input terminal IN, Q, Q, and Q will rise to 0NLOUT. W level occurs.

At this time, the base potential of Q, , Q, is approximately equal to the base potential of Q3, so OI''Ii' is applied.Next, T is applied to IN.
TL signal glue. When the W level, that is, approximately 0.4V, is applied, the base potential of Q becomes approximately equal to the potential of IN9.
Then, Q,,Q, is turned off. As a result, the potential of the collector of Q, that is, the base potential of Q4 becomes equal to Vca, so a high level occurs at 0LIT. Normally, Q1 is called a phase inversion transistor because an opposite phase signal of IN is generated at the collector.

By the way, in the conventional circuit shown in Fig. 1, the TTL with R8, 几, is
It is an important resistance that determines the speed and power consumption of the circuit. In recent '1' TL circuits aimed at high speed and low power, '+
Ω at -20, 1%, Ω at =5.

R8=5 is selected to be about Ω. Now, the current consumption is calculated assuming that the voltage (Vf) between the base and emitter of the transistor is 0.8 . When IN is applied with L (Iy level 0.4v), Q, , Q are turned OFF, so the current consumption is only the current flowing through the circuit 1.

I,c=(Vcc-Vf-0,4V)/20
KΩ=(5V-0,8V-0,4V)/20 Ω=0
．． 19mA (1) When high level 2.4V is applied to IN, Qt
Since lQ3 turns on, I ce-(Vcc-3V f )/R, +(VC,
C-V f )/Rz=(5V-3X0.8V)/20
1 (Q + (5V - 0,8V) 15Ω ” = 0.13mA + 0.84mA = 0.97mA (2
). Here, 1 shown in equation (1) is isometrically the input terminal of this TTL circuit.
Since the fan-in of the circuit is determined, it is desired that it be as small as possible. Furthermore, since equation (2) determines the power consumption of this TTL circuit, it is desirable that it be as small as possible. However, increasing R, , R, causes a speed delay due to the parasitic capacitance of Q, , Q.

An object of the present invention is to provide a circuit that can eliminate the drawbacks of the conventional circuit, maintain high speed performance, and reduce power consumption.

That is, in the present invention, in an input circuit in which a human input signal is applied to the N side of a PN junction, and the P side is connected to the first power source via an impedance element, the impedance of the impedance element is determined by the potential difference between both ends of the impedance element. Characterized by change.

Such a semiconductor logic circuit can eliminate such drawbacks of conventional circuits.

FIG. 2 is a conceptual diagram of the present invention. RI in Figure 1.

R3 is impedance element 2. ．． 2. It has been changed to

FIG. 3 shows a specific embodiment of the present invention. Field effect transistors T, , T, are used for ZI+2. The operation of this circuit will be explained below.

First, T, , and T are field effect transistors whose current path is a P region formed in an N-type semiconductor.

When the gate G and the lease S are set to +5■, the resistance between S and D with respect to the potential of the drain D is as shown in FIG. Here, in FIG. 3, in order to make the switching speed the same as that of the conventional circuit, l',,T, must be selected as follows.

First, T, must supply a large amount of base current of Q, through T1 at the time when Q, , Q, starts to turn on.

Therefore, T is the first at the bias point where D is 3 f-2, 4
It is sufficient to set Ω to 20, which is the same as R in the figure.

T! UOIJTcD potential is TTLCDM value t! Pressure 1.5
At the base of Q4 such as VK, connect Ω to 5, which is the same as R in Figure 2.
You can set it to . That is, D = 3. You can set it to 5Ω with IV. Then, the same current consumption calculation as in equations (1) and (2) is performed using T3. Calculation taking into consideration the bias dependence of the conduction resistance of T2 results in the following.

When I N = 0.4 V: Ice = (5V-o, sV, -o, 4V)/20 to ΩX
α - (5V-o, 5v-0, 4V) / 20 [ΩX (5/3) = 0.1 1mA (3
Also, α is the increase in resistance when υD increases from 2.4■ to 1.2■ as shown in Fig. 5.

When IN=2.4V: ICC-(VCC-3Vf), /20 is Ω×β+ (V
cc-V f )/s KΩ×α=(5V-0,8V
X3)/20 to Ω×1+(5V-o, sV)/sKΩ×X(6,5/2) =0.13mA+0.26mA=0.39mA(・1) Gari. In the case of W, from equations (1) and (3), o, ], t
mAlo, 19 mA = 0.58, if IN power is High, 0.39mA from equations (2) and (3)
70.97mA=0.4. In other words, it is possible to reduce power consumption by almost half and maintain the same speed.

FIG. 4 shows another embodiment of the invention. Torede T,,T
, controls the gate voltage to improve speed and reduce power consumption.

It's IN. W paste T1. From the above calculation, the gate potential of T is G(T,)=5V and G(T!)=1, respectively.
．． If it becomes 2 V and IN is High, G
(T1)=o,sV,G(T,)=2.4V,! near'
, Cru. As a result, when IN is L6y, the conduction resistance of T1 can be made larger and the conduction resistance of T2 can be made smaller. Similarly, when IN is High, the conduction resistance of T1 can be made small and the conduction resistance of T2 can be made large, so that extremely high-speed operation is possible.

As described above, according to the present invention, it has been found that high speed and low power consumption can be achieved by introducing an impedance element whose impedance changes depending on the potential difference between both ends into a TTL circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example of a TTI circuit. FIG. 2 is a diagram showing the concept of the present invention. FIG. 3 is a diagram showing a specific embodiment of the present invention. FIG. 4 shows another embodiment of the invention. FIG. 5 is a diagram showing the characteristics of a field effect transistor.
transistor. ＃ l Figure 17 House l Mu 2 concave 3rd room 4 concave

Claims (3)

[Claims] (1) In an input circuit in which a human input signal is applied to one end of a PN junction, and the other end of the PN junction is connected to a first power source via an impedance element, the impedance of the impedance element is A semiconductor logic circuit characterized in that it changes with a potential difference. (2) The semiconductor logic circuit according to claim (1), wherein the impedance element is a field effect transistor. (3) The gate potential of the field effect transistor changes in accordance with a human input signal.
The semiconductor logic circuit according to item 2).