JPS63246916A - Inverter circuit - Google Patents

Abstract

PURPOSE:To retard optionally the rise of an output signal of an inverter circuit and the speed of rise by connecting a variable capacitance addition circuit whose capacitance is changed externally to an output terminal. CONSTITUTION:In applying as voltage of VTHN (threshold voltage of an N channel MOS transistor(TR) 3)+VCC to a pad 6, since a voltage at a node N3 and a node N5 is at a VCC level, the TR 3 is always in the on-state, then the load capacitor of a capacitance C1 is added to the node N3. In applying the voltage of VTHN+(VCC/2) to the pad 6, since only the voltage is applied up to the VCC/2 to the node N4, the charge stored in the capacitor 4 is halved in the state of giving a voltage of VTHN+VCC to the node N4 from the relation of Q=CV. Thus, the load capacitance added to the node N3 is C/2 and an inverter output characteristic as shown in dotted lines is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an inverter circuit provided on a semiconductor integrated circuit, and more particularly to an inverter circuit that can arbitrarily delay the waveform change of an output signal with respect to a human input signal. It is.

[Conventional technology]

FIG. 5 is a circuit diagram showing a conventional inverter circuit configured with a CMOS circuit using both an N-channel MOS transistor and a P-channel MOS transistor. In the figure, 1 is an N-channel MOS transistor whose drain is connected to node N2, gate is connected to node N1, and source is connected to ground terminal E1, and 2 is an N-channel MOS transistor whose drain is connected to node N2 and gate is connected to node Nl. A P-channel MOS transistor whose source is connected to a power supply terminal T1 that supplies voltage VCC, T2 is an input terminal, and T2 is an input terminal.
3 is an output terminal, and these transistors 1 and 2 and terminals TI, T2 . T3 constitutes an inverter circuit 10.

Next, the operation will be explained. FIG. 6(a), (bl is a signal waveform diagram showing the output characteristics of a conventional inverter circuit, FIG. 6(a) is a waveform of a signal on input terminal T2,
Figure (b) shows the waveform of the signal on the output terminal T3.

When the input terminal T2 is at the rHJ level, the transistor 1 is on and the transistor 2 is off, so the output terminal T3 is at the rLJ level. When input terminal T2 is at rLJ level, transistor 1 is off and transistor 2 is off.
is in the on state, so the output terminal T3 becomes "H" level.

When the voltage at the input terminal T2 changes from the rHJ level to the ``J level'', the voltage at the output terminal T3 changes from the ``L'' level to the rHJ level, but the speed of the change mainly depends on the load capacitance of the output terminal T3. It is determined by the characteristics of transistor 2. If the load capacitance is small for transistor 2 which has a certain conductance, the output level will be rL.
The speed of change from J level to rHJ level is fast;
Conversely, if it is large, the output level will change from rLJ level to rHJ level.
The speed at which levels change will be slower.

Similarly, the voltage at input terminal T2 changes from rLJ level to rHJ level.
When the voltage at the output terminal T3 changes from the rHJ level to the rLJ level, the speed of the change is mainly determined by the load capacitance of the output terminal T3 and the characteristics of the transistor l.

When the load capacitance is small for transistor 1 having a certain conductance, the output level changes quickly from the "H" level to the rLJ level, and conversely, when it is large, the output level changes from the rHJ level to the rLJ level. Speed will be slower.

[Problem that the invention seeks to solve]

In a conventional inverter circuit, the rising and falling speeds of the output signal for one input signal are as follows:
Since it is uniquely determined by the load capacitance of the output terminal and the conductance of the transistors 1 and 2, there is a problem in that once the inverter circuit is formed, it is not possible to slow down the rise or fall speed of the output signal.

The present invention has been made in view of these points, and its purpose is to provide an inverter circuit that can arbitrarily delay the rise and fall speeds of an output signal.

[Means for solving problems]

In order to achieve such an object, the inverter circuit according to the present invention makes it possible to control the load on the output terminal from the outside by adding a circuit that can change the capacitance value from the outside to the output terminal of a normal inverter circuit. It is configured so that

[Effect]

In the inverter circuit according to the present invention, the rising and falling speeds of the output signal can be arbitrarily controlled.

〔Example〕

An embodiment of the inverter circuit according to the present invention will be described with reference to an 0M03 circuit using both an N-channel MOS transistor and a P-channel MOS transistor. FIG. 1 shows the CMOS circuit.

In the figure, an inverter circuit 10 has a first N-channel MOS transistor 1 and a P-channel MOS transistor 2. N-channel MOS transistor 1 has a drain connected to output terminal T3 via node N2,
the gate is connected to the input terminal T2 via the node N1,
A source is connected to ground terminal E1. In addition, transistor 2 (between P channels O3) has its drain connected to node N2.
is connected to the output terminal T3 through the gate, and the gate is connected to the node N1.
is connected to input terminal T2 through
It is connected to a power supply terminal T1 that supplies power.

20 is a variable capacitance addition circuit. This variable capacitance addition circuit 20 is composed of a second N-channel MOS transistor 3, a capacitor 4, a resistor 5, and an external voltage application pad 6. N-channel MOS transistor 3 has a drain connected to output terminal T3 via node N3,
The gate is connected to node N4, and the source is connected to node N5. Capacitor 4 has a capacitance value C1, one end is connected to node N5, and the other end is connected to ground terminal E2. The resistor 5 has a resistance value R1, one end is connected to the node N4, and the other end is connected to the ground terminal E3. External voltage application pad 6 is connected to node N4.

Next, the operation will be explained. The resistance value R1 is set to be large so that an external voltage can be easily applied. Figure 2 shows
The output characteristics of the inverter circuit 1a are shown when the voltage applied to the pad 6 is changed. FIG. 2(a) shows the signal waveform on the input terminal T2, and FIG. 2(b) shows the signal waveform on the output terminal T3. First, when no voltage is applied to the puff drawer,
Since the node N4 is connected to the ground terminal E3 through the resistor 5, the potential on the node N4 becomes the ground level. At this time, transistor 3 is in the off state, so no extra capacitance is added to node N3, and its output characteristics are as shown by the solid line in FIG. becomes the same as

Next, when a voltage of VTHN (threshold voltage of N-channel MOS transistor 3) + Vcc is applied to pad 6, transistor 3 is always on regardless of whether the voltages at node N3 and node N5 are at VCC level or at ground level. A load capacitance with a capacitance value C1 is added to the node N3.

As a result, the rising and falling speeds of the output signal of the inverter circuit 10 are delayed, resulting in the inverter output characteristics as shown by the dashed line in FIG. 2(b).

Furthermore, when a voltage of ■A□+(Vcc/2) is applied to the pad 6, even if the potential of the node N3 is VCC, the voltage is only applied to the node N4 up to Vcc/2, so that the voltage is stored in the capacitor 4. Since Q=CV, the amount of charge becomes half of the state in which a voltage of VTHN+■Cc is applied to node N4. As a result, the value of the load capacitance added to the node N3 becomes substantially C1/2, resulting in an inverter output characteristic as shown by the dotted line in FIG. 2(b).

FIG. 3 is a circuit diagram showing a second embodiment of the present invention, in which the inverter circuit 10 is the same as that of the first embodiment,
30 is a variable capacitance addition circuit.

The variable capacitance addition circuit 30 is composed of a second P-channel MOS transistor 3as, a capacitor 4a'b, a resistor 5a, and an external voltage application pad 6a. The P-channel transistor 3a has a drain connected to the output terminal T3 via the node N3, a gate connected to the node N6, and a source connected to the node N7. The capacitor 4a having a capacitance value C2 has a voltage ■ at one end. , and the other end is connected to a node N7. One end of the resistor 5a having a resistance value R2 is connected to the power supply terminal T5 that supplies the voltage VCC, and the other end is connected to the node N6. External voltage application pad 6a is connected to node N6.

The operation of the circuit shown in FIG. 3 is similar to the operation of the first embodiment shown in FIGS. 1 and 2, and the waveform of the signal a on the input terminal T2 is shown in FIG. The waveform of the signal on the output terminal T3 is shown in FIG. 4(b). It is assumed that the resistance value R2 of the resistor 5a in FIG. 3 has a sufficiently large value. First, pad 6
When no voltage is applied to a, the node N6 is connected to the resistor 5a.
Since it is connected to the power supply terminal T5 through the node N
The potential on 6 becomes VCC. Since the transistor 3a is in the off state at this time, no extra capacitance is added to the node N3, and its output characteristics are as shown by the solid line in FIG. be the same as the characteristics.

Next, -I Vtop l (VTMP
is the dark value voltage of P-channel MOS transistor 3a), transistor 3a is always on whether the voltages at nodes N3 and N7 are VCC level or ground level, so node N3 has a capacitance value C2. This will add a load capacity of . As a result, the rising and falling speeds of the output signal of the inverter circuit 10 are delayed, resulting in the inverter output characteristics as shown by the dashed line in FIG. 4(b).

Also, (Vcc/2) l VT to pad 6a
When the voltage MP l is applied, even if node N3 falls to the ground level, the voltage at node N7 remains VCC/
2, the amount of charge stored in the capacitor 4a is -1Vy+<pl at node N6 from Q=CV.
It becomes half of the state when the voltage is applied. As a result, the load capacity added to node N3 becomes substantially C2/2,
The inverter output characteristics are as shown by the dotted line in FIG. 4(b).

In addition, in the above embodiment, the operation of a single CMOS inverter circuit was explained, but as an actual usage example, for example, a delay inverter circuit where the optimum point is not clear, or a case where the rising and falling speed of the output signal waveform is important. There is an example in which the inverter circuit according to the present invention is used in the output stage of a meaningful internal clock. In this case as well, the delay and output signal waveform can be changed arbitrarily as in the case of the above embodiment, which is very effective for evaluating device margins and current consumption.

〔Effect of the invention〕

As explained above, in the present invention, by connecting a variable capacitance addition circuit that can change the capacitance value externally to the output terminal, it is possible to arbitrarily delay the rise and rise speed of the output signal of the inverter circuit. This has the advantage that very useful data can be easily obtained for delay optimization or various evaluations in devices.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of an inverter circuit according to the present invention, Fig. 2 is a signal waveform diagram for explaining its operation, and Fig. 3 is a circuit diagram showing a second embodiment of the invention. , 4th
The figure is a signal waveform diagram for explaining its operation, FIG. 5 is a circuit diagram showing a conventional inverter circuit, and FIG. 6 is a signal waveform diagram for explaining its operation. 1.3...N channel MOS transistor, 2...
P-channel MOS transistor, 4... capacitor,
5...Resistor, 6...Pad, T1...Power terminal,
T2...Input terminal, T3...Output terminal, Nl-
N5...Node, E1-E3...Ground terminal,
10... Inverter circuit, 20... Variable capacitance addition circuit.

Claims (3)

[Claims] (1) An inverter circuit provided on a semiconductor integrated circuit, characterized in that a variable capacitance addition circuit capable of externally changing the capacitance value is connected to an output terminal. (2) The inverter circuit consists of a P-channel MOS transistor whose source is connected to a power supply terminal, whose drain is connected to an output terminal, and whose gate is connected to an input terminal, and a P-channel MOS transistor whose source is connected to a ground terminal, whose drain is connected to an output terminal, and whose gate is has a first N-channel MOS transistor connected to the input terminal, and the variable capacitance addition circuit has a second N-channel MOS transistor and a first N-channel MOS transistor connected to the input terminal.
the second N-channel MOS transistor has a source connected to the other end of a capacitor which has one end connected to the ground terminal, and one end connected to the ground terminal. Claim 1, characterized in that a gate is connected to the other end of the resistor connected to the resistor, and a drain is connected to the output terminal.
Inverter circuit described in section. (3) The inverter circuit consists of a first P-channel MOS transistor whose source is connected to a power supply terminal, whose drain is connected to an output terminal, and whose gate is connected to an input terminal; and a first P-channel MOS transistor whose source is connected to a ground terminal and whose drain is connected to an output terminal. The variable capacitance addition circuit includes a second P-channel MOS transistor and an N-channel MOS transistor whose gate is connected to the input terminal.
an external voltage application pad connected to the gate of the S transistor; the second P-channel MOS transistor has a source connected to the other end of a capacitor which has one end connected to the power supply terminal; and one end connected to the power supply terminal. 2. The inverter circuit according to claim 1, wherein a gate is connected to the other end of the resistor connected to the resistor, and a drain is connected to the output terminal.