JPS6066389A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the number of constant current sources and to reduce power consumption by using write constant current sources also for a control circuit in a static type semiconductor storage device using bipolar transistors (TRs). CONSTITUTION:The emitters of TRs Q1, Q2 of a control circuit connected to a write amplifier WA are connected to the collectors of TRs Q3, Q4 of which emitters are connected to write constant current sources IW1, IW2 and the constant current sources IW1, IW2 are also used for the control circuit. Therefore, constant current sources to be exclusively used for the control circuits are unnecessary, so that the number of constant current sources can be reduced and the power consumption can be also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a static semiconductor memory device using bipolar transistors, a special example thereof, and a write control section thereof.

Prior Art and Problems FIG. 1 shows a static semiconductor memory device using a conventional bipolar transistor.

In FIG. 1, Schottky clamp type memory cells Cjj (i=O+ 1+"・+n-1+j=
o, 1. ..., m-1) are shown. Each memory cell has two Schottky barrier diodes 5BD
1,5BD2. Consists of two load resistors R+, R2, and two multi-emitter transistors. Multi-emitter transistor element QO1,
The emitter of QO2 is connected to a bit line such as Bo', Bq
The elements QH1 and Qu2 are connected to a hold line, for example, HO. Since the transistor elements Qoi, QO2, QEl, and QEl2 are clamped by the Shida-Sotky barrier diodes 5BDI and 5BD2, these transistor elements operate in a non-saturated operating region. P! For example, when selecting memory cell C00, 14. The potential of word iWo is set to level 7, and bit line selection transistors QBO and QBO' to which bit lines Bo and Bo are connected are selected by setting the column selection signal YO to level .

Connect ■ to the constant/regional flow sources IR1, R2, Iwl, and IW2. In addition, the fixed-1C style AV only 1. ID2 is for read operation and is set to lIn and In2 and IR. Also,
Constant current source Iw1. ', [W2 fl: iW is for write/operation, and IW is set to IW2=■W. As mentioned above, during a read operation, a current IR flows through the bit lines Bo and Bo, and during a write operation, a current IFI flows through one bit line depending on the write data, but a current IFI flows through the other bit lines. Current IR+Iw flows.

A detection transistor QDO is provided on each bit line Bo, Bo.

Qno' are connected, their collectors are connected to a sense amplifier SA for read operation, and their base potentials are controlled by a detection transistor control circuit C1. In other words, during write operation, the transistor QDO
, QDO' is set to the 7-high level, and the base potential of the other is set to the low level. As a result, transistors Qo1 . The on/off state of QO2 is rewritten.

Also, during read operation, transistors QDO, QDO
The first base positions of ' are both set to intermediate level. As a result,
Transistors Qσ1 and QO2 of selected memory cell Coo
on/off status), i.e., stored data ``1++''.

0'', a difference occurs between %a ID and ID, and this difference is detected by the sense amplifier SA and output as data Dout.

Note that the detection transistor control circuit C1 is a transistor Q.
+ ', Q2, constant current source 11. i2.

Well, if the light is constant, the current source control circuit C2 is the transistor Q.
51 Q4, in this case the valley transistors Q5. Q4 is a constant current source]:w1. For IW2, transistors QBO+QBO' constitute a current switch. As a result, during the read operation, the magnetic current of the constant current source Jv+, IW2 flows through the transistor Q'tQ4.
During write operation, the constant current sources IW1. The current of one of the constant current sources IW2, for example Iwl, flows through the transistor Q3, and the current of the other constant current source Iw2 is controlled so as to flow through the transistor QBO', that is, the bit line BO: I'1. Ru.

The above-mentioned control + ali times ici and C2 are both light amplifier W
AK is controlled, in detail, the circuit WA of the light amplifier WA
-1, controlled by WA-2. In addition, the circuit WA-
1 (WA-2,) is a transistor Q21゜Q22 that constitutes a current switch for the resistor R1-4 and the constant current source 3 (VR is the reference comparison voltage), as shown in Fig. 2 (5). , Q23 and Q24 constitute a current switch for the constant current source 4.

Q25, and therefore generates a signal at the potential shown in FIG. 2 (D) in response to the write enable signal ~VE and input data D, D.

However, in the first control circuit C1,
Constant current sources I+ and I2 are required for the fall of the base position of the detection transistors QDO and QDO', resulting in a problem of increased power consumption.

Purpose of the Invention The purpose of the present invention is to solve the problems of the conventional type described above.
Constant current source I+ of control circuit C1 in FIG.

The role of I2 is the write constant current source Iw1. By having IW2 serve as the current source, the number of constant current sources can be reduced, and power consumption can therefore be reduced.

According to the present invention, there are provided a plurality of word lines, a plurality of pit line pairs, a statitough memory cell provided at each intersection of the bit line pair and the word line,
a pair of detection transistors whose emitters are connected to each of the bit line pairs; a pair of write constant current sources connected to each of the focus line pairs via bit line selection transistors; ．． Second. Third
and a write amplifier that generates a fourth signal, the collector of which is connected to the power supply, the emitter of which is connected to the base of each of the detection transistor pairs, and whose base potential is set to each of the first...and fourth signals. The first signal is controlled by the second signal. a third transistor, the collector of which is connected to the emitter of each of the first and second transistors, the emitter of which is connected to each of the write current sources, and the base potential of which is controlled by each of the third and fourth signals; ．． Fourth
transistors, and collectors of the respective first .幀2
A semiconductor memory device is provided, the semiconductor memory device having a fifth transistor connected to the emitter of the transistor, the emitter of which is connected to the current source of each of the transistors, and whose base potential is controlled by the write enable signal. .

Examples of the invention Hereinafter, the present invention will be explained in detail with reference to Figure #J6.

FIG. 3 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. In Figure 5, ? The constant DC sources I+ and I2 in Figure 41 are not provided, and the transistor Q5
．． The collector of Q4 is connected to the emitters of transistors Q1 and Q2, respectively. In other words, the control circuits C1 and C2 in FIG. 1 are configured as one circuit. Further, transistors Qs, Q6 which are directly controlled by the write enable signal are transistors Q3 . Each is connected in parallel to Q4.

Next, the operation of the circuit shown in FIG. 5 will be explained.

If the transistor Q5. Q6 turns on. At this time, the two outputs of circuit WA-1 are at the same intermediate level, and the two outputs of circuit WA-2 are at the same high level, so the write constant current sources IW1 and IW2
The current flows through the circuits of transistors Ql, (C) and the circuits of transistors Q2 and Q4, respectively.As a result, the forward potential drop (V
l) become equal, and base potentials equal to 1 are given to the injection transistors QDO and QIIO'. Note that the base potential at this time is the resistance of the circuit\VA-1 (WA-2).
fL1. (FLs) (21A(5)) ・'r')
1ffff i□ is adjusted by 2. In this way, during the read operation, the constant current sources 1w1. Since IW2 is connected to the emitter of the transistor Qi, (',!,2) via the transistors Q5 and Q4 in the on state, the constant current source Iw1.IW2 becomes the constant current source h,
It will be playing the role of I'2.

During write operation, VVE is at low level (WJ'J>'YO), so transistors Q5 and Q6
are both turned off, but the other transistors Q1 to Q4
The on/off state differs depending on the input data Din.

For example, Dln is high level, D is high level, Dlfi is low level -? l'1lJf,) transistor Q1. Q3 is on, transistor Q2*Q'
is in the off state. Therefore, transistor Q1. Q3
The current of the write constant current source Iw1 flows through the circuit configured by the above, but the current of the write constant current source IW2 does not flow through either of the transistors Q4 and Q6. However, the current from the write constant current source W2 flows through the bit line JO via the transistor QBO'.

Also, at this time, since the transistors Q4 + Q6i are in the on state, the transistor Q2 is connected to the transistor Q2.
Only the current flow at the pace of BO' flows through the transistor Q.
1 flows into Iw+. In this way, even during the write operation, the constant current source IW2 plays the role of the constant current source IW2 in FIG.

Similarly, during a write operation, when D is at a low level and the line is at a high level, the constant current source Iw1 functions as the constant current source 1 in FIG.

As described in detail, according to the present invention, a constant 'dL flow source Jw
1. IW2 is shown in Fig. 1, 'I is the constant current source h in the conventional type, and the role of I2 can no longer be ignored. Therefore,
The number of constant current sources can be reduced, which is useful for lowering power consumption.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional semiconductor memory device, Fig. 2 is a circuit diagram of circuits WA-1 and WA-2 in Fig. 1, and Fig. 2 (c) is a circuit diagram of a conventional semiconductor memory device.
are output waveform diagrams of circuits WA-1 and WA-2, Figure 3.
FIG. 5 is a diagram #5 showing an embodiment of the semiconductor memory device according to the present invention. WO: Word line BO, BO: Bit line C00: Memory cell QDO, 'QDa': Detection transistor QBO, Qn
o': Bit line selection transistor WA Niwrite amplifiers Q1 to Q6: First to sixth transistors Iw1. IW
2 Nirite constant current source 1) in: Input data signal WE Nirite enable signal.

Claims (1)

[Claims] 1. A plurality of word lines % A plurality of pit line pairs, a static memory cell provided at each intersection of the bit line pair and the word line, a detection transistor pair whose emitter is connected to each of the bit line pairs, and each of the above A pair of write constant current sources are connected to the pit line pair via bit line selection transistors, and the first
．． 2. A write amplifier that generates the third and fourth signals, the collector of which is connected to the power supply and the emitter connected to the base of each of the detection transistor pairs;
．． The collectors of the first and second transistors are controlled by the second signal. ? 42 transistors, the emitters are connected to the respective current sources, and the base potentials are connected to the respective sixth .42 transistors. The third signal is controlled by the fourth signal. a fourth transistor, and a fifth transistor whose collector is connected to the emitter of each of the first and second transistors, whose emitter is connected to each of the write constant current sources, and whose base potential is controlled by the write enable signal. A semiconductor memory device comprising six transistors.