JPS6066388A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the number of constant current sources and to reduce power consumption by constituting a write amplifier of a static type semiconductor storage using bipolar transistors (TRs) in diode logics. CONSTITUTION:The write amplifier is constituted of AND circuits AND-1, AND- 2 consisting od diodes D1, D3 and highly conductive diodes D2, D4 and wired OR circuits OR-1, OR-2, etc. processing a data signal D, a signal D' and an inversion write enable signal WE'. The diodes D2, D4 are turned on at the high level reading of the signal WE' and only the diode D3 is turned on at the writing. The output voltage of the write amplifier is set up to a prescribed value in accordance with the level of the signal D and signal D'. Since many emitter followers requiring respective constant current sources are not used, the number of constant current sources of the write amplifier is reduced and the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is directed to the improvement of a static type semiconductor memory device d1 using a pie breaker-latrannostar, particularly its write amplifier circuit.

[Technology background]

S'BD type, PNPN using bipolar transformer
In state type, I2L type, etc., type semiconductor memory devices, a memory cell is provided at each intersection of a plurality of word lines and a plurality of bit line pairs, and the bit line pairs are selected by a bit line selection transonuter. connected to a constant current source.

It should be noted that the constant current source for the read mode and the write mode are provided, and the connection of the constant current source for the write mode to the bit line pair is controlled by the write amplifier for the write mode. In addition, a detection transistor is connected to each bit line, and a sense amplifier for read mode is connected to this detection transistor.
The control of this detection transistor is also performed by the write amplifier 0.

The write amplifier is used both when controlling the detection transistor and when controlling the constant current source for write mode, as shown in Figure 1 (
1 (as shown, it is necessary to generate two output signals of three levels: ■ゎ, ■).

Conventional Lye I amplifiers are constructed using a large number of emitter followers, and therefore require a large number of constant current sources, which is disadvantageous in terms of power consumption.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems in the conventional type.
By configuring the write amplifier using diode logic, it is possible to reduce the number of constant current sources and reduce power consumption.

[Structure of the invention]

To achieve the above object, the present invention generates three-level output signals in response to a data signal, an inverted data signal of the data signal, a write enable signal, and an inverted write enable signal of the write enable signal. In Sudame's light amplifier circuit, the first one whose collector is connected to the power supply. 2nd transosbe corresponding customer 1st. The first . connected to the emitter of the second transistor. a second constant current source 1; a first OR circuit that generates a first OR logic signal between the inverted write enable signal and the data signal;
a second OR circuit that generates an OR logic signal; a first diode AND circuit that generates a first AND logic signal of the write enable signal and the first OR logic signal;
and a second diode AND circuit for generating a second AND logic signal of the write enable signal and the second OR logic signal, the container 1. (by the second AND logic signal) the first. A semiconductor memory device characterized in that the pace of a second transistor is driven is provided.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a semiconductor memory device using a general bipolar transistor. In FIG. 1, this is a representative of seven Yotsugi-Klang memory cells arranged in n rows and m columns. oo
is shown. The memory cell Coo is composed of two Schottky barrier diodes 5BDI, a white BD2, two load resistors R1a and R2, and two multi-emitter transistors. The emitter of QC11GC2 is the bit line B, for example. , connected to the lice, element QH1'Q
H2 is connected to a hold line, for example H8. Transistor element Qc1. Qc2. QH4, Q□2 are Schottky barrier diodes SBD, , SBD,
These transistor elements will operate in their non-saturated operating region.

For example, when selecting memory cell C80, word line W. The potential of bit line B is set to high level. ;Bit line selection trunk star Q Bo+ Q to which the tag is connected
B. ', column selection signal Y. Select bit line B by setting the bit line B to high level. , constant current source IB1+I
Connect to B2+Iw1+Iw2. In addition, the constant current source 'R
11RR2 is for read operation, I,,==IR2
=I. Further, the constant current sources 1, 4, and 1w2 are for write operation, and it is assumed that (i)=Iw2=Iw. As will be described later, during a read operation, the bit line B. A current IR flows through each of the bit lines, and during a write operation, a current IR flows through one bit line depending on the write data, while a current IR flows through the other bit lines. + I, flows.

Each bit line B. , Bo is a detection transistor Q.

0 QDol are connected, their collectors are connected to sense amplifier 7'SA for read operation, and these six base potentials are controlled by write amplifier WA. During write operation, transistor QDO9D. ′ is set to a high level, and the base potential of the other is set to a low level. As a result, the transistor QDO'QDol and the selected memory cell forming the current switch, for example, the transistor Q within C8°.
C+, l 1. The on/off state of QC2 is rewritten. Also, during read operation, transistor QDO' Q
Both base potentials of DO are set to intermediate level VC. As a result, the transistor QC11QC of the selected memory cell Coo
2 on/off state, i.e. stored data “1”, “0”
According to electrician. , q, this difference is detected by the sense amplifier SA and becomes the data D. It is output as llt. In addition, each transistor Q31Q4 is a constant current source W1
1IW2 constitutes a current switch with transistors QB□+QBO'. As a result, during the read operation, constant current source Iw1. (2) The current of W2 is controlled to flow through transistors Q3 and Q4, respectively, and during write operation, the current of constant current source 'W1. IW
2, for example, a current of 1w1 flows through the transistor Q3, and the current of the other constant current source w2 is controlled so as to flow through the transistors QBo'tf, cb, and the lower bit line 7.

It should be noted that although the output levels of the circuits WA-1 and WA-2 of the write-an 7'WA shown in FIG. 1 are different, their circuit configurations are the same.

Next, write amplifier WA+7) circuit WA-1, WA-2
(WA-1 as a representative) will be explained.

FIG. 3 is a circuit diagram showing a conventional circuit WA-1. Third
In the figure, transistors Q21 and Q227 constitute a current switch for constant current source IsK, and transistors Q23, Q24, and Q25 constitute constant current source I4.
A current switch is configured for. To briefly explain the circuit operation, in the read operation (d.

Since WE) is VR, and WE) is D, D, the currents of constant current sources ra and I4 are respectively connected to the circuit of resistor R3 + transistor Q2□, resistor R5, and transistor Q230.
flows into the circuit. As a result, VD=VD=VCo-13R3 However, I3-ei, R3==R5. During a write operation, WE<V□, therefore, the current of constant current source 3 flows through transistor Q21, and if the data signal is 10>D, the current of constant current source I4 flows through resistor R.
3, R4, and flows through the circuit of transistor Q24.

Therefore, VD=Vcc (Rs+R4)I4 Vn ""cc. Conversely, if D)D, then v = v D CC V D = Voo - (R5 + Ra ) I 4 = Vcc (
R3+R4) I 4 However, R4-=R6. Well, three levels will be formed as shown in Figure 1.

However, in the circuit of FIG. 3, a large number of emitter followers are used, and therefore a constant current #I3 is used.

Since I4 is required, there is a problem that the dissipation power becomes large.

FIG. 4 is a circuit diagram showing an embodiment of the write amplifier according to the present invention. In Figure 4, diode AND circuit A
ND-1 and AND-2 are provided, and the constant current source 3+I4 shown in FIG. 3 is not provided. Each of the 9 diodes I'1li, 21 paths D-1°AND-2 has the same circuit configuration, and in this case,
The conductivities of D, , D3 are set smaller than those of the diodes D2 and D4. Furthermore, the OR circuits 0R-1 and 0R-2 that constitute the wired OR logic are f
- It is provided to output an OR logic signal of the write signal D and the inverted write enable signal WE.

Next, the operation of the circuit shown in FIG. 4 will be explained. During a read operation, WE is at a high level. Therefore, diode D! +D3 is cut off and diode D2*D
4 is turned on. Therefore, each diode D2+D4
If the current flowing in is IR, then VD=VD=VCC-R
7rR(Ry==RB).

Also, during a write operation, the eave is at a low level, so that the diode D2. D4 cuts off. Then, if D) is D, the diode "D!" is also cut off, and only the diode D4 is turned on. Therefore, if the current flowing through the diode D4 is IW, then V = V D CC VD = vcc RgI.

=Vcc-R7I.

becomes. Conversely, if D ) I), then V, == V
co-R7IW V =V D RiC . Here, as mentioned above, the diode D1.

Since the conductivity of D3 is set at +17, which is smaller than the conductivity of diodes D2 and D4, I, , )I, is obtained. Therefore, in this case as well, the first replay filter of the VDVD
The relationship is shown in the figure.

〔Effect of the invention〕

As explained above, according to the present invention, the number of constant current sources is reduced, which is useful for reducing power consumption.

[Brief explanation of drawings]

Figure 1 is a waveform diagram showing write amplifier output characteristics, Figure 2 is a circuit diagram showing a semiconductor memory device using a general bipolar trannostar, Figure 3 is a circuit diagram showing a conventional write amplifier, and Figure 4 is a circuit diagram showing a conventional write amplifier. The figure is a circuit diagram showing an embodiment of a write amplifier according to the present invention. Misaki...data signal, 1...inverted data signal, WE...
・Write enable signal, WE-...Inverted write enable signal, 0R-1, 0R-2...OR circuit, AND
-1, AND -2...AND circuit, Ql, Q2
...Transistor, 11112... Constant current source. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi

Claims (1)

[Claims] 1. In a write amplifier circuit for generating three-level output signals in response to a data signal, an inverted data signal of the data signal, a write enable signal, and an inverted write enable signal of the write enable signal, the collector is connected to the power supply. The 6th 2nd.
fc is connected to the emitter of the second transistor. a second constant current source; a first OR circuit that generates a first OR logic signal between the inverted write enable signal and the data signal; a second OR circuit between the inverted write enable signal and the inverted data signal; a second OR circuit that generates a logic signal; a diode AND circuit that generates a first AND logic signal of the write enable signal and the first OR logic signal; and the write enable signal No. 4i. and the second OR logic signal;
゜Second AND logic signal fltj record 1. A conductor storage device characterized in that the pace of the second transistor is driven.