JPS586236B2 - Programmable read-only memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable read-only memory circuit, and particularly to a programmable read-only memory (hereinafter referred to as P-R) whose constituent units are a transistor and a Zener diode.
OM) circuit.

Conventionally, this type of P-ROM has a diode matrix structure in which the constituent units are two diodes 10 and 20 connected in series in opposite directions, as shown in FIG. Writing is performed by short-circuiting and destroying one of the two diodes. For example, by applying a voltage to the row line 30 and column line 40 for writing, one of the diodes 10 or 20 is reverse biased. Do this by shorting.

Furthermore, a drive transistor is required to drive the next stage.

In such a structure, the input voltage for reading written information is required to be at a level sufficient to simultaneously conduct the forward-connected diode and the base-emitter junction of the drive transistor. It is very difficult to operate under low voltage power sources.

An object of the present invention is to provide a P-ROM circuit that can operate with a low power supply and has a small number of constituent elements.

The P-ROM circuit of the present invention is constructed using transistors and Zener diodes, which constitute a transistor matrix, and solves the above-mentioned drawbacks of the conventional P-ROM. In ROM, it is possible to operate satisfactorily even at a power supply voltage so low that it cannot operate.

FIG. 2 shows one memory unit (
A circuit example of a unit memory cell) is shown.

The details of the present invention will be explained below with reference to FIG.

The base terminal of transistor 1 is connected to Zener diode 2.
The collector terminal of the transistor 1 is connected to the output terminal 6 and further connected to the power supply terminal 5 via a load resistor 4.

Further, the emitter terminal of the transistor 1 is grounded via a resistor 7.

Program writing is performed by selectively passing a write current of an appropriate magnitude from the input terminal 3 to the output terminal 6 according to the content of the program, and selectively short-circuiting and destroying the Zener diode 2.

At this time, all other terminals are left open.

The write current also flows through the collector-base junction of the transistor 1, but in this junction it is in the forward direction, so the write current generates little power and does not destroy the junction.

The resistor 7 functions to prevent the write current from leaking to unnecessary parts.

Now, consider a case where an appropriate power supply voltage is applied to the power supply terminal 5 and another voltage is applied to the input terminal 3.

At this time, assuming that there is no writing to the Zener diode due to the information content, the voltage V3 of the input terminal 3 is equal to the breakdown voltage Vz of the Zener diode 2 and the forward voltage VBE between the base and emitter of the transistor 10.
Transistor 1 does not conduct and terminal 6 remains at a high level unless the sum of .

Next, depending on the content of the information, writing to the Zener diode is performed, and therefore the Zener diode 2
is short-circuited, and in this case, when the voltage v3 at input terminal 3 exceeds the base-emitter forward voltage VBE of transistor 10, transistor 1 becomes conductive, and therefore terminal 6 becomes low. level.

In other words, if a voltage slightly exceeding the base-emitter forward voltage VBE of the transistor 10 is applied to the input terminal 3, a low level will be obtained from the output terminal 6 if the Zener diode 2 is selectively short-circuited and destroyed. ,
A high level is obtained from the output terminal 6 when there is no short-circuit breakdown.

This means that necessary output information is stored by selectively short-circuiting and destroying the Zener diode 2.

When the transistor is conductive, transistor 1 can draw enough current from output terminal 6 to drive the next stage due to its current amplification effect, and no other drive transistor is required. .

As is clear from the above, in the present invention, the power supply voltage required for reading information may be at a level slightly exceeding the forward voltage VBE between the pace emitters, and this is possible even at the low power supply voltage as described above. It is also at a level that works well.

Figure 3 shows two P-ROM structural units horizontally as described above.
This shows an example of the configuration of a P-ROM circuit with a 2x2 bit transistor matrix arranged in two rows and two vertically. By selectively shorting and destroying four Zener diodes according to the information, 2-bit input, 2-bit output P-
A ROM is obtained.

It is also obvious that the number of rows and columns can be increased or decreased as necessary.

[Brief explanation of drawings]

Figure 1 shows a conventional diode matrix P-ROM circuit.
FIG. 2 shows a circuit according to an embodiment of the invention, and FIG. 3 shows a transistor matrix embodiment according to the invention. In the figure, 1 is a transistor, 2 is a Zener diode, 3 is an input terminal, 4 is a load resistor, 5 is a power supply terminal, 6 is an output terminal, and 7 is a write current leakage prevention resistor.

Claims (1)

[Claims] 1 A transistor whose emitter terminal is grounded directly or through a first resistor, a Zener diode whose one terminal is connected to the base terminal of the transistor, and a Zener diode whose one end is connected to the collector terminal of the transistor. Second
a resistor, a predetermined voltage is applied to the other terminal of the second resistor, and the other terminal of the Zener diode is connected to an input terminal;
A programmable read-only memory circuit characterized in that a circuit whose output terminal is the collector terminal of the transistor is used as a unit memory cell.