JPS6065615A - Burst signal generator - Google Patents

Abstract

PURPOSE:To set optionally a phase value of an end period and to allow a burst analog signal accurately at the phase value of the end period by constituting the generator with a wave number detecting means, an end phase detecting means and a signal generating and stopping means. CONSTITUTION:The wave number detecting means 2 counts the number of generated waves and generates a wave number end signal when the generated wave number reaches a preset wave number. The end period phase detecting means 3 counts a clock signal at the generation of the wave number end signal. When this count value reaches the preset end period data, the stop signal is generated. The signal generation stop means 4 closes a gate circuit 4 by using the stop signal so as to stop a clock signal applied to other circuit by using a clock signal 42. Thus, the burst signal generator sets optionally the end period phase value and allows the burst analog signal to be ended accurately at the set end period phase value.

Description

[Detailed Description of the Invention] This invention provides a digitally synthesized burst signal that can generate and terminate a signal by setting an arbitrary burst width (determined by the number of generated waves and frequency) and an arbitrary final phase value. Regarding the generator.

For example, when measuring the time response of an automatic control system, you may want to arbitrarily change the final phase of a burst signal to see how the time response changes, or you may wish to measure by arbitrarily changing the burst width using a signal with a constant final phase value. There are cases etc. Furthermore, when two burst signals are generated, it may be desired to end the burst signals with a constant phase difference.

<Prior art> A conventional burst signal generator, as shown in Fig.
F control was used to generate a burst signal. Alternatively, a signal with a constant frequency was modulated with a rectangular wave. However, although the burst width can be controlled to some extent in any of the burst signal generators, it is difficult to terminate the signal at an arbitrary final phase value. Moreover, even if it was terminated, the final phase value was an inaccurate value.

<Object of the Invention> An object of the present invention is to provide a burst signal generator that can arbitrarily set a final phase value and accurately terminate a burst analog signal at the set final phase value. .

Another object of the present invention is to provide an apparatus in which the number of generated analog signal waveforms can be set below the decimal point and the burst width can be controlled with the precision of a clock signal.

<Summary of the Invention> The present invention is a burst signal generating device of so-called phase cumulative function generating means, which counts the number of generated waves and sends out a wave number end signal 1 when the number of generated waves set from the outside is reached. From the time of the signal, the clock signal is advanced to a final phase value set externally in advance, and when the set final phase value is reached, generation of the analog signal is stopped.

The phase accumulation type signal generating means is the one written in the waveform memory in 1. The obtained amplitude value (amplitude data) is read out using the phase data of the signal waveform (given as address data), and is sent to a digital-to-analog converter (hereinafter referred to as a DA converter) to convert it into an analog signal wave. It generates an analog signal through a filter, and in order to read out the amplitude data corresponding to the phase data in the waveform memory, the current phase data and frequency data are cumulatively added, and the waveform is read out as the phase data to read out the next amplitude data. 10 to generate an analog signal.

Therefore, in this invention, the wave number data from the burst width setter and the final phase from the final phase value setter are set in advance so that the analog signal ends at an arbitrary burst width (determined by wave number and frequency) and at an arbitrary phase. After the data is supplied to the burst signal generator and the set constant wave number is generated, the analog signal is stopped at the set phase value. The wave number setter and the final phase value setter may be provided in the tB alone, or the data may be sent to the control device or other CPU.
You can take it as is.

<Embodiment of the Invention> FIG. 2 shows an embodiment of the invention. In Figure 2, 1
2 is a phase cumulative function generation means, 2 is a wave number detection means,
3 is a 411J1 phase detection means, and 4 is a signal generation stop F means.

The phase accumulation type function generating means 1 is composed of a frequency setter 11, a phase accumulation adder S2 2, a latch circuit 13 and 5, a waveform memory 14, a DA converter 16, and a low-pass filter 17. The adder 12 adds the current phase data and the frequency data from the frequency setter 11 to create new phase data. The launch circuit 13 operates based on a clock signal and latches phase data. The waveform memory 14 sends out amplitude data using the phase data from the launch circuit 13 as an address. After the amplitude data is once input to the latch circuit 15, it is converted into an analog signal by the DA converter 15, and the analog signal wave is passed through the low-pass filter 17 and sent out from the output terminal.

The wave number detection means 2 is composed of a counter (counter) 21. For example, in the case of the fully separable down counter 21, the set wave number from the burst width setter 22 is preset, and the wave number end signal is generated when it is decreased by 1 by the carry signal of the adder 12 and becomes zero. . In addition, in the case of the newly settable up counter 21, the complement of the set wave number is freshened, and the carry signal of the adder 12 is used to make it 1.
When a carry signal of the up counter 21 is generated, this can be used as a wave number end signal. or,
It is also possible to count the carry signal of the adder 12 from 1 using a normal counter 21, compare the counted value with a set wave number using a digital comparator, and generate a wave number end signal when they match. Further, here, the carry signal of the adder 12 is counted as the number of waves generated by the burst signal generator, but the output waveform may be directly counted.

The final phase detection means 3 is composed of a counter (counter) 31. In this case as well, a fully sestable down counter 31 may be used, a fully sestable up counter 31 may be used, or a combination of the counter 31 and a decile comparator may be used. For example, in the case of a pre-centered down counter 31, the final phase setter 32
The end phase data from the wave number end signal is preset, and when the number is reduced to zero by the clock signal from when the wave number end signal is generated, a stop signal is generated. To count the clock signals from the time when the wave number end signal is generated, for example, it is preferable to open a gate circuit with the waveform end signal and apply the clock signal to the counter 31.

The means 4 for stopping signal generation is constituted by a gate circuit.

That is, the clock signal supplied from the clock signal source 42 to the phase cumulative function generating means 1, the final phase detecting means 3, and other circuits.
The gate circuit is closed by the stop signal so that the turn signal is +L. It is practically convenient to add a function to this gate circuit, in addition to the stop signal, to provide a signal for temporarily stopping or a signal for continuous generation.

<Operation of the Invention> In the two series of embodiments, the adder 12 performs 14-bit addition, and the storage capacity of the waveform memory 14 is 16°38.
4 words and zuro. The waveform storage 111 stores amplitude values obtained by decomposing one period of 360 degrees of the signal wave into 16,384 points. Therefore, phase data Oo and ooo contain amplitude data with a phase value of zero, and phase data (10,001
has amplitude data with a phase value of 1 minute 19 seconds, and a phase value of 0
0,046 stores amplitude data with a phase value of 1 degree 39 seconds, and phase data 04,097 stores amplitude data with a phase value of 90 degrees 1 minute 18 seconds.

This note 1. When the σ content is read out repeatedly at a clock frequency of 16,384 Hz, amplitude data every 1 minute and 19 seconds is read out with one clock, and an analog signal wave with a frequency of 1) 1z is sent out from a burst signal generator. When read with a clock frequency of 1,638.4 KHz repetition frequency, an analog signal wave with a frequency of 10011 z is sent out.

Now, the frequency data of 1゜OHZ is input to the frequency setter 11.
is set and driven at a clock frequency of 16,384 Hz to operate the burst signal generator. Initially, the device stops generating signals at the stop signal.

First, a start pulse is applied to the start signal terminal 51, the 7-node terminal of the W adder 12, and the load terminals of the counters 21 and 31, the memory of the adder 12 is cleared, and the memory of the adder 12 is cleared. Set wave number data and final phase data are set in 21 and 31, respectively. At the same time, release the signal to pause (and the device starts working.

The adder 12 first sends phase data oo, ooo,
Next, 100 is added to the current phase data and sent to the latch circuit I3 as the next phase data of 00.100. i
tt, waveform record 1. The key unit 14 sends out 1 line width data every 2 degrees 11 minutes 50 seconds, and the burst signal generator sends 100H data.
Send out an analog signal wave of z. Also, the frequency setter 11
When 50KHz is set as the frequency data, R17
22 frequency to 1.63L41 (Hz, 4 degrees 23
Amplitude data every minute and 40 seconds is read from the waveform memory 14. Although the clock frequency converter is not shown, it can be easily constructed using a frequency divider and a gate circuit.

Since the adder S7 has 12i dimensions and handles 14 inputs, the sum of additions is 16,384. When the value exceeds , a carry signal is sent.

That is, since a carry signal is generated every time the phase of the generated signal exceeds 360 degrees, the wave number can be counted by counting the carry signals.

The wave number detection means 2 counts the number of generated waves and generates a wave number end signal when a preset wave number is reached.

As described above, in the case of the pre-centered down counter 21, the set wave number is preset, and when the number is decreased by the carry signal of the counter 12 and becomes zero, a wave number end signal is generated.

The end phase detection means 3 counts the clock signals from the time when the wave number end signal is generated. When the counted value reaches preset final phase data, a stop signal is generated. As described above, in the case of the pre-centered down counter 31, the set final phase data is pre-set and the clock signal from when the wave number end signal is generated is decremented, and when the count reaches zero, a stop signal is generated.

This stop signal is given to the signal generation stop means 4.

The signal generation stop means 4 starts the gate circuit Ijl by the stop signal.
! 4 is closed, and the clock signal supplied from the clock signal source 42 to other circuits is stopped. Therefore, the burst signal generator temporarily stops generating signals.

After a certain period of time, by applying a start pulse to the start signal terminal 51, the adder 12 is reset, the counter 21 presets the set wave number, the setter 31 presets the set end +U1 phase data, and outputs the signal again. Depart J2.

In this way, the device of the invention generates a burst signal.

<Another Embodiment of the Invention> FIG. 3 shows another embodiment of the invention. The difference from the embodiment shown in FIG. 2 is that the waveform detection means 2 and the final phase detection means 3 operate simultaneously in parallel, and the logical sum of their respective outputs is taken by the OR circuit 11 & 55, so that all output points are When it reaches zero, a stop signal is generated. However, in this case as well, the operation of the final phase detection means 3 is such that only the last digit of the adder 12 corresponding to the wave number end signal - the set final phase data loaded with the whisker signal acts on the wave number end signal. It is the same as stepping by the clock signal from the time of signal generation.
Depends on.

This means that the phase data given to the waveform memory 14 is
This is because the new phase data is obtained by adding the current phase data Y and frequency data X in step 2, and the phase data is influenced by the value of the frequency data X. That is, (X-1)・180/2″ degrees=(X-1)・180/16384 degrees---<
1), which is (X-1) times the phase step stored in the waveform storage 14. Therefore, the final phase value will advance by the phase amount shown in equation (1) at most.

<Other Embodiments of the Invention> FIG. 4 shows another embodiment in which the error caused by the frequency data X described above is halved. Furthermore, in Figure 4, the applicant was born in 1930.
The initial phase setting circuit I9, which is an invention of a "signal generator" filed on September 9, 1988, is also added.

In the embodiment shown in FIG. 4, when the carry signal from the adder 12 is output,
The (X-1-Y) data value C is latched by the launch circuit 61, and the frequency data value In order to correct the difference, the digital comparator 63 compares the magnitude of the value of this (X→-Y) data with the value of
'>X/2, a correction signal is generated and the gate circuit 63
to one of the inputs. The other input of the gate circuit 64 is connected to a down counter 3 constituting the terminal phase detection means 3.
Gives a minimum bit signal of 1. Therefore, when (X0Y)>X/2, the stop signal is issued when the down counter is 0, and when (X-1-Y)<X/2, the stop signal is issued when the down counter is 1. Make it 4. By doing this, the error in the final phase is:
2) You can take a bite that is halved, and 121 degrees is doubled.

Incidentally, FIG. 4 is also an example in which the initial phase value can also be controlled. That is, a data selector J8 is provided between the adder 12 and the latch circuit 13, and an initial phase setting circuit 9 is provided at one input.
The initial phase data A is input to the adder 12 to the other input.
The phase data B of each frame is inputted. Then, the selection signal initially selects the initial phase data A, and then sequentially selects the phase data B. The accuracy of the initial phase value is independent of the frequency data X and depends only on the phase step of the waveform memory 14.

In this way, the burst signal generator of FIG. 4 can arbitrarily set the initial phase value, burst width, and final phase value of the burst analog signal and generate it.

In addition, the above figures 2, 3 and f/! Although each of the embodiments shown in FIG. 4 has been described as being constructed using individual circuits, it is easy to consider that it can be constructed using a microcomputer (hereinafter referred to as .mu.cpu).

In this case, the functions of the wave number detection means 2, final phase detection means 3, and signal generation stop means 4 are executed by the functions of the μCPU.
I can do it.

<Advantages of the Invention> As described above, the burst signal generator of the present invention can arbitrarily set and generate the final phase of the burst signal, which was not possible in the past. Furthermore, the burst width can also be set and generated with the accuracy of the clock signal. Moreover, in the embodiment shown in FIG. 4, the initial phase value can also be arbitrarily set and generated, so that the initial phase value, burst width, and final phase value can be controlled.

Furthermore, during the pause 11J1 of the burst signal, although not shown, the control circuit receives the stop signal from the final phase detection means 3, counts the clock signals, and after a certain period of time, outputs a start pulse to the start signal terminal 51. By giving , the pause period can be arbitrarily determined.

iiC, the burst signal generator of the present invention is used as a signal source when measuring the time response of an automatic control system, for example.
Alternatively, it will be very effective if used as a signal source for new precision measurements in the future.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional burst signal generator, FIG. 2 is a block diagram for explaining one embodiment of the present invention, FIG. 3 is a block diagram of another embodiment, and FIG. The figure is a block diagram of another embodiment. l Two-phase accumulation type function generation means, 2: Wave number detection means, 3: Final phase detection means, 4: Signal generation stop means, 11: Frequency setter, 12: Phase accumulation adder, 13: Launch circuit, 14: Waveform memory, 15
: Launch circuit, 16: D-A converter, 17: Low-pass filter, 18: Data selector, 19; Initial phase setter, 21: Counter, 22: Burst width setter, 31
: Counter, 32: Final phase setter, 41: Gate circuit, 42: Clock signal source, 51 NIST signal terminal,
55: OR circuit, 61: Launch circuit, 62; Divider, 63: Comparator, 64: Gate circuit, Patent applicant Takeda Riken Kogyo Co., Ltd. No. 11'2 + No. 21''I No. 31η Procedural amendment (voluntary) ) October 14, 1980 1 Indication of the case Japanese Patent Application 1982-1737552 Title of the invention Burst signal generator 3 Person making the amendment Relationship to the case Patent applicant 5 Contents of the amendment (1) In the specification, page 12 Line 18 1 'Signal generator' filed on September 9, 1982 [Patent application 1982-165768 r signal generator filed on September 8, 1981]'
I am corrected. (2) "Minimum bit signal" in lines 3 and 9 on page 13 of the same book is corrected to "least significant bit signal."that's all

Claims (1)

[Claims] (1) Phase data is given to a waveform memory to read amplitude data, the phase data and frequency data are added together and the result is sequentially given to the waveform memory as new phase data, and the amplitude data is read from the waveform memory. A. In a burst signal generator that generates an analog signal through a digital-to-analog converter, the number of waves generated by the burst signal generator is multiplied by 11, and when the number of generated waves reaches a preset wave number, a wave number end signal is generated. A wave number detection means; B. A final phase detection means that advances according to a clock signal from the time when the wave number end signal is generated by the wave number detection means and generates a stop signal when the set final phase data is reached; C, J- A signal generation stop stage for stopping the signal generation of the burst signal generator in response to a stop signal from the final phase detection means, and stopping the analog signal waveform at the set generation wave number and the set final phase value. A burst signal generator characterized by: