JPS6065611A - Delay line - Google Patents

Abstract

PURPOSE:To obtain a tapped delay line by decreasing the number of quantities of amplifiers, capacitors and switches and connecting in cascade delay circuits advantageous for circuit integration. CONSTITUTION:The switches S11, S12 perform input/output control of the capacitor C11. After the capacitor C11 samplies an output voltage sampled and held at the pre-stage at a prescribed period by using the switches S11, S12, the capacitor C11 is connected to an input terminal of the amplifier A13. The switches S13, S14 perform the input/output control of the capacitor S12 and the switches S15, S16 perform the input/output control of the capacitor C13 respectively. The capacitors C12 and C13 are connected alternately between an input/ output terminal and ground of the amplifier A13 by the switches S13, S14 and the S15, S16 and this operation is conducted in synchronizing with the transfer period of the C11. The delay circuits like the above are connected in cascade for two stages. Thus, the number of quantities of the amplifiers and capacitors is decreased respectively as the delay circuit to obtain a delay time and also the tapped delay line is constituted.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal delay line, and particularly to a tapped delay line suitable for the configuration of a transversal filter that facilitates integration into an integrated circuit (IC). be.

[Background of the invention]

FIG. 1 is a circuit diagram showing a conventional delay line.

In Figure 1, Sat, So2.5oz, S
o4.5osSO6 are switches, Co+,
(1'02, Cos, and Co4 are capacitors, AH, A, and 2 are amplifiers, A is a signal input terminal, and B and C are output terminals.

FIG. 2 is a switching time chart of each switch in FIG. 1 and a waveform diagram showing signal waveforms at input terminal A and output terminals B and C.

In Figure 2, (a) is the switch 5o+, Sos
, Sos switching state, (A) is switch 5o2. Switching state of So4゜SO6, (C)
is a voltage waveform applied to input terminal A, (d) is a voltage waveform appearing at output terminal B, and (e) is a voltage waveform appearing at output terminal C.

The operation of this conventional example will be explained below.

Switch 5o+, 5o3. Sos is shown in Figure 2 (α)
, switch So2. Sb2.5oa performs a switching operation as shown in FIG. 2(A), and the switching period is T. Now switch Sot, Sos,
Sos is in conductive state (0, N), switch So2.
Sb2. Assume that Sb2 is in a non-conducting state (OFF). In this state, the delayed output voltage of the previous stage is applied to the input terminal A, and the delayed output voltage information is stored in the capacitor co+.

Further, in the capacitor CO2, the voltage information stored in the capacitor CO2 is reset. Further, the capacitor Cos is connected to the inverting input terminal of the amplifier A I 2, and an output voltage is applied across the capacitor Co4, and the output voltage information is stored in the capacitor Coa. Next, Sui,
Nochi So+, Sos, Sos are in non-conducting state, switch 5o2. -5oa, Sb2 becomes conductive. The capacitor CO1, which has stored the output voltage information of the previous stage, is connected to the inverting input terminal of the amplifier A11.
An output voltage is applied across +2, and the output voltage information is stored in the capacitor CO2, and the capacitor Cos stores voltage information proportional to the voltage information that is maintained at the output terminal of the amplifier AH and stored in the capacitor CO2. , the voltage information stored in capacitor Co4 is set.Next, the switches Sot, Sos, So
s is conductive, the switch is ``;C2,S(+4,
Sb2 becomes non-conductive and the same operation is repeated.

As described above, in the conventional method, in order to design a delay circuit that obtains a delay time equal to the switching period T, two amplifiers are required as shown in FIG. 1, and a large number of capacitors are also required accordingly. In addition, Fig. 2(d), (
As shown in d), the output waveform becomes a comb waveform, so a hold circuit is required, and the I
It was disadvantageous for C conversion.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology. 1. The purpose of the present invention is to reduce the number of amplifier capacitors and switches compared to the prior art, and to provide a tapped amplifier with delay circuits connected in cascade, which is advantageous for IC implementation. The purpose is to provide a signal delay line.

[Summary of the invention]

In order to achieve the above object, the present invention provides one aspect of the present invention.

a plurality of first capacitors that are controlled to be sequentially connected between the output terminal and the inverting input terminal of the amplifier and between the ground;
a switch circuit for controlling the connection of the capacitors; a third capacitor or capacitors for accumulating the signal from the signal input terminal and transferring the accumulated signal to the inverting input terminal of the amplifier; A delay line is constructed using a delay circuit including a switch circuit that controls storage and transfer operations in synchronization with connection control of the first capacitor.

[Embodiments of the invention]

An embodiment of the present invention will be explained below.

FIG. 5 is a circuit diagram showing an embodiment of the present invention. 6th
In the figure, A13 is an amplifier, S11°, S+2. S
15* S1a + S'5+ S and 6 are switch and switch respectively.

C11, C42, and C13 are capacitors, D is an input terminal, and E and F are output terminals.

FIG. 4 is a time chart showing the operating state of each switch shown in FIG. 6, and a waveform diagram showing the signal board shape of each terminal. In FIG. 4, (a) shows switch S4. (b) is the operating state of switch Se2, (C) is the operating state of switches S, R, and S+6, (d) is the operating state of switch S
14, the operating state of S15, (C) shows the voltage waveform applied to the input terminal, (A) shows the voltage waveform appearing at the output terminal E, and ω) shows the voltage waveform appearing at the output terminal F. T is switch S11. The operation cycle of S12 is shown, and φ1. φ2
*f'3. φ4 is the switch S++, S12. (S,
sS+a'), (Su, S+s) indicates the phase in which it becomes conductive.

This embodiment is a delay line having tapped terminals in which two stages of delay circuits are cascaded.

First, the operation of each element will be briefly explained.

In FIG. 3, switch S11. S12 performs input/output control of the canister C11. The canister C11 samples the sample-and-held output voltage of the previous stage at regular intervals by the switches S++ and S12, and then is connected to the input terminal of the amplifier A1t. Switch S'5.514 controls input/output of capacitor CI2;
Switches S15 and S16 perform input/output control of the canopy CSS. Capacitor CI2 and capacitor c
ps is switch S,s +'S+4 and switch S,5
9, S, and 6 are alternately connected between the input and output terminals of the amplifier A1B and the ground, and this operation is performed by the canoccictor C.
This is done in synchronization with the 1+ transfer cycle.

The overall operation will now be explained in detail. Initially, in phase φ in FIG. 4, the capacitor C+ samples the sampled and held delayed output voltage of the previous stage via the switch SN.

The output of this chopper amplifier A13 is a voltage corresponding to the charge of the capacitor C12 when the phase is φ3, or a voltage corresponding to the charge of the capacitor C12 when the phase is φ4.
At this time, a voltage corresponding to the charge of the capacitor C13 is output. On the other hand, in the case of one phase φ3, both ends of the capacitor cu are grounded by the switch S16, and the charges in the capacitors C and 3 are discharged. Similarly, the edge of phase φ4 is capacitor CI.
Both ends of the capacitor Cj2 are grounded by the switch S14, and ill of the capacitor Cj2 is discharged.

Next, in phase φ2, capacitor C11 is connected to switch S
+2 to the input terminal of the amplifier, 'f13. At this time, the output of amplifier A1B is 1 phase 91. The capacitor c12 is connected to the amplifier AI by the switch S1s K.
A voltage corresponding to the charge of the capacitor CH connected between the input and output terminals of the amplifier A and 3 is connected between the input and output terminals of the amplifier A and 3 by the switch S14, or when the phase is φ4, the capacitor cps is connected between the input and output terminals of the amplifier A and 3, and the voltage corresponding to the charge of the capacitor CH is On the other hand, when the phase is 1114, both ends of the capacitor C13 are grounded by the switch S16 to discharge the charge of the capacitor C13.Similarly, when the phase is 1114, the capacitor C12 is grounded at both ends by the switch S14. The charge in the capacitor C12 is then discharged.

Next, the phase becomes φ1 again, and the above operation is repeated. Note that the delayed output voltage in one stage of the delay circuit can be obtained as a voltage delayed by the switching period T. Also, since the amplifier AI 3 operates as an inverting amplifier, FIG. 4(e).

As shown in (A) and (!I), with respect to the input voltage applied to the input terminal, the output terminal E receives a voltage of the opposite polarity delayed by a time T, and the output terminal F receives a voltage of the same polarity delayed by a time 2T. appear.

According to this embodiment, the number of amplifiers and canisters can be reduced as delay circuits to obtain the same delay time. Further, it is possible to construct a delay line with a curved line in which the delay time per stage of delay circuit is equal to the sampling period T and the output waveform is a hold waveform.

Next, other embodiments of the present invention will be described.

FIG. 5 is a circuit diagram showing another embodiment of the present invention. Fifth
In the figure, 511o, S, and 2° are switches, respectively.
G is an input terminal, and H and I are output terminals. 6th
The figure is a time chart showing the operating state of each switch shown in FIG. 5, and a waveform chart showing the signal waveform of each terminal. In FIG. 6, (σ) is switch SI+. operating condition,
(b) shows the operating state of the switch 512o, and (C) shows the operating state of the switch 512o. Operating state of S16, (d) is switch 5
141 Operation status of S15.

(g) shows the voltage waveform applied to the input terminal G, (7"l shows the voltage waveform appearing at the output terminal H, and c9) shows the voltage waveform appearing at the output terminal I, respectively.

This embodiment is a delay line having two tap output terminals in which two stages of delay circuits are connected in series.The delay time per stage of delay circuit is sampling period T, and the output voltage has the same polarity as the input voltage and is held. Outputs the voltage waveform.

The operation of this embodiment is almost the same as that shown in FIG. 5, and the input/output of the capacitor C11 is controlled by switches 511o + 512o K, and after sampling the signal voltage from the previous stage,
The input and output terminals of the capacitor C1+ are inverted and the amplifier A1H
By inputting Ic, Fig. 6(e), (fi,
As shown in (9), with respect to the input voltage applied to the input terminal G, the output terminal H receives a voltage of the same polarity delayed by a time T, and the attractive terminal I receives a voltage of the same polarity delayed by a time 2T. appear.

According to this embodiment, in order to obtain the same delay time, the number of amplifiers and capacitors in the delay circuit can be reduced.
The delay time per delay circuit stage is the sampling period T, and the output voltage is the same polarity as the input voltage.
The output waveform can constitute a tapped delay line that becomes a hold waveform.

FIG. 7 is a circuit diagram showing another embodiment of the present invention. In FIG. 7, J is an input terminal, and K is an input terminal.

L is an output terminal. FIG. 8 is a time chart of each switch shown in FIG. 7 and a waveform diagram showing signal waveforms of each terminal. In FIG. 8, (a) is switch S1
+, 511o (7) Operating status, (b) Itt
Operating states of switches S+2 and 5j20, (C) operating states of switches S and 3°S+6, (d) switch S1
41 Operating state of Srs, (e) is the voltage waveform applied to the input terminal I, (a) is the voltage waveform appearing at the output terminal K,
(!l) indicates the voltage waveform appearing at the output terminal LK.

The operation of this embodiment can be easily understood from the operation of FIG. 5 and the circuit shown in FIG.

Therefore, as shown in FIG. 8(e), ω, 0), the delay time per delay circuit stage is the sampling period T, and the voltage applied to the input terminal J at the output terminal of the first stage delay circuit is On the other hand, the output terminal of the second stage delay circuit outputs a voltage with a reverse polarity and a time delay of T, and a voltage with a reverse polarity and a time delay of 2T with respect to the voltage applied to the input terminal J.

According to this embodiment, in order to obtain the same delay time, the number of amplifiers and capacitors in the delay circuit can be reduced.
In addition, the delay time per stage of the delay circuit is equal to the sampling period TK, and the tapped delay circuit outputs a voltage showing the same polarity or the opposite polarity to the Kugata voltage for each delay time T, and the output waveform is a bold waveform. lines can be constructed.

FIG. 9 is a circuit diagram showing another embodiment of the present invention. In FIG. 9, S2+, S22+ S23. S
24 are switches, C21 and C22 are capacitors, M is an input terminal, and N and O are output terminals. FIG. 10 is a time chart showing the operating state of each switch shown in FIG. 9 and a waveform diagram showing signal waveforms at each terminal. In FIG. 10, (α) is the operating state of switch 821, (b) is the operating state of switch S22, and (C) is the operating state of switch S22.
is the operating state of the switch 52B, and (d) is the operating state of the switch S24.
The operating state shown in (e) is switch S, S*516
The operating state of switch SuS, 5) is the operating state of switch SuS, 5 -(
! 1) shows the voltage waveform applied to the input terminal Af, (h) shows the voltage waveform appearing at the output terminal N, and (t) shows the voltage waveform appearing at the output terminal 0. φ1. φ2. φ5. φ4
+l'5+φ6 are switch, inch S21, S22, and
S2s・S24・(S's, Su)・(S14・5
15) indicates the phase in which the state becomes conductive.

This embodiment is a delay line having a tap output terminal in which two stages of delay circuits are connected in cascade.

The operation of this embodiment will be explained.

Capacitor C21 in Figure 9
alternately samples the delayed output voltage of the previous stage and inputs each to the amplifier A1s. Sui Nochi S2+, S
22 is the capacitor C21, and a switch 525S24 is a switch S for controlling the input of the capacitor C22.
1s, Sea is capacitor CI2 cD input/output f
l+II control, switch S'5. S16 is capacitor C
13 input/output side? n wo row tx 5゜capacitor C12
and capacitors c and s are respectively switches S15 t 5
14 and switch 5Sea K from the capacitor C2j
Amplifier AI alternately synchronizes with the transfer period of and (?22)
The connection is controlled between the output terminal 1 of No. 5 and the ground.

Next, the overall operation will be explained in detail as time passes. First, one phase φ2 is applied, and the capacitor C2j is connected to the input terminal of the amplifier A13 via the switch S22, and the delay signal of the previous stage sampled at one phase φ is inputted to the amplifier Ala Ic.

At this time, the capacitor C12 is switched due to the phase φ5.

The output terminal of the amplifier A13 is connected by a capacitor s1s between the input and output terminals of the amplifier A13, and the output of the amplifier A13 outputs a voltage corresponding to the charge of the capacitor C21. On the other hand, both ends of the capacitor cps are grounded by the switch S+6 to discharge the charge.

Next, in one phase φI, the capacitor C21 samples the delayed output voltage of the previous stage using the switch S21.

At this time, the output of the previous stage is output to the switch 514 by one phase φ5.
Since the capacitor CI2 continues to be in a conductive state and both ends of the capacitor CI2 are connected between the input and output terminals of the amplifier A15, a voltage corresponding to the charge of the capacitor CI2 is output. During this time, both ends of the capacitor C43 are grounded by the switches S and 6.

Subsequently, in the second phase φ4, the capacitor C22 inputs the delayed output signal of the previous stage sampled in the phase φ3 connected to the input terminal of the amplifier A, 30 via the switch S24. Due to this transition phase l116, the capacitor CI5 is connected between the input and output terminals of the amplifier A13 by the switch S15, and the output of the amplifier A13 is connected to the capacitor C22.
corresponds to the charge of

On the other hand, both ends of the capacitor CI2 are grounded by the Sui-Sochi Set to discharge the charge.

Furthermore, in one phase φ3, the capacitor C22 samples the delayed output voltage of the stage preceding the switch 523vC. At this time, the output of the previous stage is switched to switch S1 by 1 phase φ6.
5 continues to be conductive and the capacitor cps is connected between the input and output terminals of the amplifier A1H, so that a voltage corresponding to the charge of the capacitor c1s is output. During this time as well, both ends of the capacitor C12 are grounded.

The voltage at each output terminal becomes phase φ2 again, and the same is repeated thereafter.
If the sampling interval of 2 is T, then the signal at the output terminal N is delayed by 2T with respect to the input voltage at the input terminal M, and the signal is delayed by 4T (2T+2) at the voltage output terminal O, which shows the opposite polarity.
T) According to this embodiment, which outputs delayed voltages showing the same polarity, the number of amplifiers, capacitors, and switches can be reduced, the delay time per stage of delay circuit is 2T, the output waveform is a hold waveform, and the input voltage is It is also possible to construct a tapped delay line that outputs a voltage having a polarity opposite to that of the input signal.

FIG. 11 is a circuit diagram showing another embodiment of the present invention. In FIG. 11, S2+o + 522o, 52
so and S24° are switches, P is an input terminal, and Q and R are output terminals. Figure 12 is the 11th
FIG. 2 is a time chart showing the operating state of each switch shown in the figure and a waveform diagram showing signal waveforms of each terminal. In FIG. 12, (a) shows the operating state of switch S2+O.

(, 6) is the operating state of switch 522 (+, (C) is the operating state of switch 5250, (d) is the operating state of switch S24°, (e) is the operating state of switches S1S and S16, (7') (g) shows the voltage waveform applied to the input terminal P, and (A) shows the voltage waveform appearing at the output terminal Q. (L) shows the voltage waveform appearing at the output terminal RK. φ4. φ2.φ3.φ4
．． φ5. φ6 are respectively switches S2. o, 522
o, 52so, 52ao, (S1s, Su
), (Su.

The phase at which S, 5) becomes conductive, and T indicates the sampling period.

In this embodiment, the delay time per stage of the delay circuit is twice the sampling period T, the output signal voltage outputs a voltage having the same polarity as the input signal voltage, and the output waveform is a hold waveform. This is a two-stage cascade connection of tapped and delay lines.

The operation of this embodiment is almost the same as that in FIG. 9, and the capacitor C21 is connected to the switch 521015220.

The input and output of the capacitor C22 are controlled by the switches 52so + 52aa, respectively, and after sampling the signal voltage from the previous stage, the capacitor C21 or , by inverting the input and output terminals of the i-yaya patta C22 and inputting it to the amplifier A15, Fig. 12 (!1), (A),
As shown in (i), each output terminal has a voltage of the same polarity delayed by 2T at output terminal Q with respect to the voltage applied to input terminal P, and a voltage of the same polarity delayed by 4T (2T+2T) at output terminal R. Output each voltage.

According to this embodiment, the number of amplifiers, capacitors, and switches can be reduced, and the delay time per stage of delay circuit is 21. The output waveform is a hold waveform.

It is possible to configure a tapped delay line that outputs a voltage having the same polarity as the input voltage.

FIG. 15 is a circuit diagram showing another embodiment of the present invention. In FIG. 15, S is an input terminal, and U and V are output terminals. FIG. 14 shows a time chart showing the operating state of each switch shown in FIG. 15. In FIG. 14, (a) is the operating state of switch S1, (b) is the operating state of switch S22, (C) is the operating state of switch 5210, (d) is the operating state of switch 5220, and (e) is the operating state of switch 5220.
is the operating state of switch 5250, 0) is the operating state of switch 524
0, (c) is the operating state of the switch S'sS16, (h) is the operating state of the switch S14. The operating state of S15 is shown in detail. T indicates the sampling period of the signal.

This embodiment is a delay line in which delay circuits of 2T, in which the delay time per stage of delay circuit is equal to T and twice the sampling period, are connected in cascade.

The operation of this embodiment can be understood without further explanation from the explanation of the operation of the above-mentioned embodiment. The output voltage at each output terminal shown in FIG. 13 is a voltage of opposite polarity that is delayed by a time T at the output terminal U with respect to the input voltage applied to the input terminal S.

A voltage of opposite polarity delayed by 5T (T+2T') is outputted to the output terminal V, respectively.

According to this embodiment, the number of amplifiers, capacitors, and switches can be reduced, and the first stage delay circuit shows a voltage of opposite polarity to the input voltage delayed by a time T, and the voltage waveform becomes the hold waveform. IB is input, and the second stage delay circuit shows a voltage of the same polarity with respect to the input voltage waveform delayed by a time of 2T.

It is possible to configure a tapped delay line that outputs a voltage whose glJL pressure waveform is a hold waveform.

It is clear that a transvercal filter can be constructed by connecting a variable gain controller or a fixed coefficient multiplier to each input/output terminal of these embodiments and adding their outputs.

〔Effect of the invention〕

According to the present invention, the number of amplifiers, capacitors, and switches can be reduced compared to the prior art, and a delay line that obtains a delay time proportional to the sampling period can be configured, which is advantageous for 1'C implementation. Also, the polarity of the output voltage for each delay circuit,
By considering the amount of delay in advance when designing, it is possible to simplify a coefficient unit such as a transversal filter.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional delay line, Fig. 2 is a time chart showing the operating status of each switch in Fig. 1, and a waveform diagram showing signal waveforms at each terminal, and Fig. 3 is an embodiment of the present invention. A circuit diagram showing an example. Fig. 4 is a time chart showing the operating state of each switch in Fig. 3, and a waveform chart showing the signal waveform of each terminal, Fig. 5, Fig. 7, Fig. 9, and Fig. 11. 13th
The figures are circuit diagrams showing other embodiments of the present invention, and FIGS. 6, 8, 10, 12, and 14 are circuit diagrams, respectively. FIG. 14 is a time chart showing the operating state of each switch in FIG. 13 or a waveform chart showing the signal waveform of each terminal. In the figure -AN, "12 + AIB=・amplifier,
co+ -co: CO5, CO4, CII, CI2
,CI3,"21,C22°"°canokushita,
5O5o2. Sos, Su4. Su5. Su
6. S++; Su2. S1s, S1a,
S1b, Su. S21. S22. S25. S2a, S++o
, S+2o, 521o, 522o, 52
so, 52ao ゛ switch. Fig. 2 @ 4 gall 1 - T3 mother waste ri @ 82 □B￥f between Fig. 70 Death / Fig. 2

Claims (1)

[Claims] an amplifier, a plurality of first capacitors whose input/output terminals are alternately connected between an output terminal and an inverting input terminal of the amplifier, and a ground; and a connection between the first capacitor and the first capacitor. a second capacitor or capacitors for signal accumulation from the signal input terminal and transfer of the accumulation signal to the inverting input terminal of the amplifier;
and a switch circuit that controls the storage and transfer operations of the 27Q capacitor in synchronization with the connection control of the first capacitor, and delays the signal input from the signal input terminal and takes it out from the output terminal of the amplifier. A delay line comprising one or more stages of delay circuits connected in series.