JPS60157329A - Delay line - Google Patents

Abstract

PURPOSE:To obtain a circuit which is advantageous to conversion into an IC by using three pairs of capacitors which are controlled with connection to an amplifier to constitute a delay circuit and therefore decreasing the number of amplifiers, capacitors and switches. CONSTITUTION:At first a capacitor C11 samples an input via a switch S11 and at the same time a capacitor C12 is connected to an amplifier A13 by a switch S15. A capacitor C13 samples the output of the amplifier A13 by a switch S14. Then the C13 is connected to the input terminal of the A13 via a switch S12, and the C13 is connected to the input terminal of the A13 by a switch S13. Then the input and output terminals of the C12 are inverted by a switch S16 and connected between the input and output terminals of the A13. Thus it is possible to obtain the output voltage which is delayed by a switching cycle T.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal delay line, and particularly to a tapped delay line suitable for the configuration of a transversal filter that facilitates integration into an integrated circuit (IC). .

[Background of the invention]

Figure 1 is a circuit diagram showing a conventional delay line.

8 in Fang 1 figure, S(H* S6t+ Soy: + 8
84-MOB, 5Q11 is a switch, C
o + , C'ot and Cos -Cn< are each capacitors, A11. A,! are each an amplifier, A is a signal input terminal, and H and C are each an output terminal.

, 1 to 2 are switching time charts of each switch in FIG. 1 and waveform diagrams showing signal waveforms at input terminal A and output terminals B and C.

In Figure 2, lal is switch 8n+, "OR"
5011 switching form f1. lbl is switch S
. 1118041 Switching state of S06, (C1
is the voltage waveform applied to the input terminal A, ldl is the voltage waveform appearing at the output terminal B, and te+ is the voltage waveform appearing at the output terminal C.

The operation of this conventional example will be explained below.

Switch S01 'SO3' SOB is the spear 2 (a)
, switch S02.804, soa performs a switching operation as shown in Figure 2 (bl), and the switching period is T.

Now, the switches Sob, Sas, and Sow are in a conductive state (ON).
).

Switch Soz+So4.8oe is in non-conducting state (o F
F). In this state, the delayed output voltage of the previous stage is applied to the input terminal A, and the delayed output voltage of the previous stage is applied to the capacitor C81.
The voltage is stored in the capacitor C62, and the voltage stored in the capacitor CO2 is reset. Furthermore, capacitor C8, amplifies 5 At! is connected to the inverting input terminal of the capacitor C84, and an output voltage is applied across the capacitor C84, and the output voltage is stored in the capacitor Co4. Next, the switch So+'Son'5oll becomes non-conductive, and the switch S02'8G41 soa becomes conductive. Capacitor C01 that stores the output voltage of the previous stage
is connected to the inverting input terminal of amplifier AII and capacitor C
620, the output voltage is stored in the capacitor C82, and the capacitor C8 is connected to the amplifier A,
It is connected to the output terminal of the capacitor COt and stores a voltage proportional to the '1 voltage stored in the capacitor COt. Also, capacitor C
At O4, the accumulated voltage is reset. Next again, switch S0. , So,, So, becomes conductive, and switch sown 5041 soa becomes non-conductive,
Similar operations are repeated.

As described above, in the conventional method, in order to design a delay circuit that obtains a delay time equal to the switching frequency #JT, two amplifiers and a large number of capacitors are required as shown in Figure 1. Two spears (di, t)
As shown in el, the output waveform becomes a comb-shaped waveform, so a hold circuit is required, and I
It was disadvantageous for C conversion.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art.The purpose of the present invention is to reduce the number of amplifiers, capacitors, and switches compared to the conventional art, and to connect delay circuits in cascade, which is advantageous for IC implementation. The purpose of the present invention is to provide a tapped signal delay line.

[Summary of the invention]

According to the present invention, a first capacitor is connected and controlled between an output terminal and an inverting input terminal of the amplifier, a switch circuit that controls the connection of the first capacitor, and one end of which is connected to the inverting input terminal of the amplifier. A second capacitor whose connection is controlled such that it is connected alternately to a terminal and an output terminal and the other end is grounded, a switch circuit that controls the connection of the second capacitor, and a signal accumulation and accumulation signal from a signal input terminal. The storage and transfer operations of one or a mantissa capacitor of spear 3 and the capacitor of spear 6 which transfer data to the inverting input terminal of the amplifier are controlled in rotation with the connection of the capacitor of the first spear 2. This is achieved by configuring delay 1# using a delay circuit consisting of a switch circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

Figure 3 is a circuit diagram showing one embodiment of the present invention. spear 6
In the figure, A1. is the amplifier, Sl.

81t'511814.81B'8111 are each a capacitor, D is an input terminal, and E and F are output terminals.

, 1 to 4 are time charts showing the operating states of each switch shown in FIG. 3 and waveform diagrams showing signal waveforms at each terminal. In Figure 4, (al is switch S11'5I
Operation status of 41Sllll, (bl is switch 81!l
(C1 is the voltage waveform applied to the input terminal, ldl is the voltage waveform applied to the output terminal E, and (e) is the voltage waveform appearing at the output terminal F.

T indicates the period of operation of these switches, φ,.

φ2 is switch 81+・5118+3. S14+5lu
st. indicates the phase when becomes conductive.

This embodiment is a delay line having a 2-tap output terminal and a terminal in which two stages of delay circuits are cascaded.

First, in Figure 3, which briefly explains the operation of the valley elements, switches S, . . . S1. performs input/output control of the capacitor C11. The capacitor C1l is connected to the switch 8s.
After sampling the output voltage sampled and held in the previous stage by s, 8+t at a constant cycle, the amplifier A1
．． connected to the input terminal of Switch S11. Sl, performs input/output control of the capacitor CIA, respectively. The capacitor CI, is connected to the amplifier A by the switch S'', S+4.
1. After sampling the output voltage of the amplifier A at a period synchronized with the sampling of the capacitor C8.

connected to the input terminal of Switch 811118111
are each capacitor CI! Performs input/output control.

The capacitor Ctt is connected to the amplifier A1 . The input and output terminals of the capacitor Cl11 are connected between the input terminal and the output terminal of the capacitor Cl11 so as to be inverted.

The overall operation will now be explained in detail. First, in phase φ1 in FIG. 4, the capacitor CIt samples the delayed output voltage sampled and held in the previous stage via the switch 8ml. Capacitor C12 is connected to amplifier A1. by switch srs. A voltage corresponding to the charge held in the capacitor C1t appears at the output terminal of the amplifier AI3, which is connected between the input terminal and the output terminal of the amplifier AI3. Further, the switch S14 is in a conductive state, and the capacitor Cl11 samples the output voltage of the amplifier AIfi.

Then, in phase φ, capacitor CII is connected to switch S
1. is connected to the input terminal of the amplifier 41 through the capacitor CI! The input and output terminals of the capacitor C+t are inverted by the switch S16, and the amplification is performed.

There is a wire between the input terminal and the output terminal of the terminal. The input and output terminals of the capacitor C+a are inverted by the switch 8111, and one end of the thousand-yapacitor C1m is grounded, and the other end is connected to the amplifier A8. connected to the input terminal of

At this time, the charge of capacitor C11 and capacitor C1!
'1 voltage corresponding to the charge of the amplifier A1. and the charge of the capacitor C1. appears at the output terminal of Thereafter, similar operations are repeated. Note that the delayed output voltage in one stage of the delay circuit can be obtained as a voltage delayed by the switching period T, and the amplifier A1B operates as an inverting amplifier. In other words, as shown in Figure 4 (cl, (dl, tel), for the input voltage at the input terminal, the output terminal E
A voltage of the same polarity delayed by a time T appears at the output terminal F, and a voltage of the same polarity delayed by a time 2T appears at the output terminal F, respectively.

According to this embodiment, it is possible to reduce the number of amplifiers and capacitors in the delay circuit in order to obtain the same delay time. Further, it is possible to configure a tapped delay circuit in which the delay time per stage of delay circuit is equal to the switching period T and the output waveform is a hold waveform.

Next, other embodiments of the present invention will be described.

Figure 5 is a circuit diagram showing another embodiment of the present invention. Fang 5
In the figure, Sll. , Sl. are the switches,
G is an input terminal, and Hll is an output terminal. spear 6
The figure is a time chart showing the operating state of each switch shown in Figure 5, and a waveform chart showing the signal waveform of each terminal. In Figure 6, (al is switch S1.., SI4.S
l, the operating state of switch Sl! 'O+811
+S16 operating state, tel is the voltage waveform applied to the input terminal G, (di is the voltage waveform appearing at the output terminal H, te
l indicates the voltage waveform appearing at the output terminal l.

This embodiment is a delay line having a two-tap output terminal in which two stages of delay circuits are connected in cascade, the delay time per stage of the delay circuit is a switching period T, and the output voltage has the opposite polarity to the input voltage. Shows the held voltage waveform.

The operation of this embodiment is similar to that shown in Figure 3, except that the capacitor C1l is connected to the switch S11°, Sl! . The input/output is controlled by rL, and after sampling the signal voltage from the pre-installation, the input/output terminal of the capacitor C□ is inverted and inputted to the amplifier A13.
As shown in tel, in response to the input paper pressure applied to input terminal G, output terminal H receives a voltage whose polarity is reversed with a delay of T, and output terminal terminal receives a voltage of the same polarity with a delay of 2T. Each appears.

According to this embodiment, in order to obtain the same delay time, the number of amplifiers and capacitors as a delay circuit can be reduced.
An output voltage with the opposite polarity to the delayed output voltage of the previous stage is output, and the delay time per delay circuit stage is the switching period T.
A tapped delay line whose output waveform is a hold waveform can be configured.

Figure 7 is a circuit diagram showing another embodiment of the present invention. On the 7th figure? , J is the input terminal, and K is the input terminal.

L is an output terminal. Figure 8 is a time chart showing the operating state of each switch shown in Figure 7, and a waveform chart showing signal shaping at each terminal.

In Figure 8, (al is switch "1118110.
S14. The operating state of S11, (bl is switch 8111
81! . The operating state of eSI S eSI B, (voltage waveform applied to C and input terminal JK, id) indicates the voltage waveform appearing at the output terminal K, and let indicates the voltage waveform appearing at the output terminal.

The operation of this embodiment can be easily understood from the operation of the circuits shown in Figure 3 and Figures 1-5.

Therefore, as shown in Figure 8 (Ci, !di, (el K), the delay time of the first stage of the delay circuit is the switching period T, and in the first stage delay circuit, the output voltage (the peak is the input voltage (C1) On the other hand, a second-stage delay circuit with the same polarity shows an output whose polarity is inverted with respect to the output voltage (el is the input voltage Td).

According to this embodiment, the number of amplifiers and capacitors can be reduced as a busy delay circuit to obtain the same delay time.
Furthermore, the delay time per stage of the delay circuit is equal to the switching period T, and for each delay time T, an output voltage having the same polarity or an inverted polarity (coefficient) with respect to the input voltage is output μ.
A tapped delay line whose output waveform is a hold waveform can be configured.

Figure 9 is a circuit diagram showing another practical example of the present invention.
, In Figure 179, 811181g+81B*S,
4 are switches, C, . . . , C□ are capacitors, M is an input terminal, and N and 0 are output terminals. , 17in figure is a time chart showing the operating state of each switch shown in Figure 9, and a waveform chart showing the signal waveform of each terminal. , 1'F10, (a) is the switch S
7. (b) is the operating state of switch stt,
(C) is the operating state of switch S□, (d) is switch S
, 4, (e) is the operating state of switch 81m+ 816, (f+ is the operating state of switch 814.81C,
(g) shows the voltage waveform applied to the input terminal M', (h) shows the voltage waveform appearing at the output terminal NK, and m shows the voltage waveform appearing at the output terminal O. φ1. φ8. φ3. φ4. φ6. φ6
are switches s, 1, respectively. s□, 8zs, 'ba +
(818181+1)l (814,8111) indicates the phase in which it becomes conductive.

This embodiment is a delay line having two tap output terminals in which two stages of delay circuits are connected in cascade.

The operation of the non-embodiment will be explained.

In Figure 9, capacitor CWt at -16 is connected to switch S2. The delayed output voltage of the previous stage is sampled through the phase φ2, and the voltage is held until phase φ2. Further, the capacitor C1 is connected to the output terminal of the amplifier AI when the switch 814 becomes conductive at the phase φ6, and the capacitor C1 is connected to the output terminal of the amplifier AI.
11 and switches S and 14C to the amplifier to sample the output voltage holding the output of 0.

Next, capacitor C! ! is the switch S at the phase φ,
The output voltage of the previous stage is sampled through ts'r, and the al pressure is maintained until phase φ4. At this time as well, the phase φ6
A capacitor C1 is connected to the output terminal of the amplifier All, and the output voltage holding the output of the amplifier A is sampled by the capacitor C1 and the switch 5IIIK.

Note that the operations will be explained step by step as time passes.

First, in phase φ, capacitor CIl is connected to amplifier A3 through switch S□. is connected to the input terminal of the phase φ
The delayed output signal of the previous stage sampled at 1 is input to the amplifiers A, . At this time, due to the phase φ, the capacitor 011 is connected by the switch 5111 to the capacitor C1! between the input and output terminals of the amplifier kHB. The input and output terminals of the switch S1. The input/output terminals are inverted, one end is connected to the input terminal of the amplifier AIB, and the other end is grounded. At this time, the amplifier Al
11 outputs a voltage corresponding to the sum of charges of capacitors c*+ and cst'cta.

Then, in phase φ, capacitor C! S samples the delayed output voltage of the previous stage using switch 8111,
In the phase φ synchronized with this, the capacitor C1t is connected between the input and output terminals of the amplifier All by the switch 8111. The input and output terminals of the amplifier A1B are inverted and connected, and the output of the amplifier A1B is a voltage proportional to the charge of the capacitor C1l, which is maintained during this period. In addition, the capacitor Css inverts the input and output terminals of the capacitor C13 by a switch 814, so that one end is grounded and the other end is connected to the amplifier A.
Connected to the 1° output terminal.

Subsequently, in phase φ4, capacitor C1t is connected to the input terminal of amplifier A130 via switch 8!4, and inputs the delayed output signal of the previous stage sampled in phase φ. At this time, due to the phase φ, the capacitor Ctt is connected between the input and output terminals of the amplifier AI by the switch 81+1, inverting the input and output terminals of the capacitor C1t,
The capacitor CIA inverts the input and output terminals of the capacitor Cl1l by a switch 5lfi, and one end is connected to the amplifier Δ1.
is connected to the input terminal of the terminal, and the other end is grounded. At this time, the output of the amplifier Al11 is connected to the capacitor C□*C12* (
A voltage that resonates with the sum of the respective charges of -1B is output.

Furthermore, in phase φ, capacitor C□ is connected to switch a
ll samples the delayed output voltage of the previous stage, and in phase φ synchronized with the delayed output voltage, the capacitor C11 is connected to the amplifier A1 . The input and output terminals of the capacitor C0 are inverted and connected between the input and output terminals of the amplifier A1. A voltage proportional to the charge of the capacitor C1t is outputted, and this voltage is maintained during this period. Further, the capacitor CIm is connected to the capacitor C1s by the switch 814.
The input and output terminals of the amplifier A1. connected to the output terminal of

The voltage at each output terminal is determined by the switch 811814s
If T is the period of the switching operation of ss + s, then the signal at the output terminal N is delayed by 2T and has the same polarity with respect to the signal voltage at the input terminal M, and the signal at the output terminal 0 is 4T.
Voltages that are delayed by T (2T+2T) and exhibit the same polarity appear, respectively.

According to this embodiment, the number of amplifiers, capacitors, and switches can be reduced, an output signal voltage with the same polarity as the input signal voltage is output, the delay time per stage of delay circuit is 2T, and the output waveform is a hold waveform. A tapped delay line can be configured as follows.

Figure 11 is a circuit diagram showing another embodiment of the present invention. In Figure 11, St+. ,S! ! . , So. , S□.

are switches, P is an input terminal, and Q and P are output terminals. FIG. 12 is a time chart showing the operating state of each switch shown in FIG. 11, and a waveform diagram showing signal waveforms at each terminal.

In Figure 12, (al is the operating state of switch S6.., (b) is the operating state of switch S□0, IC) is the operating state of switch 823G, (d) is the operating state of switch S24°, and tel is the operating state of switch S□0. The operating state of switch 5illS16, +fl is the operating state of switch 8141SIII, Ig
1 represents the voltage waveform applied to the input terminal P, and 1 represents the voltage waveform appearing at the output terminal Q.+i+ represents the voltage waveform appearing at the output terminal H. φ.

φ1. φ1. φ1. φ6. φ6 is each switch S2
t. .

8*to, S*so, 8*4o, (8sa, S+a >
(814,8+s) is the phase at which it becomes conductive, T is the period of operation of the switch 8111816.8141SIII, and indicates the sampling period of the signal.

In this example, the delay time per stage of delay circuit is twice the sampling period (2T), the output signal voltage outputs a voltage with the opposite polarity to the input signal voltage, and the output waveform is a hold waveform. This is a delay circuit with two tap output terminals in which two stages of circuits are connected in cascade.

The operation of this embodiment is almost the same as that shown in Figure 9, but the capacitors C1l and ct* are each switched by a switch (Ssto+
5tto) + (8tao+5tao) After sampling the signal voltage fPt#i from the previous stage, the input and output terminals of the capacitors C, 1, are inverted and inputted to the amplifier A1B. ,
As shown in Figure 12 (gl, (hl, (it)), a delayed output voltage having a polarity opposite to that of the input signal voltage of each delay circuit is output to each output terminal.

According to this embodiment, the number of amplifiers, capacitors, and switches can be reduced, an output voltage whose polarity is inverted with respect to the output voltage of the previous stage delay circuit is output, the delay time is 2T per delay circuit stage, and the output waveform is It is possible to construct a tapped delay line where is the hold waveform.

Figure 15 is a circuit diagram showing another embodiment of the present invention. In Figure 13, S is an input terminal and U is an input terminal.

■ are output terminals. The 14th figure of the spear is! FIG. 14 is a time chart showing the operating state of each switch shown in FIG. 13 and a waveform chart showing signal waveforms of each terminal. In Figure 14, (a) is the operating state of the switch 5210, (bl is the operating state of the switch S!m., and (C) is the operating state of the switch S, 11G.
(d) is the operating state of switch 5t4o, l
et is the operating state of switch 5It0.81B1816.

(fl is the operating state of the switches 5110.S14, 5ill, (gl is the voltage waveform applied to the input terminal S, (hl is the voltage waveform appearing at the output terminal U, m is the voltage waveform appearing at the output terminal V, and the phase φ1. φ8.φ8.φ4 +
'/', -φ6 are switches 5tIO0S, o, respectively.
S2. o, S, 4゜+ (8s*o, 8Is+S+a
), (SIIO1SL4.Sss) indicate the phase in which they become conductive, and T is the switch 51111'81! .

, S+s・Sss, 8t+, 8+a, and indicates the S/Bling cycle of the input signal.

This embodiment is a delay line in which delay circuits of 2T, which have a delay time T equal to the sampling period and twice the delay time of one stage of delay circuits, are connected in cascade.

The operation of this embodiment can be understood from the explanation of the operation of the above-mentioned embodiment without further explanation. Therefore,
As shown in Fig. 14, the output voltage at each output terminal is different from the input voltage at the input terminal 811C.
has the same polarity delayed by 2T, and output terminal V has a voltage of 3T (
2T + T) A delayed voltage with reversed polarity appears, respectively.

According to this embodiment, the number of amplifiers, capacitors, and switches can be reduced, and a tapped delay line can be constructed in which the delay time is an integral multiple of the sampling period T and a delayed output voltage having an arbitrary polarity is obtained for each delay circuit. I can do it.

It is clear that a transversal filter can be constructed by connecting a variable gain controller or a fixed coefficient multiplier to each input/output terminal of these embodiments and calculating the outputs thereof.

〔Effect of the invention〕

According to the present invention, it is possible to configure a delay line that obtains a delay time proportional to the sampling period by reducing the number of amplifiers, capacitors, and switches compared to the conventional technology, which is advantageous for implementing an IC. By considering the polarity of the output and the amount of delay beforehand, it is possible to simplify the coefficient unit such as a transnosal filter.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional delay line, and Figure 172 is a circuit diagram showing a conventional delay line.
In the figure, a time chart diagram showing the operating state of each switch and a waveform diagram showing the signal waveform of each terminal, Figure 3 is a circuit diagram showing an embodiment of the present invention, Figure 4 is the operating state of the switch in Figure 3. Time chart diagram showing each terminal σ)
Waveform diagrams showing signal waveforms, Figure 5, Figure 7 1. i9. Figures 11 and 13 are circuit diagrams showing embodiments of the present invention 0) and other σ), Figures 6 and 8 are 1, 1'F10, Figures 12 and 14, respectively. Figure, Spear 7 Figure 1,? 9, 11, and 13; a time chart showing the operating state of each switch; and a waveform chart showing the signal waveform of each terminal. A,,IA,,IA,,,,,amplifier,01111C
11t-COa-C(+41c111c1m'C*a+
Ctx+C**-capacitor, sot l sat'
sos, 804, soa 180111 Sll
I S118118341sts”11115ll
(115lIO18□, 8!!. e%s 181!418t+o l 5tto, 81
m. , S24°...switch. Representative patent attorney Akio Takahashi.

Claims (1)

[Claims] 1. An amplifier, a capacitor whose input/output terminals are controlled to be connected between the output terminal and the inverting input terminal of the amplifier, a switch circuit which controls the connection of the first capacitor, and the amplifier. A second capacitor whose connection is controlled so that the input and output terminals are alternately inverted and the other end is grounded to the inverted input terminal and output terminal of the second capacitor, a switch circuit that controls the connection of the second capacitor, and a signal one or more capacitors of the spear 3 for storing the signal from the input terminal and transferring the stored signal to the inverting input terminal of the amplifier;
and a switch circuit that controls the storage and transfer operations of the capacitor 173 in synchronization with the connection of the first and second capacitors, and delays the signal input from the signal input terminal so as to control the operation of the amplifier and the transfer circuit. A delay line characterized in that it is formed by cascading one or more stages of delay circuits that are taken out from an output terminal.