JPH0446007B2 - - Google Patents
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- Publication number
- JPH0446007B2 JPH0446007B2 JP58109186A JP10918683A JPH0446007B2 JP H0446007 B2 JPH0446007 B2 JP H0446007B2 JP 58109186 A JP58109186 A JP 58109186A JP 10918683 A JP10918683 A JP 10918683A JP H0446007 B2 JPH0446007 B2 JP H0446007B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- input terminal
- operational amplifier
- switching means
- common potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 73
- 238000000034 method Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 3
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/002—N-path filters
Description
【発明の詳細な説明】
（技術分野）
本発明はLSI化に適したDCオフセツト量の少
いスイツチトキヤパシタSC形遅延等化器に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a switched capacitor SC type delay equalizer with a small amount of DC offset, which is suitable for LSI implementation.
（背景技術）
フアクシミリ等の情報伝送の普及に伴つて、情
報伝送に用いられる機器の小形化、低コスト化が
強く求められている。これらの要請に対して、機
器のLSI化が必須条件である。遅延等化器のLSI
化に適した構成法として、次の２つの方法が考え
られる。(Background Art) With the spread of information transmission such as facsimile, there is a strong demand for smaller and lower cost equipment used for information transmission. In response to these demands, converting devices to LSI is an essential condition. Delay equalizer LSI
The following two methods can be considered as configuration methods suitable for this purpose.
(1) スイツチ、キヤパシタ及び演算増巾器（OP
−AMP）を用いる方法。(1) Switches, capacitors, and operational amplifiers (OP
-AMP) method.
(2) 抵抗、キヤパシタ及びOP−AMPを用いる方
法。(2) Method using resistor, capacitor and OP-AMP.
LSIにより構成された素子の偏差が同一ロツト
内に於ても（10〜20％）位が限度であるため、素
子の精度が厳しく要請される上記(2)を方法は不適
当である。特に、MOS構成の場合、同一ロツト
内の素子の偏差は大きくしても、偏差のバラツキ
は少い。この特徴を生かした構成法として、上記
(1)の方法がある。現在、(1)の方法により、遅延等
化器のLSI化が進められている。第１図は一般に
よく用いられるSCを用いた遅延等化器である。
第１図の伝送関数T1（z-1）は次式で与えられる。 Since the deviation of devices constructed by LSI is limited to 10 to 20% even within the same lot, method (2) above, which requires strict precision of the devices, is inappropriate. In particular, in the case of a MOS configuration, even if the deviation of elements in the same lot is large, the variation in deviation is small. As a configuration method that takes advantage of this feature, the above
There is method (1). Currently, LSI implementation of delay equalizers is progressing using method (1). FIG. 1 shows a commonly used delay equalizer using SC.
The transmission function T 1 (z −1 ) in FIG. 1 is given by the following equation.
Ｔ（z-1）＝−K2＋K4＋（K1K5−K2−K3−2K4
）z-1＋（K3＋K4）z-2／１＋（K5K6＋K5K7−２）z-1＋
（１−K5K7）z-2……(1)
ここで、ｚ＝ejwT、Ｔ＝１／fc、fcはクロツク
周波数である。 T (z -1 ) = -K 2 +K 4 + (K 1 K 5 -K 2 -K 3 -2K 4
)z -1 + (K 3 +K 4 )z -2 /1 + (K 5 K 6 +K 5 K 7 -2)z -1 +
(1-K 5 K 7 )z -2 (1) where z=e jwT , T=1/fc, and fc is the clock frequency.
一般に、遅延等化器の伝達関数T2（z-1）は次
の様になる。 Generally, the transfer function T 2 (z -1 ) of a delay equalizer is as follows.
T2（z-1）＝−A2＋A1z-1＋A0z-2／A0＋A1z-1
＋A2z-2……(2)
また、遅延特性τ（ｗ）は式(2)より次の様にな
る。 T 2 (z -1 ) = -A 2 +A 1 z -1 +A 0 z -2 /A 0 +A 1 z -1
+A 2 z -2 ...(2) Also, the delay characteristic τ(w) is as follows from equation (2).
τ（ｗ）＝2TA0A1coswT−A1A2coswT＋２（A2
／0−A2／2）／A2／0＋A2／1＋A2／2＋2A1A2coswT＋2A0
A2cos2wT＋2A1A0coswT……(3)
ここで、式(2)のA0、A1、A2と式(1)のK1、K2、
……、K7の間には次の関係がある。 τ(w)=2TA 0 A 1 coswT−A 1 A 2 coswT+2(A 2
/ 0 −A 2 / 2 ) /A 2 / 0 +A 2 / 1 +A 2 / 2 +2A 1 A 2 coswT + 2A 0
A 2 cos2wT + 2A 1 A 0 coswT...(3) Here, A 0 , A 1 , A 2 of formula (2) and K 1 , K 2 of formula ( 1 ),
..., K 7 has the following relationship.
K5K7＝１−A2 ……(4)
K5K6＝A1＋A2＋１ ……(5)
K1K5＝A1＋A0＋A2 ……(6)
A0＝K3＋K4 ……(7)
A2＝K2＋K4 ……(8)
従つて、遅延等化器の設計に於ては、まず、要
求遅延特性をA0、A1、A2をパラメータとして式
(3)を用いて近似する。要求規格を満足するA0、
A1、A2の値を求め、式(4)〜式(8)の関係により第
１図の容量比K1、K2……K6を決定する。 K 5 K 7 =1−A 2 ...(4) K 5 K 6 =A 1 +A 2 +1 ...(5) K 1 K 5 =A 1 +A 0 +A 2 ...(6) A 0 =K 3 +K 4 ...(7) A 2 =K 2 +K 4 ...(8) Therefore, when designing a delay equalizer, first set the required delay characteristics using A 0 , A 1 , and A 2 as parameters. formula
Approximate using (3). A 0 that satisfies the required standards,
The values of A 1 and A 2 are determined, and the capacitance ratios K 1 , K 2 .
次に、遅延等化器より生じるDCオフセツト量
について述べる。DCオフセツト量については、
SC回路が一般にクロツク周波数fc≫使用周波数
ｆに近い条件で用いられるので、SC回路を直接
DCオフセツト量について解析するよりも、SC回
路を等価RC回路に変換して論ずる方が簡単であ
る。第２図は第１図のDCオフセツト量に着目し
た場合の等価RC回路である。第２図に於て、Ein
(1)はOP−AMP1の反転入力端子に存在するDCオ
フセツト量の起電圧、Ein(2)はOP−AMP2の反転
入力端子に存在するDCオフセツト量の起電圧、
Rin(1)はEin(1)の駆動抵抗、Rin(2)はEin(2)の駆動
抵抗である。この回路の出力端子に生ずるDCオ
フセツト量Vout（０）とEni(1)、Ein(2)の関係は、
第２図において節点方程式を解く事により得ら
れ、次式に示す様な簡単な関係になる。 Next, we will discuss the amount of DC offset generated by the delay equalizer. Regarding the DC offset amount,
Since the SC circuit is generally used under conditions close to the clock frequency fc≫the working frequency f, the SC circuit can be directly
Rather than analyzing the amount of DC offset, it is easier to convert the SC circuit into an equivalent RC circuit and discuss it. FIG. 2 shows an equivalent RC circuit when focusing on the amount of DC offset shown in FIG. In Figure 2, Ein
(1) is the electromotive force of the DC offset amount present at the inverting input terminal of OP-AMP1, Ein(2) is the electromotive force of the DC offset amount present at the inverting input terminal of OP-AMP2,
Rin(1) is the driving resistance of Ein(1), and Rin(2) is the driving resistance of Ein(2). The relationship between the DC offset amount Vout(0) generated at the output terminal of this circuit, Eni(1), and Ein(2) is as follows:
This can be obtained by solving the nodal equations in Figure 2, resulting in a simple relationship as shown in the following equation.
Vout(1)＝−R1／Rin(1)Ein(1) ……(9)
従つて、出力端子に生ずるDCオフセツト量に
ついては、OP−AMP2の反転入力端子に存在す
るDCオフセツト量Ein(2)は全く関係ないことがわ
かる。 Vout(1)=-R 1 /Rin(1)Ein(1) ...(9) Therefore, regarding the amount of DC offset occurring at the output terminal, the amount of DC offset present at the inverting input terminal of OP-AMP2 Ein( It turns out that 2) is completely unrelated.
よつてVout（０）はRin(1)、Ein(1)が固定であ
るため、R1によつて決定される。すなわち、遅
延等化器の設計に於て、R1をいかに小さくする
かにかかつてくる。また、第２図の回路は第１の
回路の等価RC回路であるため、R1及びR2は第１
図の容量の間に次の様な関係がある。 Therefore, since Rin(1) and Ein(1) are fixed, Vout(0) is determined by R1 . In other words, the design of the delay equalizer depends on how small R 1 can be made. Also, since the circuit in Figure 2 is an equivalent RC circuit of the first circuit, R 1 and R 2 are
The following relationship exists between the capacities shown in the figure.
第１図の回路に於ては、Vout（０）は、いかに
してK6を大きくなる様に設計するかにかかつて
いる。 In the circuit of FIG. 1, Vout(0) depends on how K 6 is designed to be large.
（発明の目的）
本発明は、回路自身から生じるDCオフセツト
量の少い回路構成のスイツチトキヤパシタを用い
た遅延等化器を提供することを目的とする。(Objective of the Invention) An object of the present invention is to provide a delay equalizer using a switched capacitor having a circuit configuration in which the amount of DC offset generated from the circuit itself is small.
（発明の概要）
本発明のスイツチトキヤパシタ遅延等化器は、
積分容量を備え、且つ非反転入力端子が共通電位
点へ接続された第１演算増幅器と、前記積分容量
と同じ容量を備え、且つ非反転入力端子が共通電
位点へ接続された第２演算増幅器と、信号入力端
子と前記第２演算増幅器の反転入力端子との間に
接続された第１容量K5と、信号入力端子と前記
第１演算増幅器の反転入力端子の間に接続された
第２容量K3と、
第３容量K1と、
第４容量K2と、
第５容量K6と、
第６容量K7と、
第７容量K4と、
前記第１演算増幅器の前記反転入力端子と共通
電位点とを切換えて前記第３容量K1の一端へ接
続する第１スイツチング手段SW1と、前記第１
演算増幅器の出力端と共通電位点とを切換えて前
記第３容量K1の他端へ接続する第２スイツチン
グ手段SW2と、前記信号入力端子と共通電位点
とを切換えて前記第４容量K2の他端へ接続する
第３スイツチング手段SW3と、前記第１演算増
幅器と反転入力端子と共通電位点とを切換えて前
記第４容量K2の前記一端へ接続する第４スイツ
チング手段SW4と、前記第１演算増幅器と出力
端子と共通電位点とを切換えて前記第５要領K6
の一端へ接続する第５スイツチング手段SW5と、
前記第２演算増幅器の前記反転入力端子と共通電
位点とを切換えて前記第５容量K6の他端へ接続
する第６スイツチング手段SW6と、前記第２演
算増幅器と出力端子と共通電位点とを切換えて前
記第６容量K7と、前記第１演算増幅器の前記反
転入力端子と共通電位とを切換えて前記第６容量
K7の他端へ接続する第７スイツチング手段SW7
と、前記第１演算増幅器の前記反転入力端子と共
通電位とを切換えて前記第６容量K7の一端へ接
続する第８スイツチング手段SW8と、前記信号
入力端子と共通電位点とを切換えて前記第７容量
K4の他端へ接続する第９スイツチング手段SW9
と、前記第２演算増幅の反転入力端子と共通電位
点とを切換えて前記第７容量K4の一端へ接続す
る第10スイツチング手段SW10とを備えたもので
あつて、全ての前記スイツチング手段は２相クロ
ツクで駆動されるものであつて且つ、第１、第
２、第４第５、第６、第８、第９及第10スイツチ
ング手段とからなる組と第３及び第７スイツチン
グ手段とからなる組とは逆相関係で共通接地点へ
接続し、更に容量K1及びK6の値を等しくしてDC
オフセツト出力電圧を小さくしたことを特徴とす
るものである。(Summary of the Invention) The switch capacitor delay equalizer of the present invention has the following features:
A first operational amplifier including an integral capacitor and having a non-inverting input terminal connected to a common potential point; and a second operational amplifier having the same capacitance as the integrating capacitor and having a non-inverting input terminal connected to a common potential point. a first capacitor K5 connected between the signal input terminal and the inverting input terminal of the second operational amplifier; and a second capacitor K5 connected between the signal input terminal and the inverting input terminal of the first operational amplifier. a capacitor K3 , a third capacitor K1 , a fourth capacitor K2 , a fifth capacitor K6 , a sixth capacitor K7 , a seventh capacitor K4 , and the inverting input terminal of the first operational amplifier. a first switching means SW1 for switching between and a common potential point to connect to one end of the third capacitor K1 ;
a second switching means SW2 that switches between the output terminal of the operational amplifier and the common potential point and connects it to the other end of the third capacitor K1 ; and a second switching means SW2 that switches between the signal input terminal and the common potential point and connects it to the other end of the third capacitor K1; a third switching means SW3 connected to the other end of the first operational amplifier, a fourth switching means SW4 connected to the one end of the fourth capacitor K2 by switching the first operational amplifier, the inverting input terminal, and a common potential point; Switching the first operational amplifier, the output terminal, and the common potential point to the fifth point K6
a fifth switching means SW5 connected to one end of the
a sixth switching means SW6 for switching between the inverting input terminal of the second operational amplifier and a common potential point and connecting the same to the other end of the fifth capacitor K6 ; and the common potential with the inverting input terminal of the first operational amplifier.
Seventh switching means SW7 connected to the other end of K7
and eighth switching means SW8 for switching between the inverting input terminal of the first operational amplifier and the common potential to connect it to one end of the sixth capacitor K7 , and switching between the signal input terminal and the common potential point to connect it to one end of the sixth capacitor K7. 7th capacity
Ninth switching means SW9 connected to the other end of K4
and a tenth switching means SW10 for switching between the inverting input terminal of the second operational amplifier and a common potential point and connecting it to one end of the seventh capacitor K4 , wherein all the switching means A set comprising first, second, fourth, fifth, sixth, eighth, ninth and tenth switching means, and third and seventh switching means, which are driven by a two-phase clock. The set consisting of is connected to a common ground point in an opposite phase relationship, and furthermore, the values of capacitances K 1 and K 6 are made equal, and DC
This is characterized by a small offset output voltage.
第３図は、本発明のDCオフセツト量の少い、
SCを用い遅延等化器である。また、第４図はク
ロツク周波数fc≫使用周波数ｆの場合のDCオフ
セツト量に着目したRC等価回路である。 FIG. 3 shows the low DC offset amount of the present invention.
This is a delay equalizer using SC. Furthermore, FIG. 4 shows an RC equivalent circuit focusing on the amount of DC offset when clock frequency fc≫usage frequency f.
はじめに、第３図に示す遅延等化器の構成につ
いて説明する。１，２はそれぞれ積分容量C1及
びC2を備えた第１及び第２の演算増幅器で、こ
れらの非反転入力端子は共通電位点（この場合、
グランド）に接続されている。信号入力端子３と
第２演算増幅器２の反転入力端子との間には容量
K5が接続され、また信号入力端子３と第１演算
増幅器１の反転入力端子との間には容量K3が接
続されている。スイツチSW3は、信号入力端子３
と共通電位点とを切換えて容量K2の一端へ接続
する。スイツチSW4は、容量K2の他端と共通電
位点とを切換えて第１演算増幅器１と反転入力端
子へ接続する。スイツチSW1は、第１演算増幅
器１の反転入力端子と共通電位点とを切換えて容
量K1の端へ接続する。スイツチSW2は、容量K1
の他端と共通電位点とを切換えて第１演算増幅器
１の出力端子へ接続する。スイツチSW8は、第
１演算増幅器１と共通電位点とを切換えて容量
K7へ接続する。スイツチSW9は、信号入力端子
３と共通電位点とを切換えて容量K4の一端へ接
続する。スイツチSW5は、第１演算増幅器の出
力端子と共通電位点とを切換えて容量K6の一端
へ接続する。スイツチSW6は、容量K6の他端と
共通電位点とを切換えて第２演算増幅器２の反転
入力端子へ接続する。スイツチSW10は、容量K4
の他端と共通電位点とを切換えて第２演算増幅器
２の反転入力端子へ接続する。スイツチSW7は
容量K7の他端と共通電位点とを切換えて第２演
算増幅器２と信号出力端子へ接続する。以上説明
したすべてスイツチは２相クロツクで駆動され、
かつ第１、第２、第４、第５、第６、第８、第９
及び第10スイツチングとからなる組と、第３及び
第７スイツチングとからなる組とは逆相関係で共
通電位点へ接続される。 First, the configuration of the delay equalizer shown in FIG. 3 will be explained. 1 and 2 are first and second operational amplifiers equipped with integral capacitances C 1 and C 2 , respectively, and their non-inverting input terminals are connected to a common potential point (in this case,
ground). A capacitor is connected between the signal input terminal 3 and the inverting input terminal of the second operational amplifier 2.
K 5 is connected, and a capacitor K 3 is connected between the signal input terminal 3 and the inverting input terminal of the first operational amplifier 1. Switch SW 3 is signal input terminal 3
and the common potential point and connect it to one end of the capacitor K2 . The switch SW4 switches the other end of the capacitor K2 and the common potential point to connect it to the first operational amplifier 1 and the inverting input terminal. The switch SW1 switches the inverting input terminal of the first operational amplifier 1 and the common potential point to connect it to the end of the capacitor K1 . Switch SW2 has a capacity of K 1
The other end and the common potential point are switched and connected to the output terminal of the first operational amplifier 1. Switch SW8 switches the first operational amplifier 1 and the common potential point to
Connect to K7 . The switch SW9 switches the signal input terminal 3 and the common potential point and connects it to one end of the capacitor K4 . The switch SW5 switches the output terminal of the first operational amplifier and the common potential point and connects it to one end of the capacitor K6 . The switch SW6 switches the other end of the capacitor K6 and the common potential point and connects it to the inverting input terminal of the second operational amplifier 2. Switch SW10 has a capacity of K 4
The other end and the common potential point are switched and connected to the inverting input terminal of the second operational amplifier 2. The switch SW7 switches the other end of the capacitor K7 and the common potential point to connect it to the second operational amplifier 2 and the signal output terminal. All the switches explained above are driven by two-phase clocks,
and 1st, 2nd, 4th, 5th, 6th, 8th, 9th
and the 10th switching, and the set consisting of the 3rd and 7th switching are connected to a common potential point in an opposite phase relationship.
次に、第３図に示す本発明による遅延等化器の
伝達関数T3（z-1）は次式で与えられる。 Next, the transfer function T 3 (z -1 ) of the delay equalizer according to the present invention shown in FIG. 3 is given by the following equation.
T3（z-1）＝−K1K4＋K1K5＋K4＋K5＋K3K6＋（K2K6＋K3K
6−K1K5−K4−2K5）z-1＋K5z-2／（K1＋１）＋（K6K7−
K1−２）z-1＋z-2……（11）
ここで、C1＝C2＝1.0である。T 3 (z -1 ) = −K 1 K 4 +K 1 K 5 +K 4 +K 5 +K 3 K 6 +(K 2 K 6 +K 3 K
6 −K 1 K 5 −K 4 −2K 5 )z -1 +K 5 z -2 / (K 1 +1) + (K 6 K 7 −
K 1 −2)z −1 +z −2 (11) Here, C 1 =C 2 =1.0.
従来技術の場合と同様に、設計パラメータA0、
A1、A2から回路の容量比はK4、K6を任意定数と
して次の様にして求める。 As in the prior art, the design parameters A 0 ,
The capacitance ratio of the circuit is determined from A 1 and A 2 as follows, using K 4 and K 6 as arbitrary constants.
K1＝A0−１ ……（12）
K5＝A0 ……（13）
K6K7＝A0＋A1＋１ ……（14）
K3K6＝（A0−１）K4＋A0 2＋K4−A2
……（15）
K2K6＝A0＋A1＋A2＋K4−A0K4 ……（16）
次に第１図に示すDCオフセツト量について述
べる。第４図に於て、OP−AMP1、２に存在す
るDCオフセツト量の起電圧をEin(1)、Ein(2)、及
びEin(1)、Ein(2)の駆動抵抗をRin(1)、Rin(2)とす
る。従来技術の場合と同様にして、第４図に於
て、出力端子に生ずるDCオフセツト量Vout（０）
とEin(1)、Ein(2)の間の関係を求めると、次の様
になる。 K 1 = A 0 -1 ... (12) K 5 = A 0 ... (13) K 6 K 7 = A 0 + A 1 +1 ... (14) K 3 K 6 = (A 0 -1) K 4 +A 0 2 +K 4 −A 2
...(15) K 2 K 6 =A 0 +A 1 +A 2 +K 4 -A 0 K 4 ...(16) Next, the amount of DC offset shown in FIG. 1 will be described. In Figure 4, the electromotive force of the DC offset amount present in OP-AMP1 and 2 is expressed as Ein(1), Ein(2), and the drive resistance of Ein(1) and Ein(2) is expressed as Rin(1). , Rin(2). In the same manner as in the case of the conventional technology, in Fig. 4, the DC offset amount Vout(0) generated at the output terminal is
The relationship between Ein(1) and Ein(2) is as follows.
Vout（０）＝−R3／Rin(1)Ein(1)＋R2R3／R1Rin(2)Ei
n(2)……（17）
従つて、本発明の遅延等化器のDCオフセツト
量Vout（０）は、式(10)に示す従来技術の場合の
DCオフセツト量Vout（０）に比較して、Ein(1)だ
けではなくEin(2)にも関係し、しかもEni(1)とEni
(2)と異符合で存在することである。即ち、本発明
の遅延等化量のDCオフセツト量が従来技術の場
合に比較して、大巾に小さく出来る可能性があ
る。通常、Eni(1)、Eni(2)、Rin(1)、及びRin(2)は
デバイス技術により決まり、
Ein(1)≒Ein(2)
Rin(1)≒Rin(2) ……（18）
としてもよく、R1＝R2となる様にすれば、DCオ
フセツト量Vout（０）は、
Vout（０）＝０ ……（19）
とすることも可能である。 Vout(0)=- R3 /Rin(1)Ein(1)+ R2R3 / R1Rin ( 2)Ei
n(2)...(17) Therefore, the DC offset amount Vout(0) of the delay equalizer of the present invention is equal to that of the prior art shown in equation (10).
Compared to the DC offset amount Vout(0), it is related not only to Ein(1) but also to Ein(2), and moreover, Eni(1) and Eni
It exists with a different sign from (2). That is, there is a possibility that the DC offset amount of the delay equalization amount of the present invention can be made significantly smaller than that of the prior art. Usually, Eni(1), Eni(2), Rin(1), and Rin(2) are determined by the device technology, and Ein(1)≒Ein(2) Rin(1)≒Rin(2) ……(18 ), and by setting R 1 = R 2 , the DC offset amount Vout (0) can also be set as Vout (0) = 0 (19).
また、第４図の等価抵抗と第３の容量との間に
は、次の関係がある。 Further, the following relationship exists between the equivalent resistance and the third capacitance shown in FIG.
従つて、式（19）の結果は、第３図に於ては次
の様な関係となる。 Therefore, the result of equation (19) has the following relationship in FIG.
K1＝K6 ……（21）
第５図は本発明により遅延等化器の別の構成例
で、第３図に示した遅延等化器と等価である。第
３図と相違する点は、第３図のスイツチSW1及
びSW2による容量K1の切換えは、第５図のスイ
ツチSW2及びSW3が行ない、第３図のスイツチ
SW8の切換えは第５図のスイツチSW2が行ない、
第３図のスイツチSW10は第５のスイツチSW4が
行なう。従つて、第３図に於てはスイツチの総数
が10個であるが、第５図に於ては６個と大巾に減
少させることができる。 K 1 =K 6 (21) FIG. 5 shows another configuration example of a delay equalizer according to the present invention, which is equivalent to the delay equalizer shown in FIG. 3. The difference from FIG. 3 is that the switching of capacitance K1 by switches SW1 and SW2 in FIG. 3 is performed by switches SW2 and SW3 in FIG.
Switching of SW8 is performed by switch SW2 in Figure 5.
The switch SW10 in FIG. 3 is performed by the fifth switch SW4. Therefore, the total number of switches is 10 in FIG. 3, but it can be greatly reduced to 6 in FIG. 5.
（発明の効果）
以上説明したように、本発明によれば、回路自
身から生じるDCオフセツト量の少ない回路構成
の遅延等化器を提供することができる。(Effects of the Invention) As described above, according to the present invention, it is possible to provide a delay equalizer having a circuit configuration in which the amount of DC offset generated from the circuit itself is small.
第１図は従来の遅延等化器の構成例、第２図は
第１図に於てDCオフセツト量に着目した場合の
RC等価回路、第３図は本発明による遅延等化器
の構成例、第４図は第３図に於てDCオフセツト
量に着目した場合のRC等価回路、及び第５図は
本発明により遅延等価器の別の構成例である。
１……第１演算増幅器、２……第２演算増幅
器、３……信号入力端子、４……信号出力端子。
Figure 1 shows an example of the configuration of a conventional delay equalizer, and Figure 2 shows an example of the configuration of a conventional delay equalizer.
RC equivalent circuit, FIG. 3 shows an example of the configuration of a delay equalizer according to the present invention, FIG. 4 shows an RC equivalent circuit when focusing on the amount of DC offset in FIG. 3, and FIG. 5 shows a delay equalizer according to the present invention. This is another configuration example of an equalizer. 1...First operational amplifier, 2...Second operational amplifier, 3...Signal input terminal, 4...Signal output terminal.
Claims (1)
電位点へ接続された第１演算増幅器と、前記積分
容量と同じ容量を備え、且つ非反転入力端子が共
通電位点へ接続された第２演算増幅器と、信号入
力端子と前記第２演算増幅器の反転入力端子との
間に接続された第１容量K5と、信号入力端子と
前記第１演算増幅器の反転入力端子の間に接続さ
れた第２容量K3と、 第３容量K1と、 第４容量K2と、 第５容量K6と、 第６容量K7と、 第７容量K4と、 前記第１演算増幅器の前記反転入力端子と共通
電位点とを切換えて前記第３容量K1の一端へ接
続する第１スイツチング手段SW１と、前記第１
演算増幅器の出力端と共通電位点とを切換えて前
記第３容量K1の他端へ接続する第２スイツチン
グ手段SW２と、前記信号入力端子と共通電位点
とを切換えて前記第４容量K2の他端へ接続する
第３スイツチング手段SW３と、前記第１演算増
幅器と反転入力端子と共通電位点とを切換えて前
記第４容量K2の前記一端へ接続する第４スイツ
チング手段SW４と、前記第１演算増幅器の出力
端子と共通電位点とを切換えて前記第５要領K6
の一端へ接続する第５スイツチング手段SW５
と、前記第２演算増幅器の前記反転入力端子と共
通電位点とを切換えて前記第５容量K6の他端へ
接続する第６スイツチング手段SW６と、前記第
２演算増幅器の出力端子と共通電位点とを切換え
て前記第６容量K7の他端へ接続する第７スイツ
チング手段SW７と、前記第１演算増幅器の前記
反転入力端子と共通電位とを切換えて前記第６容
量K7の一端へ接続する第８スイツチング手段SW
８と、前記信号入力端子と共通電位点とを切換え
て前記第７容量K4の他端へ接続する第９スイツ
チング手段SW９と、前記第２演算増幅器の反転
入力端子と共通電位点とを切換えて前記第７容量
K4の一端へ接続する第10スイツチング手段SW１
０とを備えたものであつて、全ての前記スイツチ
ング手段は２相クロツクで駆動されるものであつ
て且つ、第１、第２、第４第５、第６、第８、第
９及び第10スイツチング手段とからなる組と第３
及び第７スイツチング手段とからなる組とは逆相
関係で共通接地点へ接続し、更に容量K1及びK6
の値を等しくしてDCオフセツト出力電圧を小さ
くしたことを特徴とするスイツチトキヤパシタ形
遅延等化器。 ２ 積分容量を備え、且つ非反転入力端子が共通
電位点へ接続された第１演算増幅器と、前記積分
容量と同じ容量を備え、且つ非反転入力端子が共
通電位点へ接続された第２演算増幅器と、信号入
力端子と前記第２演算増幅器の反転入力端子の間
に接続された第１容量K5と、信号入力端子と前
記第１演算増幅器の反転入力端子の間に接続され
た第２容量K3と、第３容量K2と、第４容量K6
と、前記第３容量の一端と前記第４容量の一端と
の間に直列に接続された第５容量K1と、第６容
量K7と、第７容量K4と、 前記信号入力端子と共通電位点とを切換えて前
記第３容量K2の他端へ接続する第１スイツチン
グ手段SW１と、前記第１演算増幅器の反転入力
端子と共通電位点とを切換えて前記第３容量K2
の前記一端へ接続する第２スイツチング手段SW
２と、前記第１演算増幅器の出力端子と共通電位
点とを切換えて前記第４容量K6の前記一端へ接
続する第３スイツチング手段SW３と、前記第２
演算増幅器の反転入力端子と共通電位点とを切換
えて前記第４容量K6の他端へ接続する第４スイ
ツチング手段SW４と、前記第２演算増幅器の出
力端子と共通電位点とを切換えて前記第６容量
K7の一端へ接続する第５スイツチング手段SW５
と、前記第３容量K2と前記一端と前記第６容量
K7の他端へ接続し、前記信号入力端子と共通電
位点とを切換えて前記第７容量K4の一端へ接続
する第６スイツチング手段SW６と、及び前記第
４容量K6の前記他端と前記第７容量K4の他端へ
接続するものであつて、全ての前記スイツチング
手段は２相クロツクで駆動されるものであつて且
つ第１及び第５スイツチング手段とからなる組と
第２、第３、第４及び第６スイツチング手段とか
らなる組とは逆相関係で共通接地点へ接続し更に
容量K1及びK6を等しくし、DCオフセツト出力電
圧を小さくしたことを特徴とするスイツチトキヤ
パシタ形遅延等化器。[Scope of Claims] 1. A first operational amplifier having an integral capacitor and having a non-inverting input terminal connected to a common potential point; and a first operational amplifier having the same capacitance as the integral capacitor and having a non-inverting input terminal connected to a common potential point. a second operational amplifier connected; a first capacitor K5 connected between the signal input terminal and the inverting input terminal of the second operational amplifier; and a first capacitor K5 connected between the signal input terminal and the inverting input terminal of the first operational amplifier. A second capacitor K3, a third capacitor K1 , a fourth capacitor K2 , a fifth capacitor K6 , a sixth capacitor K7 , a seventh capacitor K4 , and the first capacitor connected between a first switching means SW1 for switching the inverting input terminal of the operational amplifier and a common potential point and connecting it to one end of the third capacitor K1 ;
a second switching means SW2 that switches between the output terminal of the operational amplifier and the common potential point and connects it to the other end of the third capacitor K1 ; and a second switching means SW2 that switches between the signal input terminal and the common potential point and connects it to the other end of the third capacitor K1; a third switching means SW3 connected to the other end of the first operational amplifier, a fourth switching means SW4 connected to the one end of the fourth capacitor K2 by switching between the first operational amplifier, the inverting input terminal, and a common potential point; By switching the output terminal of the first operational amplifier and the common potential point, the fifth point K 6
a fifth switching means SW5 connected to one end;
and a sixth switching means SW6 that switches the inverting input terminal of the second operational amplifier and the common potential point to connect it to the other end of the fifth capacitor K6 , and the output terminal of the second operational amplifier and the common potential point. a seventh switching means SW7 that switches between a common potential and the inverting input terminal of the first operational amplifier and connects the second end of the sixth capacitor K7 to one end of the sixth capacitor K7 ; 8th switching means SW to connect
8, a ninth switching means SW9 for switching between the signal input terminal and the common potential point and connecting it to the other end of the seventh capacitor K4 , and switching between the inverting input terminal of the second operational amplifier and the common potential point. The seventh capacity
10th switching means SW1 connected to one end of K4
0, and all the switching means are driven by a two-phase clock, and the first, second, fourth, fifth, sixth, eighth, ninth and third switching means are driven by a two-phase clock. 10 switching means and a third
and seventh switching means are connected to a common ground point in a reverse phase relationship, and further have capacitances K 1 and K 6
A switched capacitor type delay equalizer characterized in that the values of are made equal to reduce the DC offset output voltage. 2. A first operational amplifier including an integral capacitor and having a non-inverting input terminal connected to a common potential point; and a second operational amplifier having the same capacitance as the integrating capacitor and having a non-inverting input terminal connected to a common potential point. an amplifier, a first capacitor K 5 connected between a signal input terminal and an inverting input terminal of the second operational amplifier, and a second capacitor K 5 connected between a signal input terminal and an inverting input terminal of the first operational amplifier. Capacity K 3 , 3rd capacity K 2 , and 4th capacity K 6
, a fifth capacitor K 1 , a sixth capacitor K 7 , a seventh capacitor K 4 connected in series between one end of the third capacitor and one end of the fourth capacitor, and the signal input terminal. a first switching means SW1 that switches between the common potential point and the other end of the third capacitor K 2 ; and a first switching means SW1 that switches between the inverting input terminal of the first operational amplifier and the common potential point to connect the third capacitor K 2 to the other end of the third capacitor K 2 .
a second switching means SW connected to the one end of the
2, a third switching means SW3 for switching the output terminal of the first operational amplifier and a common potential point and connecting it to the one end of the fourth capacitor K6 ;
A fourth switching means SW4 switches between the inverting input terminal of the operational amplifier and the common potential point to connect it to the other end of the fourth capacitor K6 , and switches between the output terminal of the second operational amplifier and the common potential point to 6th capacity
Fifth switching means SW5 connected to one end of K7
, the third capacitor K 2 , the one end, and the sixth capacitor
a sixth switching means SW6 connected to the other end of the seventh capacitor K 7 and switching between the signal input terminal and the common potential point to connect to one end of the seventh capacitor K 4 ; and the other end of the fourth capacitor K 6 and the other end of the seventh capacitor K4 , and all of the switching means are driven by a two-phase clock, and a set consisting of first and fifth switching means and a second , the set consisting of the third, fourth, and sixth switching means are connected to a common ground point in an opposite phase relationship, and further, the capacitances K 1 and K 6 are made equal, and the DC offset output voltage is reduced. Switch capacitor type delay equalizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10918683A JPS601915A (en) | 1983-06-20 | 1983-06-20 | Switched capacitor-type delay equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10918683A JPS601915A (en) | 1983-06-20 | 1983-06-20 | Switched capacitor-type delay equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS601915A JPS601915A (en) | 1985-01-08 |
| JPH0446007B2 true JPH0446007B2 (en) | 1992-07-28 |
Family
ID=14503815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10918683A Granted JPS601915A (en) | 1983-06-20 | 1983-06-20 | Switched capacitor-type delay equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601915A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11671064B2 (en) * | 2020-01-07 | 2023-06-06 | Qorvo Us, Inc. | Equalizer for envelope power supply circuitry |
| US11677365B2 (en) | 2020-01-08 | 2023-06-13 | Qorvo Us, Inc. | Envelope tracking power management apparatus incorporating multiple power amplifiers |
| US11545945B2 (en) | 2020-03-04 | 2023-01-03 | Qorvo Us, Inc. | Apparatus and method for calibrating an envelope tracking lookup table |
| US11626844B2 (en) | 2020-03-09 | 2023-04-11 | Qorvo Us, Inc. | Envelope tracking radio frequency front-end circuit |
-
1983
- 1983-06-20 JP JP10918683A patent/JPS601915A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| SWITCHED-CAPACITER FILTER DESIGN USING CASCADED SECTION=1980 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS601915A (en) | 1985-01-08 |
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