JPS6064616U - frequency multiplier - Google Patents

frequency multiplier

Info

Publication number
JPS6064616U
JPS6064616U JP15551083U JP15551083U JPS6064616U JP S6064616 U JPS6064616 U JP S6064616U JP 15551083 U JP15551083 U JP 15551083U JP 15551083 U JP15551083 U JP 15551083U JP S6064616 U JPS6064616 U JP S6064616U
Authority
JP
Japan
Prior art keywords
frequency multiplier
frequency
input signal
pulse wave
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15551083U
Other languages
Japanese (ja)
Inventor
杉本 悦夫
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP15551083U priority Critical patent/JPS6064616U/en
Publication of JPS6064616U publication Critical patent/JPS6064616U/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の周波数逓倍器を概略的に示す回路図、
第2図は、この発明の1実施例を示すブロック線図、第
3図はこの考案の動作牽説明するための波形図で弗る。 図において、1は入力端子、2は入力リターン端子、8
は出力端子、9は出力リターン端子、10はパルス整形
回路、11は帯域フィルタである。図中同一符号は、同
−或は相当部分を示す。
FIG. 1 is a circuit diagram schematically showing a conventional frequency multiplier;
FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of this invention. In the figure, 1 is an input terminal, 2 is an input return terminal, and 8
9 is an output terminal, 9 is an output return terminal, 10 is a pulse shaping circuit, and 11 is a bandpass filter. The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号周波数の奇数倍の所要周波数信号を取゛   
−出す周波数逓倍器において、入力信号をパルス波に整
形す予パルス整形回路と、この回路の出力パルス波から
上記所要周波数成分のみを通過させるフィルタとを備え
てなる周波数逓倍器。
Get the desired frequency signal that is an odd multiple of the input signal frequency.
- A frequency multiplier comprising a pre-pulse shaping circuit that shapes an input signal into a pulse wave, and a filter that passes only the required frequency component from the output pulse wave of this circuit.
JP15551083U 1983-10-06 1983-10-06 frequency multiplier Pending JPS6064616U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15551083U JPS6064616U (en) 1983-10-06 1983-10-06 frequency multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15551083U JPS6064616U (en) 1983-10-06 1983-10-06 frequency multiplier

Publications (1)

Publication Number Publication Date
JPS6064616U true JPS6064616U (en) 1985-05-08

Family

ID=30343439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15551083U Pending JPS6064616U (en) 1983-10-06 1983-10-06 frequency multiplier

Country Status (1)

Country Link
JP (1) JPS6064616U (en)

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