JPS6063683A - Switched capacitor multiplier circuit - Google Patents

Abstract

PURPOSE:To obtain a high-precision arithmetic result by eliminating an error due to a feedthrough and an error due to the offset of an amplifier by a combinational logical circuit which generates driving signals for the 1st - the 4th analog switches. CONSTITUTION:When data applied to a data input terminal 2 is ''+1'', switches 8-5 and 8-8 are turned on to fetch an analog signal applied to an input terminal 1 in a capacitor 10 temporarily. Then switches 8-6 and 8-7 are turned on to charge an output capacitor 11. When the data is ''-1'', the switches 8-6 and 8-7 are turned on directly to charge the output capacitor 11 through the input capacitor 10. When the data is ''0'', the switches 8-6 and 8-8 are turned on firstly to reset the charge in the input capacitor 10, and then the switches 8-6 and 8-7 are turned on to perform transfer to the output capacitor 11.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a switched capacitor multiplier circuit, and particularly to a switched capacitor multiplier circuit in which an analog signal is applied to one input, a multilevel signal is applied to the other input, and the multiplier circuit is a switched capacitor circuit. The present invention relates to a constructed two-manpower multiplication circuit.

[Background of the invention]

One of the conventionally used multipliers is one that utilizes the nonlinear characteristics of transistors and the like.

For example, the drain voltage VD1. of a MOS transistor operating in the triode region. Gate voltage V. There is a relationship between D10 and the drain current D10. Here B1. vthl is a constant determined by the MOS transistor. Now, ■, 1. ■ Considering D1 as two analog inputs, the gate voltage V of another MOS transistor with similar characteristics. 2-〇 and VD□
-VDl. Here, B1= B2 Vtht: Vthz
Then, the difference between 1 and ID2 is V as shown below. 1・V
Proportional to the product of Dl, an analog multiplier is realized.

However, this multiplier cannot completely eliminate output errors due to variations in nonlinear elements or nonlinear errors that depend on the input signal amplitude, and therefore cannot perform highly accurate calculations.

Another example of a conventional multiplier is a multiplier using switched capacitors.

FIG. 1 is a block diagram of a conventional switched capacitor multiplier.

In FIG. 1, 6 is a decoder, 12 is an operational amplifier, and 8
-1 to 8-4 are switches composed of MOS FET T, 7-1 to 7-2 are AND gates, 9 is an inverting amplifier, 10.11 is a capacitor, and 3 is an OR gate.

The analog signal applied to the input terminal l can be passed directly through the switch 8-1 or through the inverting amplifier 9 and the switch 8.
-2 to the input capacitor 10.

A two-phase clock signal is applied from the input terminal δ, 4, which determines the switch take-in timing, and this two-phase clock has the same period as the multiplication period and does not overlap with each other at high level. This is a non-overlapping clock.

The operating time of the switches δ-1 and 8-2 is determined by the clock applied to the input terminal 4 and the AND gates 7-1 and 7-2.
are opened at the same time, so the switch operations are also synchronous.

Subsequently, the clock applied to the input terminal δ turns on the switch 8-3, so that the charge accumulated in the capacitor 10 is transferred via the operational amplifier 12 to the output capacitor, which has been reset by the switch 8-4 in advance. It is accumulated in the size 11. That is, the output capacitor 11 has a voltage ■ expressed as Vo−V□X(±C1/C2) ””・(1). ut is accumulated and the value is output to the output terminal convex. In the above formula (○), C is the capacitance of the human-powered capacitor 10, and C2 is the capacitance of the output capacitor 11. Therefore, by setting C□-C2, the circuit of FIG. 1 operates as a multiplier of analog signal and data (+1). Three-value data (ie, 1.-1.O) is input to the input terminal 2, and one of the data to be multiplied by the analog input signal is designated. These δ value data are converted into +1", "-1", and "O" by the decoder 6, and when it is +1", the AND gate 7-2 is opened and the input capacitor 10 is multiplied by the analog input signal and "+1". When the value is "-1", the AND gate) 7-1 is opened and the input capacitor IOK is connected to the analog input signal and -1'.
Stores a charge equal to the value multiplied by ''.

Also, when the ternary data is “O”, the OR gate 1
3 is opened and the reset switch 8-4 is turned on, the output capacitor 11 is discharged and the output terminal 5 is turned on.
outputs ground potential.

The first problem with the multiplication circuit of FIG. 1 is that the switch 8
-1 to 8-4 turn on, the error due to the feedthrough of the busy Ptsk is "O" when the data is '±1'
The difference is that when , high-precision multiplication is impossible.

FIG. 2 is a diagram explaining the problem of FIG. 1.

For example, considering the feedthrough of switch 8-3, as shown in Figure 1, when the data is 0'', switch 8-3 is on, flQyυ set, and switch 8-4 is on. Therefore, there is no error due to feedthrough. That is, the product of the analog input signal voltage Ve and 0" is positive iK"0". Next, the Tosa K whose data is “+1” is as shown in Figure 2 (→).
Since the reset switch 8-4 is in the OFF state, the charge accumulated in the capacitor 10 is charged to the output capacitor 11 by an error corresponding to the feed "through". Therefore, when the data capacitance is +1", the output terminal 5 The multiplication result obtained is 1×(+1)+ΔV. Here, Δ
■ is the error voltage due to feedthrough. Next, when the data is "=1", as shown in FIG. 2(b)K,
Since the reset switch 8-4 is still in the off state, the charge accumulated in the capacitor 10 through the inverting amplifier 9 is charged with an error corresponding to the feedthrough in the output capacitor 11, and the output terminal 5 has V, X( -1) 10ΔV
The multiplication result is obtained.

The principle of feedthrough is as shown in Figure 2 (Q).
Since a floating capacitor C8 is added to switch 8-3, 8-1, etc., the data of switch 8-3゜8-1)
K1 every time the pulse shown in (a) in Figure 2 (d) is added.
Charge flows in by the amount of crosstalk caused by the floating capacitor C8, and as shown in (b) of FIG. 2(d),
This is based on the fact that K increases steadily. Furthermore, errors caused by the offset voltage of the inverting amplifier 9 also reduce the accuracy of the counter.

If these error voltages Δ■ are always constant regardless of the data, they can be easily canceled as the offset 'gisho' of the operational amplifier 112, but in the L path of FIG.
As explained in the figure, since the amount to be canceled differs from data to data, it is extremely difficult to remove this error.

[Purpose of the invention]

An object of the present invention is to improve upon such conventional problems and eliminate errors caused by feedthrough and amplifier offset caused by the value of the multi-value signal when taking the product of an analog signal and a multi-value signal. Another object of the present invention is to provide a switched capacitor multiplication circuit that can obtain highly accurate calculation results.

[Summary of the invention]

In order to achieve the above object, the switched capacitor multiplier circuit of the present invention operates according to multi-value data and two-phase clock.
Driving an analog switch of M1 to store an analog signal in an input capacitor, driving a second analog switch to transfer the stored signal to an output capacitor attached to an operational amplifier, and outputting the signal. In the switched capacitor multiplier circuit, a third. It has a fourth analog switch and a combinational logic circuit that creates drive signals for the multi-level 31 to fourth analog switches from multi-value data and a two-phase clock, and when multi-value data number i'''O'' Also, after discharging to the earth potential of the human capacitor, it is characterized in that it is output at the same timing as when the multi-value data is other than ``0''''.

[Embodiments of the invention]

FIG. 3 is a configuration diagram of a switched capacitor multiplication circuit showing one embodiment of the present invention, and FIG. 4 is an operation time chart in FIG. 3.

In FIG. 6, 7 is a combinational logic circuit, 6 is a decoder, 12 is an operational amplifier, and 8-4 to 8-8 are MOSFETs.
10.11 is a capacitor.

In the multiplier circuit shown in FIG.
Errors due to offset are also excluded. Also, the combinational logic circuit 7 generates data (+1.-1.O'
) is the time for operating switches 8-5, 8-6 φ□1.
φ12 to control charging and discharging of the analog input signal to the human-powered capacitor 10.

First, when the data applied to the data input terminal 2 is "+1", the analog signal applied to the input terminal IK is
The switch 8-5.8-8 is turned on, and the voltage is once taken into the input capacitor 10, and then the switch 8-6, 8-7 is turned on, and the output capacitor 11 is charged. Next, when the data is °-1'', switch directly to switch 5-5.8-7.
turns on, and the output capacitor IC is charged through the input capacitor] and O. Finally, when the data is "0", the switches 8-6.
8-7 is turned on and the output capacitor 11tC is transferred.

In this manner, the multiplication circuit shown in FIG. 3 performs the following calculation.

Vo-V, The capacitance value is 11. In the above formula ■, C□−C2 and fi? t, this example uses analog signals and ternary data.
It operates as a (+1.-1.O) multiplier.

In the time chart shown in FIG. 4, φ. 1. φ. 2
are non-overlapping two-phase clocks with a frequency equal to nFM degrees, and these clocks are respectively applied to the input terminals 3°. Further, X and Y are 2-bit digital signals encoded according to a ternary signal, which are applied to the input terminal 2.

There are no particular restrictions on the encoding rules for the digital signals X and Y, but in the case of this implementation, the decoder 6' shown in FIG. , When the ternary signal is “-1”, the ternary signal is °゛○
'', X-Y-OK conversion is performed.

Also, φ. 0. φo2,
-6 drive signal φ, 1. Converted to φ1□. The logical formula of the combinational logic circuit γ is as follows.

Ritatsuku φIilφ□2 is analog switch 8-.
5. Drive 8-6. For example, when X-1, Y-0 (that is, the three-value signal U corresponds to '+1''), switch 8-5 is the assistant of the clock cycle, and switch 8-6 is the second half of the clock cycle.
are respectively turned on, and the human capacitor 10 is charged with a charge Q of the following value, assuming that the analog input voltage is Vl.

Q ” CI Vl ... (4) This charge Q is
Next ζ (analog switch 8-6°8-7 is turned on,
The signal is transferred to the output capacitor 11 and appears at the output terminal 5. If the output voltage of output terminal 5 is C, /C2-1, then
The output voltage V0 is the analog signal V, and the ternary data ゛°+
K is the result of multiplication by "1". Similarly, when the ternary signal is -1" or "0", the output voltage is V.

are as follows:

The above equations (υ, (6), (7) are when the error due to clock feed-through is ignored, but when this error is included, equations (5), (6), C7) become 'c
7t (j t't, '6C-AC8>, (9),
C0).

■o/. ” O + i mino ・-yama (10) upper expression (phrase ~ C
Δ■ in LO) is the calculated rA difference due to clock feed through.

■ Shown in Figure 4. For example, it shows the output voltage value when the human input analog signal 1 changes as shown by the thick line in FIG.

FIG. 5, FIG. 6, and FIG. 7 are diagrams showing the states of the input capacitors in FIG. 3, and both equations (5) and (9)
, αO) due to clock feed-through, all values are less than -, as shown in Figures 5 to 5.
This will be explained with reference to FIG.

FIG. 5 (&) shows φ when the ternary data is +1°'. 2
This is an equivalent circuit of input capacitor 10 and analog switch 8-5, 8-8 when turned on. That is, φ. 2 is on, the gate voltage of the switches 8-5°δ-8 and 8-4 is at a high level, so the input capacitor 1o
The jlii! The switches 8-5, 8-8 are turned on, and the left electrode of the capacitor 1o is connected to a low impedance, and the right lower electrode is connected to the ground potential. In FIGS. 5 to 7, black arrows i: are connected to low impedance and white arrows are connected to high impedance, respectively.

Next, FIG. 5(b) shows φ. 1 indicates an on state, the lower electrode on the left side of the capacitor lO has a low impedance, and the upper electrode on the right side is connected to the input of the operational amplifier 1m 12. That is, φ. , when K is on, the gate voltages of analog switches 8-6 and 8-7 are at high level, so both switches 8-6 and 8-7 are on and the fifth figure)
The state will be as follows.

Roughly speaking, the fifth TE01 (o) is φ. This shows the moment when 1 is turned off, which is φ. Until 2 turns on,
Both electrodes of capacitor 100 are open. That is, φ.

1゜φ. At the moment when 2 is off, no analog switch is on, so the capacitor 10 has no circuit to charge or discharge charge.

FIG. 6(a) shows φ when the ternary data is "-1". 2
This is an equivalent circuit of input capacitor 10 and analog switch 8-6, 8-8 when turned on. That is, when do2 is on, the gate voltage of switch 8-6.8-δ is at a high level, so both sides of input capacitor 10'
The tail pole is connected to low impedance, that is, to ground voltage, with the edges 8-(5, 3-8 turned on).

Next, in FIG. 6(b), φ0. When turned on, the analog switches 8-5 and 8-7 are turned on, so the left-open upper 1u pole of the capacitor IO is connected to low impedance, and the right-hand upper electrode is connected to the input of the operational amplifier 12. Do 1.

Moreover, in FIG. 6(c), φ. 1. When φo2 is (), no analog switch is turned on and both electrodes of capacitor IQ are opened.

The 71st z (λ) is the input capacitor 10 and analog switch 8 when φ.2 is on when the ternary data is O''.
-0.8-8 equivalent circuit. φ. 2 is on, the analog switches 8-6, 8-8 are on, so both electrodes on both sides of the capacitor 100 are connected to low impedance, that is, to ground potential. Figure 7(b) shows φ
. 1 is on, and at this time switch 8-6
．． 8-7 is turned on, the lower electrode on the left side of the capacitor 10 is connected to a low impedance, and the upper electrode on the right side is connected to the input of the operational amplifier 12. FIG. 7(0) shows φ. 1.
φ. 2 are in an off state, and both switches are off, so both electrodes of the capacitor 10 are open.

Above, Figures 5 to 7 show ternary data (+1.-1°0)
As is clear from these figures,
The equivalent circuit for any value of ternary data is represented by exactly the same circuit. From this, it can be seen that the amount of charge flowing out due to clock feed-through is constant regardless of the ternary data. Since these charges can be considered as offset voltages of the operational amplifier 12, calculation errors due to feedthrough can be easily removed.

FIG. 8 is a sweep diagram of a switched capacitor calculation circuit showing another embodiment of the present invention.

FIG. 8 shows a product-sum circuit, in which the logic section, input capacitors, and analog switches of the embodiment circuit shown in FIG. 3 are arranged in parallel (N in the figure), and N analog This is a circuit that calculates the sum of products of a signal and N ternary signals.

As shown in FIG. 8, analog switch 8-1.8-
2.8-3, output capacitor 11 and operational amplifier 12
can be shared by a plurality of multiplier circuits 7-1 to 7-N, and the input capacitors 10-1 to 10 of waits
-NK Since the charged charges can be added by wired-OR logic, the number of circuits and parts used can be reduced.

Also, in the circuit of FIG. 8, all clock feed throughs are the same as in the circuit of FIG. 3, so adding the offset canceling circuit 15 cancels out the error. Therefore, a highly accurate product-sum circuit can be realized.

Various circuits are known as the offset cancellation circuit 15, but the simplest circuit is an operational amplifier 1.
There is a type that only applies a DC voltage to the 20 input terminal in advance to cancel out the input conversion offset voltage ΔV. This DC voltage may be one in which a variable resistor is connected between the DC power supply voltage and ground.

In this way, in each of the circuits of the embodiments shown in FIG. 1 and FIG. 8, there is a constant feedthrough that does not depend on data, and this cancellation becomes easy. In addition, since the inverting amplifier used in conventional circuits is not used, there is no error caused by this offset, and since all capacitors are of a stray-free type, errors caused by stray capacitance added to switches, wiring, etc. will not occur.

As described in detail, according to the present invention, when taking the product of an analog signal and a multi-value signal, it is possible to eliminate errors due to feedthrough caused by the values of the multi-value signal and errors due to amplifier offset. Therefore, highly accurate multiplication results can be obtained.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional switched capacitor multiplier.
2 is a diagram explaining the problems in FIG. 1, FIG. 3 is a configuration diagram of a switched capacitor multiplier circuit showing an embodiment of the present invention, FIG. 4 is an operation time chart of FIG. 3, and FIG.
6 and 7 are equivalent circuit diagrams showing the states of the input capacitors in FIG. 5, respectively, and FIG. 8 is a configuration diagram of a switched capacitor product-sum circuit showing another embodiment of the present invention. 1: Analog signal input terminal, 2: Multi-value data input terminal,
3, 4: Input terminal for two-phase overlap/rep-tuk, 5
: Output terminal, 6; Decoder, 7th combinational logic circuit,
8-1 to 8 to 8: analog switch, 9: inverting amplifier, 10: input capacitor, 11: output capacitor, 12
; Operational amplifier, ■3: Inverter, 15: Offset
cancellation circuit. Figure 2 (c) (d) Figure 3 Figure 4 Figure 5 (a) (b) (c) Figure 6 (a) (b) (C) Figure 7

Claims (1)

[Claims] ■According to a multi-value data clock, a first analog switch is driven to store an analog signal in an input capacitor;
In a switched capacitor multiplication circuit that transfers the stored signal to an output capacitor attached to the operational amplifier via a second analog switch and outputs the signal, both electrodes of the input capacitor are connected to ground potential. Third
．． It has a fourth analog switch and a combinational logic circuit that creates drive signals for the first to fourth analog switches from multi-value data and a clock, and the multi-value data is
A switched capacitor multiplier circuit characterized in that, even when the input capacitor is 0'', after discharging the input capacitor to the ground potential, the multi-value data is output at the same timing as when the multi-value data is other than 0.''. e) The combinational logic circuit drives the third and fourth analog switches to discharge the input capacitor to the ground potential even when the multi-value data is 0'', so that the multi-value data is 0''.
The second Anamag switch is driven at the same timing as in the case other than 0', and the signal stored in the input capacitor is outputted via the output capacitor. Switched capacitor multiplier circuit. (3) the combinational logic circuit, the input capacitor and the first . A plurality of third analog switches are arranged in parallel, and the second... fourth analog switch,
3. The switched capacitor multiplier circuit according to claim 1, wherein an operational amplifier and an output capacitor are commonly connected to the plurality of parts. (The phrase said operational amplifier and output capacitor are offset
Claim 1 characterized in that by adding a canceling circuit, an error based on feedthrough, which remains constant regardless of multi-value data, is canceled.
The switched capacitor multiplier circuit according to item 1, 2 or 3.