JPS6063652A - Channel buffer control system - Google Patents

Abstract

PURPOSE:To control efficiently a channel buffer by identifying the kind of a channel on the way of accessing a memory and controlling the channel buffer. CONSTITUTION:A main storage control part 4 incorporates the channel buffer 41. The interface from a channel processor 3 to the main storage control part 4 is provided with a flag. The main storage part 4 recognizes this flag to identify the kind of a channel which attains to memory access, and laters the control over the channel buffer 41. When memory access is attained from a multiplexer channel, that is registered in the channel buffer 41 regardless of whether the access is fetch or store to inhibit writing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION fal Technical Field of the Invention The present invention relates to a channel buffer control method in a data processing system that includes a channel buffer in a main memory control unit.

Background of the Technology With the recent trend toward larger and faster data processing systems, input/output devices connected to the data processing systems are also becoming faster.

In order to cope with the trend toward higher speeds of input/output devices (i.e., to improve channel throughput and prevent overruns in input/output devices), channel buffers are installed in the main memory control unit located between the main memory and the channels. A known method is to increase the memory access speed seen from the channel.

Channels include multiplexer channels to which mainly low-speed input/output devices are connected, and block multiplexer channels and select channels to which mainly high-speed input/output devices are connected. For multiplexer channels that only transfer data, there is a problem in that the function of the channel buffer is not fully utilized, and it has been desired to study a channel buffer control system suitable for the three types of channels mentioned above.

(C1 Prior Art and Problems Generally, channels include a block multiplexer channel (hereinafter referred to as BMC) and a selector channel (hereinafter referred to as S).
(hereinafter referred to as LC) and multiplexer channel (hereinafter referred to as MX).
There are three types (referred to as C).

From the viewpoint of the main memory control unit (hereinafter referred to as MCU), in the case of B) IC and SLC, there is a characteristic that read data and write data are transferred as a unit during a read or write operation. In the case of MMC, read and write operations are mixed, and data is transferred in units of 8 bytes.

The above MCU has a channel buffer (hereinafter referred to as CI (B))
Due to the characteristics of the CHB, in a data processing system incorporating the CHB, it is difficult to process the transfer data from the 3N type channels equally, which poses the following problems in terms of efficient use of the CHB. That is: ■Decrease in efficiency of use of CHB; In memory access from MXC, read and write are mixed, and the address is not continuous, but is accessed in units of 8 hides, so when using CIIB, MXC In response to a memory access request from C) I
Even if the relevant data does not exist in B, and one 64-byte block is prepared from the main memory (hereinafter referred to as MSU), only the above 8 notes will be used, and the remaining 56 bytes will be used in most cases. You will end up being thrown away.

■ Decrease in the efficiency of memory access from the central processing unit: When accessing CH[l from MXC and the corresponding data block does not exist in CIIB, accessing MSII and performing transfer, normally 8-byte access is required. A certain place is accessed in blocks of 64 hides, so
Since the interleaving unit of the MSU corresponding to the 64 bytes becomes busy and cannot be accessed during the access time of MS[+, there is a problem that the efficiency of memory access from the central processing unit is reduced. .

(d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides that, in a data processing system in which a channel buffer is built in the main memory controller, when memory access is performed from the channel processor to the main memory controller, the access request signal is A flag that specifies the type of memory access is added to the memory access, and the main memory control unit uses the flag to identify the type of channel that is accessing the memory and uses the channel buffer. The purpose is to provide a method for controlling

fe) Structure and object of the invention According to the invention, between the main memory, the central processing unit and the channel processor,
A data processing system comprising a main memory control unit that performs memory control, and in which the main memory control unit has a built-in channel buffer, wherein a flag is provided in the address interface to the main memory control unit, and the flag is This is achieved by providing a method for the storage controller to recognize and identify the type of channel that performs memory access, and to change control over the channel buffer depending on the type of channel.
In the case of memory access from a channel, the channel buffer is controlled not to be used, so there is an advantage that the channel buffer can be controlled efficiently.

ff) Embodiments of the invention First, to summarize the gist of the present invention, in the present invention,
In a data processing system that includes a channel buffer in the main memory control unit, when a channel processor accesses the main memory control unit, a flag specifying the type of channel for the memory access is included in the access request signal. In addition, when memory access is performed, the main memory control fa11 identifies the type of channel to be accessed using the flag, and controls the channel buffer. For example, if the flag is a multiplexer channel (MMC), In the case of a fetch request, control is performed to perform an 8-hide memory fetch and transfer the fetched data directly to the channel processor without registering it in the channel buffer, and in the case of a store request. Also, the control is such that 8-byte data is written directly to the main memory without writing to the channel buffer.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a data processing system to which the present invention is applied, and FIG. 2 is a diagram showing a channel buffer (CH
FIG. 3 is a block diagram showing an example of the configuration of the channel buffer (CFIB); FIG. 3 is a diagram showing an example of the configuration of the tag section of the channel buffer (CFIB).

In FIG. 1, 1 is the main storage unit (MSU), 2
3 is the central processing unit (hereinafter referred to as CPU), 3 is the channel processor (hereinafter referred to as CHP), and 1 CHP has 1 unit.
Six channels are connected. 4 is the main memory control unit (
MCU > and channel buffer (CIIB > 41
Built-in. And the CI (B is 2-way (64
(byte/way), and two ways are allocated to each channel.

First, before explaining the general operation of the CHB 41, the tag section of the CHB 41 will be explained with reference to FIG.

The tag part of C) IB 41 related to the present invention is the control part (C
TRL) and an address section (ADDR).

Since the transfer unit for C) IB 41 is 64 bytes, the address part CADDR) consists of address 4 to 25 bits and its parity -PO to P3.

The control unit (CTRL) is composed of the elements shown below. That is: V: Valid bit indicating the validity of the block.

F: FIR3T IN bit indicating whether the block is new or old. and: F-1: New (indicates recently registered).

F-0: Old, subject to move-out/replacement. Normally, when the value changes to 1-=60, if C=1 (described later), it is placed in the move-out queue.

C: Indicates that the block is stored from CIIP 3. Logically, it is a logical sum signal of BMO to BM7, which will be described later.

Pv: Parity bit for the above V, F, and C bits.

BMO-8M7: Byte marks for each 8 bytes of a 64-byte block, and when each focus is on,
This indicates that all 8 bytes corresponding to each have been written.

PB: Parity beat 7 for BMO to BM7.

In this embodiment, the tag part is COP O/1 (3
) and for each channel, 32 per way.
It is composed of two ways of lines (that is, 16 channels XZCHP).

Therefore, the CUB 41 is accessed by the CHP number and channel number.

The outline of the memory access operation from the CHP 3 will be explained below with reference to FIGS. 1, 2, and 3.

In Figure 2, 5 is the CHP address register (CHP
AR), 51 is a flag register (F) that identifies the type of channel necessary for implementing the present invention, 6 is a channel identification register (CHIDR), 61 is a CHP number identification section, and 62 is a +1 circuit which is a tag section of a channel buffer. (
CIIB TAG ) and the data portion (CHn I) AT^) of the channel buffer.

70.71 is the channel buffer tag section (hereinafter referred to as CIIBT).
(referred to as AG) and indicate way O and way 1, respectively. 80.81 is a comparison circuit (C) provided corresponding to each way, and the CIIP address register (CIIPA
The contents of R) 5 and the address part CADDR) of CHB TAG 70, 71 are compared in focus correspondence, and if they match, a match signal MCII 1 is output. 9 is a converter, which outputs logic "1" when the match signal MCH00, and the match output M
When it is CH1, logic "0" is output. 10 is a CIIB address register (CIIBAR), and 101 is a coincidence way number register (CWNR), in which the output of the converter 9 is set.

11 is the data section of the channel buffer (hereinafter COB DA
12 is the CHB data register (CI(B)
DR).

13 is the CIIP store data register (CHPSTDR
), 14°15, CI (I' fetch data register (CIIPFCHDR).

Now, when a memory access is performed from Cl1P3 to MSU 1, the CIIP address register (CHPAR
) 5, the channel identification register (CRTDR) 6 contains the channel number that accessed the memory, and the CHP number identification section 61 contains the CI to which the channel is connected (P number is sent). Ru.

Then, using the contents of the channel identification register (CHIDR) 6 and CHP number identification section 61 as an address, C11
B TAG 70, 71 is accessed, its address part (ADDR) is read, and the comparison circuit (C) 80
．． 81, the CHP address registrar ((:1IP
AR) The contents of 5 are compared.

According to the above comparison results, control is performed as follows. That is; ■In the case of fetch access from CHP: 1) If any of the match outputs MCll0.1 is obtained, the output signal is converted to 110 by the converter 9 and sent to the match way number register (CWNI?) 101. At the same time, the contents of the channel identification register (C old DR') 6 and the CHP number identification section 61 are
BAI? ) is set to 10, and C) IB DATA 11 of Cll841 is accessed using the contents of CI (B address register (C) IBIIR) 10 and the contents of match way number register (CWNR) 101 as an address, and the read output data is is set in one of the CHP fetch data registers (CHPFCHDR) 14 and 15, and the fetch data is sent to the CHP 3.

2) In case of mismatch: Since there was no data to be fetched in COB 41, it is necessary to move in from MSU 1 to Cll 841. However, the control section of COB TAG (C
The move-in operation differs depending on the contents of the TRL).

r V = 1.1 and C = 1.1 In this case, both ways 0 and 1 are v = 1 and C = 1, so F
After moving out the data in the way on the =0 (that is, old data) side to MStl 1, the data block at the address from MSU 1 is moved in to the same way, and the move-in data is bypassed (however, , the first 8 bytes] data only) and the CIIP
Sent on 3rd.

(Hereinafter, the meaning of bypass is the same.) When rV is 1.1 and C≠1,1. In this case, the V bit is 1 in both ways 0 and 1, but
Regarding the C bit, since either way 0 or 1 is 0, it is moved in to the C=001110 way, the move-in data is bypassed, and the CHP is
Sent on 3rd.

"When V≠1.1" In this case, since the V bit of one of the ways is O, the move-in data is moved into the way on the -θ side, the move-in data is bypassed, and the data is transferred to the C1 (P3). Sent out.

If the fetch data is not pure data, such as a command address word (CAM) or a channel command word (C(J)), fetch access is performed with the highest priority, and the fetch data (8-byte data) is bypassed. Direct CI
Sent to IP 3. That is, no move-in operation is performed for CI(B41).

Note that the F bit of the control unit (CTRL) of the COB TAG 70 is updated at the time of move-in.

■CI (in the case of store access from P: l) If a matching output is obtained: For the C=O way, the channel identification register (C
Using the contents of IIIDR) 6 and CHP number identification section 61 as addresses, accesses CI(B TACTo, 71 to set C=1, and stores the store data previously stored in COB data register (CIIflDI+) 12. ClIn address register (C) IBAR) obtained by the method explained at the time of Sochi access
10 and matching way number register (CIINR) 101
CIIB I of Cll841 with the contents of
Access IATA 11 and store in the block.

For the way with C=1, store data is stored in that block.

2) In case of mismatch: When rV = 1, 1 and C = 1, 1, read the data of the F = O side way to the CUP store data register (CIIPSTDR) 13 times, MSIJ
After moving out to 1, write store data to the same way.

At this time, the F bit of the corresponding way is set to logic "1", and the F bit of the other way is set to logic "0".

That is, the F bit is updated.

When rV=1.1 and C≠1,1, write store data to either way where C=0, set the F bit of the way to logic '1',
The other is set to logic "0".

"When V≠I+1 and C=1" ■Write the store data to the −θ side way.

The data on the C=1 side is registered in the moveout key, and the data on the F
Update bits.

"When V≠1,1 and C=O" Write store data to way V = 0111J and update the F bit.

The operation of memory access from COP 3 has been explained above, but when the present invention is implemented, C) DATA (hereinafter referred to as "hereinafter") and PRIOI? ITY (hereinafter referred to as P)
C) The MCU 4 identifies the M type of the channel that is accessing memory from the IP 3 by looking at the two flag bits P, and performs memory access operations corresponding to the type. controlled to do so.

In the following, the operation of the CUB 41 from JIP 3 when the present invention is implemented will be described.

First, the basic meanings of the flags D and P will be explained.

D=1: Indicates continuous data transfer.

D-0: Indicates data transfer in units of 8 bytes, and includes command address words (hereinafter referred to as CAW), channel command words (hereinafter referred to as CC-), and dynamic address conversion (hereinafter referred to as DA).
(called T) table fetch.

Channel status word (hereinafter referred to as C5-) store.

This also applies to memory accesses (fetch, store) from MXC related to the present invention.

P=1: Indicates that an access request is issued to the main storage device 1 with the highest priority.

P=0: Indicates that an access request is issued to the main storage device 1 with normal priority.

In the present invention, the following state is defined by combining the above two bits, P and P.

(11rD, P=O, O case) Indicates that the data section memory access is from MXC.

[21rD, P = 0.1] C static, CIJ, DAT table fetch, C or store memory access (MXC, BMC, SIC
”).

+31rD, P=1. "O" indicates that the data section memory access is from a source other than the MXC (ie, B?IC, SLC').

(41rD, when P=1.1) Mark as an unused flag.

Hereinafter, the fetch access will be explained as fetch access from the data section.

Among the above cases, case (3) is based on the conventional C) IB
This is the same as the case of memory access to C) 41, and the above-mentioned fetch and store operations to C)+841 are controlled.

+ll, +2) case (2) is MSU
The same control is performed except that a memory access request is issued to s with the highest priority.

The case of il+ is the operation when the present invention is implemented, and the details thereof will be explained below.

"For fetch access" CIIB TAG 7 with CIIP number and channel number
0 and performs the following control based on the reference result.

■ Case of address mismatch: This case applies to most fetch accesses from MXC.

In this case, an 8-byte fetch access is activated for MSU1. Fetch data from MSII 1 is sent directly to CI (P 3
This fetch access is completed by simply sending it to .

■In case of address match: In CII[l 41, (:HB DATA 11
The data read from C) IP fetch data register (CHPFCIIOR) 14. After setting it to either '15, simply send it to CIIP 3, and this process ends.

"For store access" CI (P number, channel number, CHB TAG 7
0 and 71, and perform the following control based on the reference results.

■ Case of address mismatch: This case applies to most store accesses from MMC.

In this case, an 8-byte store access is initiated for MSU 1. C) Writing to the IB 41 is controlled not to be performed.

■If the address matches and C=O: C) After invalidating the relevant block of IB 41 (setting v=0), an 8-byte store access is performed to MStl 1, but will not be written.

■If the address matches and C=1: Move out the relevant block of CITB 41 to MSU 1, invalidate that block (set v=0), and then perform 8-byte store access to MSII 1. , but does not write to CI (B 41).

The operation when implementing the present invention has been explained above, but
In the present invention, when a memory access is performed from the CUP 3 to the MCU 4, a flag (D, P
), and the flag (, indicating memory access from MXC) performs an 8-byte memory fetch in the case of a fetch request, and transfers the fetch data directly to CHP 3 without registering it to Cll841. The key point is that in the case of a store request, it is controlled to write 8-byte data directly to MSU 1 without writing to CUB 41.

(Illusionary Effects of the Invention) As explained in detail above, the channel buffer control method of the present invention provides an interface between the channel processor and the main memory control unit in a data processing system in which the main memory control unit includes a channel buffer. A flag is provided, the main memory control unit recognizes the flag, identifies the type of channel performing memory access, changes control over the channel buffer according to the type of channel, and controls memory access from the multiplexer channel. In both fetch and store cases,
Since it is controlled so that no registration or writing is performed in the channel buffer, it is possible to control the channel buffer efficiently.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a data processing system to which the present invention is applied, FIG. 2 is a diagram showing an example of the configuration of a channel buffer (CHB), and FIG. 3 is a diagram showing an example of the configuration of a channel buffer (CII
It is a figure showing the example of composition of the tag part of B>. In the drawing, 1 is the main memory (MSLI), 2
c central processing unit (CP[I), 3 a channel processor (CHP), 4 a main memory control unit (M
CU), 41 is a channel buffer (CHB)
, 5 CIIP address register (C) IPAR)
, 51 is a flag register (F), 6 is a channel identification register (CHIDR), 61 is C) IP number identification section, 70.71 is a channel buffer tag section (
CUB TAG), 80.81 is the comparison circuit (C)
, 10 is CI (B address register (CHBAR)
, 101 is the matching way number register (C:WNR)
, 11 is the data section of the channel buffer (CHB DA
TA), 12 is the CHB data register (CHBDI
? ), 13 is the CHP store data register (COP
STDR) and 14.15 indicate the CIIP fetch data register (C)IPFCIIDR), respectively.

Claims (1)

[Claims] A data processing system consisting of a main memory device and a main memory control section that performs memory control between a central processing unit and a channel processor, and in which the main memory control section has a built-in channel buffer. A flag is provided in an interface to the storage control unit, and the main storage control unit recognizes the flag to identify the type of channel that performs memory access, and changes control over the channel buffer depending on the type of channel. Characteristic channel buffer control method.