JPS606040B2 - integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, and more particularly to writable, read-only integrated circuits.

Various types of programmable memory elements have been developed to date, and among them, P-ROMs with transistor-based junction breakdown types, which use transistors as memory elements depending on the presence or absence of short circuits in the emitter junction, include Nichrome, etc. It is attracting attention because it can be produced using a normal bipolar process without requiring a fuse.

In particular, in the method of using open-base transistors as storage elements, the base and collector junctions can be used as decoupled diodes when configuring a memory element matrix array as they are, and since the collectors can be shared in the row direction, is widely used as it does not require insulation. Although the present invention is generally applicable to memory elements that write by flowing current, it is particularly effective for memory elements that require large current writes, such as junction breakdown type memory elements. I will also explain the combination with a destructive element. For devices using junction breakdown type memory elements, the write current is usually quite large, 20 hA, as seen in programmable ROMs and programmable logic arrays PLA that are commonly available on the market. It is an electric current.

This is a very large amount of current that can be handled by a normal integrated circuit, and therefore, to enable such large current control, a low impedance and high withstand voltage element is required in the write current path. This increases the overall size of peripheral circuit elements, which is a major obstacle to miniaturizing the pellet and shortening the propagation delay time during read operations.

One way to deal with this problem is to develop an element that can write with low energy by reducing the size of the memory element, making it possible to write with small current and low voltage, and as a result, reduce the size of the peripheral circuit elements. There is.

However, although the memory element manufactured in this way does produce a small write current, on the other hand, when a large current of about 20 mm is passed through the memory element, the collector that should remain for decoupling when a matrix array is configured. , the PN junction between the bases may deteriorate or be destroyed, resulting in writing failure.

Furthermore, since the impedance of the storage channel generally increases as the storage element and peripheral circuits are reduced, an excessively large voltage may be applied to the elements of the write circuit, potentially causing element destruction.

Therefore, the only way to stably write to a memory element that can be written to with such a small current is to adjust the writing device from outside the PROM chip to inject the optimal current and apply the optimal voltage clamp. On the other hand, considering the relationship between the programmer and PROM, it seems that the writing current and clamp voltage specifications of the programmer were changed every time the PROM process was changed. compatibility would be completely disrupted. An object of the present invention is to provide an integrated circuit having a write circuit that can supply an optimum current to a memory element with a small write current and perform stable writing without changing the conventional write specifications.

Another object of the present invention is to write without any modification using a writer having an arbitrary write current and an arbitrary clamp voltage that are greater than or equal to the minimum write current and minimum clamp voltage required for the device. Our goal is to provide the best chips possible.

In order to achieve the above object, the present invention provides a current limiting circuit in the write current path inside the chip when a large current is supplied to the PROM chip by the writer according to the conventional write specification, and the selected memory is Designed so that only the desired current flows through the element,
The excess current is further bypassed by a constant voltage clamp circuit installed inside the chip, so that excessive voltage is not applied to the chip and the memory element can be stably written to and output with the optimum current. It is characterized by

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a well-known example of a programmable RON using a junction-destructive cell array. This is a simple circuit example in which a cell array of n rows by m rows is provided with a row selection circuit and a column selection circuit, respectively, and a write operation will be explained with reference to this figure. Now, suppose that the row line X is selected by the row selection circuit 2 and the column line Y is selected by the column selection circuit 10, then the cells Q, . is in a selected state and a write current is supplied from write terminal 1, all of them are applied to column selection circuits -Y, -Q, . −×
, one row selection circuit 2 in order, and the inflow cells Q, . The emitter and base junctions of are baked and changed from the state shown in FIG. 2a to the written state of FIG. 2b, and the base,
Only the collector junction remains and is used as a decoupling diode for the cell array. Here, cell array Q, . ~Qn
A memory element that can be written with low energy is applied to m, and the clamp voltage of the writer is 2 levels and the write current is 20 degrees according to the specifications of the writer.
When a large current of mA is supplied to V, data is written in the same way as the write operation described above, but this is an excessive current for a memory element that is made to be writable with such low energy. As mentioned above, deterioration occurs in the base and collector junctions,
Alternatively, an increase in write impedance may cause problems such as excessive voltage being applied to the chip. Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 3, a current limiting circuit composed of a feedback transistor Qg and a write current value detection resistor Rg is built into the row selection circuit 2 of the slave circuit in FIG. A clamp circuit 3 is connected thereto.

Now, when a write current is supplied from the write element 1 according to the specifications of the writer in the same way as in the write operation described above, this will cause the row selection circuit 10 to
When flowing from the only ○N gate in the gate to the ground through the detection resistor Rg, when the potential increase due to Rg reaches the threshold value of the feedback transistor, Qg becomes active and the ON gate The current flowing through the gate acts to reduce the current flowing through the gate, but since the current flowing through Rg tends to decrease, a force acts in the direction where Qg is cut off.
By configuring the feedback loop in this way, the current flowing into the gate settles to a constant value, and no more can be absorbed.

Therefore, if Rg is designed so that the absorption capacity of this gate is, for example, 5 hA, and 20 hA is applied from the writer, the output voltage of the gate will be reduced because it will absorb only the amount of gate 5. begins to rise rapidly, and following this, the potential of the write element 1 attempts to rise to a clamp voltage (for example, 2Ω) set by the writer. However, if the clamp voltage is reached as it is, the elements within the chip will need a high withstand voltage, so the objective of reducing the write current and element voltage to reduce the element height cannot be achieved. It disappears. For this purpose, a constant voltage clamp circuit 3 as shown in the specific example of FIG. 4 is added. This circuit 3 serves to clamp the write terminal 1 to a voltage lower than the clamp voltage set by the writer, for example 2 levels. In this circuit, if the ratio of R, , R2 is appropriately selected so that Q, , Q2 are turned on when the write terminal 1 reaches an arbitrary voltage VC, the impedance will drop rapidly and the constant voltage Vc
It serves the purpose of clamping the voltage applied to the chip to Vc
The following can be alleviated. In this circuit diagram, the energizing diode DE has the role of decoupling when the write terminal 1 also serves as an output terminal during the decoupling operation.

A second embodiment of the present invention will be explained with reference to FIGS. 5 and 6.

In this embodiment, a current limiting circuit 4 is provided between the write terminal 1 and the column selection circuit 10, and a constant voltage clamp circuit 3 is connected to the write terminal 1 as in the first embodiment. It's connected.

The operation of this current limiting circuit 4 will be explained with reference to the drawings. When a write current is supplied from write terminal 1, the current flows between the collector and emitter of transistor Q as the main route, and passes through resistor R4 to the column selection circuit and to the selected memory element Q, . However, when the potential drop of the write current detection resistor R4 reaches the threshold value of the feedback transistor Q, Q4 becomes active, and a force that tries to cut off Q acts. This works to reduce the current flowing through Q3, but in this case, the detection resistor R4
Since the current flowing in the current is about to decrease, Q4 again acts as a force in the cutoff direction. Due to such a feedback loop, the current flowing through Q3 settles to an approximately constant value, and when an attempt is made to flow more than this constant value, the resistor R3 causes the current to flow through the write terminal 1.
The voltage at the write terminal 1 attempts to rise to the clamp voltage set by the writer, but in the same manner as explained in the first embodiment, the voltage at the write terminal 1 is reduced to V by the constant voltage clamp circuit.
It is clamped at c.

In both the first and second embodiments of the present invention, the DC impedance of the write current path from the write terminal 1 is determined by adding a resistor g for detecting the current value so that the desired current value becomes 50%. If designed, as shown in FIG. 7, it will exhibit a constant current characteristic with a slope that is the sum of the internal impedance of the write current path and Rg, and will exhibit a constant current characteristic at a point of 5 degrees A, and will also exhibit a characteristic that is clamped at Vc. As explained above, the present invention provides a constant current limiting circuit and a constant voltage limiting circuit inside the PROM chip, so that even when a large current of a high voltage clamp is supplied as a write current from outside the chip, even the above limiting circuit is suitable. It is possible to write with the optimum current to a memory element that can be written to with low energy, and the voltage at the time of writing can be kept low, so it is stable without causing deterioration or destruction. You can get written information.

In this way, even if there is a change in the manufacturing conditions of the memory element and peripheral circuit due to process improvements, it is possible to write the optimal current according to the situation without changing the write specifications, and this allows PR.
The effects of the present invention are enormous because the high performance of OM can be easily realized.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing a subordinate integrated circuit, Fig. 2 shows a memory element, Fig. 2a is a circuit diagram showing the state before writing, Fig. 2b is a circuit diagram showing the state after writing, Fig. 3 4 is a configuration and a circuit diagram showing a first embodiment of the present invention, FIGS. 5 and 6 are a configuration diagram and a circuit diagram showing a second embodiment of the present invention, and FIG. 7 is a writing FIG. 3 is a diagram showing the relationship between current and write voltage. 1...Write terminal, 2...Row selection circuit,
3... Constant voltage clamp circuit, 4... Current limiting circuit. Figure/Figure 2 Figure 3 Figure 4 Younger brother's dance figure Figure 7

Claims (1)

[Claims] 1. In an integrated circuit that includes a fixed memory element that can be written semi-permanently by flowing a write current, and a write circuit for flowing the write current into the memory element, What is claimed is: 1. An integrated circuit characterized in that a current limiting circuit is provided to limit the current flowing into a storage element to below a certain value, and a voltage limiting circuit is provided in the write circuit to clamp the voltage to below a certain value.