JPH07123219B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit, and more particularly to a technique effective when applied to an EPROM (erasable programmable read only memory).

[Prior art]

In the EPROM, when the output buffer circuit coupled to the data input / output terminal is composed of a complementary MOSFET to which the power supply voltage is supplied, the output voltage level can be maximized to the power supply voltage level.

However, if a voltage of a relatively higher level than the power supply voltage is applied to the data input / output terminal due to an overshoot of the data signal from the signal transmission line or an undesired surge voltage, the voltage is used to form a complementary MOSFET. The parasitic thyristor is operated, resulting in so-called latch-up in which an abnormal current flows between the power supply terminal and the ground terminal of the circuit.

The latch-up of the complementary MOS integrated circuit is caused by a signal externally applied to the input / output terminal of such a complementary MOS integrated circuit. That is, the input / output terminals of the integrated circuit are affected by the transient waveform distortion caused by the non-negligible inductance and capacitance present in the wiring structure including the mounting board on which the integrated circuit is mounted. A signal having a level exceeding the power supply voltage level of the integrated circuit, in other words, a signal having an overshoot component is added.

For example, when the output buffer circuit of the integrated circuit is composed of a CMOS inverter circuit composed of a P-channel type MOSFET and an N-channel type MOSFET, if an externally applied signal has an overshoot, the drain of the P-channel type MOSFET is thereby caused. The potential becomes higher than the potential of the N-type substrate gate (that is, the semiconductor region forming the P-channel type MOSFET), and such a P-channel type MOSF is formed.
The ET drain junction is forward biased. As a result, a forward current flows in the drain junction. This drain junction current means injection of minority carriers into the semiconductor region forming the drain junction.

Here, in the complementary MOS integrated circuit, the P-type drain and source of the P-channel MOSFET
N-type semiconductor region forming MOSFET, N-channel type MOSF
N-type drain and source of ET, this N-channel MOSFET
Has a P-type semiconductor region that forms
Includes a structure that can be a PN parasitic thyristor element or a parasitic PNP transistor and a parasitic NPN transistor. Therefore,
When the minority carriers are injected as described above, the parasitic thyristor element is activated, and the operation of the parasitic thyristor element causes an excessive current to flow to the power supply terminal, so-called latch-up occurs.

Conventionally, as a measure for latch-up to the external terminal of the complementary MOS circuit, for example, "LSI issued on November 30, 1984 by Ohmsha"
As described in "Handbook" P403, the N-channel type MOSFET and the P-channel type MOSFET connected to the external output terminal are charged and separated so that the current amplification factor of the parasitic bipolar transistor forming the parasitic thyristor is sufficiently reduced. It has been dealt with by arranging them around the bonding pad.

[Problems to be solved by the invention]

However, with the demand for increased storage capacity, EPROM
It has become clear that the conventional measures cannot sufficiently prevent latch-up when the MOSFETs that make up the device are miniaturized. . According to a study by the present inventors, for example, when an integrated circuit manufacturing process with a channel length of about 1.3 μm is used, it is easy to apply a DC voltage higher than the power supply voltage by about 1 [V] to the data input / output terminals. It has become clear that latch-up occurs in and the reliability is significantly reduced. Therefore, the inventors of the present invention have used a pair of Ns in which the final output stage is connected in series as a measure against latch-up of the output buffer circuit.
We considered using a channel-type MOSFET, but in that case, the maximum output voltage level was N-channel type.
It is reduced by the threshold voltage of the MOSFET.

In other words, when the output MOSFET is composed of only N-channel type MOSFET in consideration of the latch-up countermeasure of the output buffer circuit, the potential applied to the drain of the N-channel type MOSFET is in the positive range even if the signal applied from the outside has an overshoot. , And the drain junction remains reverse biased. Therefore, in this case, the injection of the minority carriers that triggers the latch-up operation does not occur, so that the latch-up operation can be prevented from occurring.

However, in this case, although there is an advantage that latch-up can be prevented, another problem to be solved occurs that the level of the signal to be output cannot be raised to the full power supply voltage due to the voltage loss due to the N-channel MOSFET. .

An object of the present invention is to provide an output buffer circuit capable of preventing latch-up of the final output stage coupled to an input / output terminal.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, between the power supply terminal and the coupling node of a pair of series-connected N-channel MOSFETs (first and second MOSFETs of the second conductivity type) connected in series as the final output stage coupled to the input / output terminals (external terminals). , A resistor element formed on the semiconductor substrate via an insulating film and a P-channel MOSFET (first conductivity type third MOSFET) formed in the N type well region (second conductivity type well region) in series It was installed in.

[Action]

According to the above means, the drop of the output voltage according to the threshold voltage of the N-channel type MOSFET is compensated by the P-channel type MOSFET in the ON state, and the P-channel type MOSF.
Latch-up is prevented by limiting the base current of the parasitic PNP transistor configured via ET by the resistance element.

〔Example〕

FIG. 1 is a circuit diagram showing an output buffer circuit which is an embodiment of the present invention. This output buffer circuit is applied to the EPROM shown in FIG.

In FIG. 2, MA is a memory array, and although details thereof are not shown, FAMOS (floating gate, avalanche injection, insulated gate field effect transistor) is used as a memory element, and among these FAMOSs arranged in a matrix, Those arranged in the same row have word lines W _{1 to} Wm whose control gates correspond to the respective rows.
And the drains of those arranged in the same column are coupled to the data lines D _{1 to} Dn corresponding to the respective columns.

The word lines W _{1 to} Wm are coupled to the output terminals of the row decoder circuit RDEC. The row decoder circuit RDEC receives the row address signal Ari and thereby forms a selection signal for selecting a predetermined word line.

Column address signals for the data lines D _{1 to} Dn
A column decoder circuit CDEC for forming a selection signal for selecting a predetermined data line according to Acj is provided.
Each of the data lines D _{1 to} Dn is connected to the common data line CD via a column selection circuit CSW which is switch-controlled by receiving a selection signal formed by the column decoder circuit CDEC. The common data line CD is connected to a sense amplifier SA that amplifies data read from a predetermined storage element and an output buffer circuit BO that receives an output from the sense amplifier SA, and write data to a predetermined storage element. Is connected to an input buffer circuit BI which supplies The output terminal of the output buffer circuit BO and the input terminal of the input buffer circuit BI are input / output terminals I / O as external terminals of the memory (integrated circuit).
Commonly connected to. The input buffer circuit BI
A programming system including a high-voltage generating circuit for programming a predetermined storage element based on write data supplied through is not shown in FIG.

Next, details of the output buffer circuit BO will be described with reference to FIG.

The output buffer circuit BO is a complementary MOS inverter circuit (hereinafter also simply referred to as a CMOS inverter circuit) I ₁ and I _{2 that} is connected in two stages and is composed of a P-channel type MOSFET Q1 and an N-channel type MOSFET Q2. Of the CMOS inverter circuit I ₃ and the amplification stage. The CMOS inverter circuits I _{1 to} I of this amplification stage
_{Since 3} does not receive a signal including an overshoot from the outside at its output terminal, it is not directly related to latch-up operation, and a MOSFET with a relatively small channel width to channel length ratio is used. Therefore, it can be laid out at a position away from the input / output terminal I / O, and therefore these CMOS inverter circuits I _{1 to} I ₃ can be laid out.
The latch-up countermeasure can be implemented by a conventional method such as arranging the P-channel type MOSFET Q1 and the N-channel type MOSFET Q2 sufficiently apart from each other around the bonding pad.

The output voltage from the sense amplifier SA is supplied to the input terminals of the CMOS inverter circuits I ₁ and I ₃ , so that complementary level amplified outputs are obtained from the output terminals of the CMOS inverter circuits I ₂ and I _3. To be

The output terminals of the CMOS inverter circuits I ₂ and I ₃ are the power supply terminals Vc
They are respectively coupled to the gates of a pair of N-channel type MOSFETs Q3 and Q4 as an output stage connected in series between c and a reference terminal such as a ground terminal. These MOSFETs Q3 and Q4 are connected to the input / output terminal I / O at the coupling node N as their output terminals, and are complementarily switch-controlled based on the input voltage of the complementary level, so that the output from the sense amplifier SA. The output according to the voltage level is supplied to the I / O terminal.

In such an output stage, an element coupled to the input / output terminal I / O is composed of a pair of N-channel type MOSFETs Q3 and Q4. Therefore, the MOSFETs Q3 and Q4 do not form a thyristor structure with each other, and there is no risk of latch-up by them. However, when the output from coupling node N is set to the high level, the output level is lowered by about the threshold voltage of MOSFET Q4 with respect to the power supply voltage level.

In this embodiment, in order to compensate for this voltage drop,
Between the coupling node N of the MOSFETs Q3 and Q4 and the power supply terminal Vcc, there is provided a P-channel MOSFET Q5 which is turned on in the same phase as the MOSFET Q3 by having its gate coupled to the output terminal of the CMOS inverter circuit I ₁ . Such MOSFET
When Q5 is turned on with MOSFET Q3 above, its
It has an auxiliary function of boosting the voltage level output to the coupling node N via the MOSFET Q3 to the current voltage level. Therefore, the MOSFET Q5 can sufficiently exhibit its function even if it has a small size such that its current supply capability is relatively low. For example, if MOSFETs Q3 to Q4 have the same channel length as each other, MOSFET Q3
Even if the channel width of the MOSFET Q5 is about 1/10, the function is sufficiently exhibited.

Since the P-channel MOSFET Q5 constitutes a complementary MOS circuit together with the N-channel MOSFET Q4 due to its structure, a thyristor structure is formed by transistors parasitic to them. Therefore, if a voltage higher than the power supply voltage is applied to the input / output terminal I / O and the thyristor is turned on, latch-up will occur, but as mentioned above, the size of MOSFET Q5 depends on its function. Since it can be made extremely small, the N-channel MOSFET Q4 and the P-channel MOSFET Q5 connected to the input / output terminal I / O are sufficiently reduced so that the current amplification factor when the bipolar transistor forming the parasitic thyristor is operated is sufficiently reduced.
And separate and place around the bonding pad,
Alternatively, the conventional latch-up countermeasure such as forming a guard ring around the MOSFET Q5 can be effectively applied.

FIG. 3 is a sectional view showing a conceptual structure of a complementary MOS circuit constituted by the MOSFET Q4 and MOSFET Q5. MOSFE
TQ4 has a source NS and a drain ND of an N + impurity region formed in the P-type semiconductor substrate PSub, and a MOSFET Q5 has a source PS and a drain PD of a P + impurity region formed in the N-type well region NW of the P-type semiconductor substrate PSub. Have.

In such a structure, the general mechanism that causes latch-up development is as follows. That is, when a voltage relatively higher than the power supply voltage is applied to the input / output terminal I / O, a current flows through the P-type semiconductor substrate PSub, whereby the parasitic NPN transistor Tr ₁ is forward-biased, whereby the transistor Tr _{1 is transferred.} Is turned on. Since the collector current of the transistor Tr ₁ flows from the power supply terminal Vcc, a potential gradient is generated in the well region NW, which causes the base of the parasitic PNP transistor Tr ₂ to be forward biased. As a result, the transistor Tr _{2 is} also turned on, and in the transistors Tr ₁ and Tr ₂ in the on state, a thyristor phenomenon occurs and a large current that leads to element destruction flows.

As a result of studying the generation of the substrate current that causes such a latch-up phenomenon, the present inventors have found that when the base current of the parasitic PNP transistor Tr ₀ connected to the drain PD of the MOSFET Q5 exceeds a predetermined critical value, We have found that the base of Tr ₁ produces a substrate current that is forward biased. Therefore, in order to control the base current of the transistor Tr ₀ that flows between the input / output terminal I / O and the power supply terminal Vcc so as not to exceed the critical value, the input / output terminal I / O and the drain of the MOSFET Q5 are controlled. The resistance element R is coupled to the PD. This resistance element R is connected to the critical value of the base current when the transistor Tr ₀ is turned on and the input / output terminal
In relation to the upper limit of the voltage applied to I / O,
The resistance value is set to a level sufficient to control the base current of the transistor Tr ₀ so as to prevent it from turning on.
The resistance element R can be formed, for example, by forming a well region in the P-type semiconductor substrate PSub and providing two electrodes in this well region. However, when the resistance element is formed by the well region as described above, an abnormal voltage such as a surge voltage applied to the input / output terminal I / O causes the PN junction between the well region and the semiconductor substrate to be in the forward bias state. In order to reduce the risk that a current that promotes the latch-up operation will flow through the semiconductor substrate as a result, the resistance element R is formed of, for example, an insulating film made of a silicon oxide film on the semiconductor substrate PSub. It is desirable to be composed of a resistance layer such as a polycrystalline silicon layer formed through a film. The resistance layer insulated from the semiconductor substrate PSub can be trimmed by a processing means such as laser light if necessary. In particular, if such a resistance element R has a resistance value that can be set by trimming, the setting operation becomes extremely convenient. When the resistance element R is provided in this way, the upper limit value of the voltage that can be applied to the input / output terminal I / O can be set to be much higher than the power supply voltage level within the range where latch-up does not occur. Therefore, I / O terminal I /
Even if the write voltage to be applied to O is made relatively high, latch-up is surely prevented.

As is clear from the above description, the following effects can be obtained in this embodiment.

(1) Since the output stage is composed of N-channel type MOSFETs Q3 and Q4, latch-up does not occur by itself.

(2) N-channel MOSFETs Q3 and Q4 that make up the output stage
P-channel type M between the connection node N and the power supply terminal Vcc
Since OSFETQ5 is provided, N-channel MOSFETQ
The voltage drop of the output node N corresponding to the threshold voltage of 3 is compensated by the P-channel MOSFET Q5 in the ON state, whereby the output voltage level at the input / output terminal I / O can be maximized to the power supply voltage level. .

(3) The P-channel MOSFET Q5 has an auxiliary function of boosting the voltage level output to the coupling node N via the MOSFET Q3 to the power supply voltage level, and has a small size such that its current supply capability is relatively low. Therefore, the flexibility can be increased in taking conventional latch-up measures such as laying out MOSFETs Q4 and Q5 forming the complementary MOS circuit so as to be separated from each other.

(4) Since the resistance element R that restricts the base current of the parasitic PNP transistor Tr ₀ that causes latch-up in the complementary MOS circuit formed by the MOSFETs Q4 and Q5 to prevent its ON operation is provided, the input / output terminal Even if a voltage having a relatively higher level than the power supply voltage is applied to the I / O, it is possible to reliably prevent the latch-up.

(5) Due to the effects of the above (3) and (4), the reliability against the latch-up countermeasure can be significantly improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. There is no end.

In the above description, the case where the invention made by the present inventor is mainly applied to the output buffer circuit of the EPROM which is the background technical field has been described, but the present invention is not limited thereto and various output buffer circuits and it. It can be applied to a circuit having substantially the same function.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

That is, a resistance element and a P-channel MOSFET are connected in series between a power supply terminal and a coupling node of a pair of N-channel MOSFETs connected in series that are coupled to an external input / output terminal. P-channel type with on-state output voltage drop according to MOSFET threshold voltage
The base current of the parasitic PNP transistor, which is supplemented by the MOSFET and configured through the P-channel type MOSFET, is limited by the resistance element to prevent latch-up.

[Brief description of drawings]

1 is a circuit diagram showing an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a functional block diagram showing an EPROM to which the output buffer circuit is applied, and FIG. 3 is a diagram for explaining a latch-up phenomenon. Complementary MOS
It is sectional drawing which shows the conceptual structure of a circuit. BO: output buffer circuit, BI: input buffer circuit, I / O
...... Input / output terminals, Q3, Q4 …… N-channel MOSFET, Q5
... P-channel MOSFET, R ... resistive element.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/04 27/08 331 Z 29/788 29/792 H03K 17/08 C 9184-5J 19 / 0948 H01L 29/78 371 (72) Inventor Takeshi Furuno 1450, Kamisuihoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (56) Reference JP-A-58-48957 (JP, A) JP-A-60- 227516 (JP, A)

Claims (2)

[Claims] 1. A coupling node of a pair of second conductivity type first and second MOSFETs connected in series as a final output stage formed on the surface of a first conductivity type semiconductor substrate and coupled to an external terminal, and a power supply. A resistance element formed between the terminal and the semiconductor substrate via an insulating film, and a first conductivity type 3M formed in a well region of the second conductivity type of the semiconductor substrate.
An output buffer circuit characterized by being provided with an OSFET in series. 2. The output buffer circuit according to claim 1, wherein the ratio of the channel width to the channel length of the third MOSFET is smaller than that of the first MOSFET.