JPS6059652U - wireless selective calling receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a radio selective calling receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a signal received and demodulated by the receiver of FIG. 1, and FIG. A flowchart showing the operation of the decoder 40 shown in FIG. 1, and FIG. 4 show the operation switches S0, Sl, S2, . A diagram showing the transition of the functions of S3, FIG. 5 is the message data processing unit 6 of FIG.
6 is a block diagram showing the configuration of the 1-chip CPU 100 in FIG. 2, FIG. 7 is a block diagram showing the configuration of the LCD driver 200 in FIG. 9 is a block diagram showing the configuration of the RAM 300 in FIG. 2, FIG. 9 is a circuit diagram showing the frame synchronization signal/stop signal detection circuit in the decoder 40 in FIG.
1 is a circuit diagram showing the selective call signal detection circuit in the decoder 40 of FIG. 1, FIG. 11 is a circuit diagram showing the configuration of the buffer 70 and call display means 80 of FIG. 1, and FIG.
' It is a diagram showing a symbol structure and display example of the display device 90 in FIG. 1. DESCRIPTION OF SYMBOLS 10... Antenna, 20... Radio part, 30... Waveform shaping circuit, 40... Address decoder, 50...
P, ROM, 60...message data processing section, 61
...Diode, 62...Capacitor, 70...
Buffer, 80...first display means, 90...second
display means, 100...IChip CPU,
101...Crystal, 101-106...Input port, 107...Interrupt port, 108...Serial interface, 111-117...Output port, 120...Bus, 130...Program counter , 140...program memory, 150...ALU
, 160... instruction decoder, 170...
...ACC, 180...RAM, 190...System clock generation circuit, 200...LCD driver, 2
10... Column driver, 220... Row driver, 230... LCD voltage control controller 240
... LCD timing controller, 250 ... data memory, 260 ... system clock controller, 270 ... command decoder, 280 ... data pointer, 290 ... character generation circuit, 295
...Serial interface, 300...RAM,
310... Serial interface, 320... Address counter, 330... X/Y decoder, 34
0...Memory array, 350...Control circuit, 500
...Shift register, 510,520.530...
Inverter, 540... Antogenide, 600...
Counter, 610...EXCLUSIVE NOR
Circuit, 710 and 720--Resistance, 730...NP
N transistor, 740...PNP transistor, 8
00...Alarm horn, 1000...Battery, SO
, Sl, S2. S3...operation switch. Fig. 9 f, 7541 Me0 00 Fig. 10 ■-Shoulder r-'T---〃

Claims (1)

[Claims for Utility Model Registration] 1. A radio selective calling receiver that receives a selective calling number and message information, including at least a first decoder that detects the selective calling number, and a first decoder connected to the first decoder and connected to the first decoder. an oscillation circuit that supplies a first reference signal to the first decoder 7; and a second decoder that decodes the message information; A radio selective calling receiver characterized in that it receives a reference signal as its own reference signal. 2 Utility Model Registration Scope of the Claims In the radio selective calling receiver according to claim 1, the second decoder receives the output of the oscillation circuit whose frequency is divided by N (N is an integer of 2 or more) by the first decoder. A radio selective calling receiver that receives the signal as its own reference signal. 3 Utility Model Registration Scope of Claim 1 In the radio selective calling receiver according to claim 1, the first decoder includes a bit synchronization circuit that performs bit synchronization based on a received signal, and the second decoder includes a bit synchronization circuit that performs bit synchronization based on a received signal. A radio selective calling receiver receives the output signal of the radio as its reference signal.