JP2845577B2 - Radio selective call receiver - Google Patents
Radio selective call receiverInfo
- Publication number
- JP2845577B2 JP2845577B2 JP2154590A JP15459090A JP2845577B2 JP 2845577 B2 JP2845577 B2 JP 2845577B2 JP 2154590 A JP2154590 A JP 2154590A JP 15459090 A JP15459090 A JP 15459090A JP 2845577 B2 JP2845577 B2 JP 2845577B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- radio selective
- signal line
- selective call
- call receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は無線選択呼出受信機に関し、特にデータ処理
等のロジック動作を行なうICを有する無線選択呼出受信
機に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio selective calling receiver, and more particularly, to a radio selective calling receiver having an IC for performing a logic operation such as data processing.
従来、この種の無線選択呼出受信機のロジック回路は
IC1個で構成され、このICは、電池電圧で動作し、デー
タ処理用のクロックは数100KHzであるため、ロジックの
信号ラインからのノイズ輻射は無線部の特性に特に大き
な問題はもたらさなかった。しかし、近年無線選択呼出
受信機の高機能化に伴ない、ロジック回路もCPU,ROM,RA
M,周辺IC,LCDドライバ等の複数のICにより構成されるよ
うになってきた。Conventionally, the logic circuit of this type of radio selective calling receiver is
Since the IC is operated by a battery voltage and the clock for data processing is several hundred KHz, the noise radiation from the signal line of the logic did not cause a serious problem in the characteristics of the radio unit. However, in recent years, as the function of the radio selective calling receiver has become more sophisticated, the logic circuit has also become
M, peripheral ICs, LCD drivers, etc. have come to comprise a plurality of ICs.
上述した従来の無線選択呼出受信機は、ロジック回路
を構成する複数のIC間の信号ラインが共通線構造（バス
方式）で接続されていて、プリント基板上に複雑に配線
されている。また、これらのICは電池電圧で動作するも
のはほとんどなく、DC−DCコンバータ等で電池電圧を昇
圧し、この昇圧された電圧により動作する。In the above-described conventional radio selective calling receiver, signal lines between a plurality of ICs constituting a logic circuit are connected in a common line structure (bus system), and are wired in a complicated manner on a printed circuit board. In addition, these ICs hardly operate at a battery voltage, and the battery voltage is boosted by a DC-DC converter or the like, and the IC is operated by the boosted voltage.
さらに、クロックも周波数が高くなってきている。従
って、信号ラインを流れる信号レベルも大きくなり周波
数も高くなっている。Furthermore, the frequency of the clock is also increasing. Accordingly, the level of the signal flowing through the signal line is increased and the frequency is also increased.
さらには、バス方式により各ICに信号ラインが接続さ
れるため信号ラインの引き廻しが長くなり、ノイズ輻射
量は一段と増加し、無線部の受信感度を著しく劣化させ
るという欠点がある。Furthermore, since the signal lines are connected to the respective ICs by the bus method, the routing of the signal lines is lengthened, the amount of noise radiation is further increased, and the reception sensitivity of the radio unit is significantly deteriorated.
本発明の無線選択呼出受信機は、アンテナと、前記ア
ンテナで受信した信号をクロック発振器からのクロック
信号によりディジタル処理する信号処理部と、前記信号
処理部で処理された信号を表示する表示部と、前記信号
処理部と前記表示部とを接続する信号ラインに直列に挿
入され前記信号ライン上の信号の高周波ノイズとなる周
波数成分に対するインピーダンスを高くして前記信号ラ
インを流れる高周波ノイズとなる電流を低減する抵抗と
を備えて構成される。A radio selective calling receiver of the present invention includes an antenna, a signal processing unit that digitally processes a signal received by the antenna with a clock signal from a clock oscillator, and a display unit that displays a signal processed by the signal processing unit. A signal that is inserted in series with a signal line connecting the signal processing unit and the display unit and that increases the impedance of a signal on the signal line to a frequency component that becomes high-frequency noise to increase a current that becomes high-frequency noise flowing through the signal line And a resistance to be reduced.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。 FIG. 1 is a block diagram of one embodiment of the present invention.
アンテナ１により受信された無線信号は、無線部２で
増幅後復調される。復調された信号は、波形整形回路３
により、デコーダ４で読みとり可能な波形に変換され
る。デコーダ４では、PROM（Programable Read Only Me
mory）５に予め書き込まれている自己の呼出番号と波形
整形回路３からの信号の中の呼出番号とを比較して、両
者が一致したときは呼出番号に引き続くメッセージ信号
をCPU6に出力する。The radio signal received by the antenna 1 is amplified and demodulated by the radio unit 2. The demodulated signal is output to the waveform shaping circuit 3
Is converted into a waveform readable by the decoder 4. In the decoder 4, a PROM (Programmable Read Only Me
(mory) 5 and compares the calling number in the signal from the waveform shaping circuit 3 with the calling number, and outputs a message signal following the calling number to the CPU 6 when they match.
CPU6では、メッセージ信号に関して誤り検出，誤り訂
正等の処理を行ない、LCDドライバ12にメッセージデー
タを出力すると供に、デコーダ４に呼出しがあったこと
を知らせるための通報命令を出力する。デコーダ４は、
CPU6からの通報命令により、増幅器９に鳴音信号を出力
してスピーカ10を駆動する。同時に、LCDドライバ12はL
CD表示部13にメッセージデータを表示させる。The CPU 6 performs processing such as error detection and error correction on the message signal, outputs message data to the LCD driver 12, and outputs a report instruction to notify the decoder 4 that a call has been made. The decoder 4
In response to a notification command from the CPU 6, a sound signal is output to the amplifier 9 to drive the speaker 10. At the same time, the LCD driver 12 is L
The message data is displayed on the CD display unit 13.
ROM7にはCPU6をコントロールするためのプログラムが
書き込まれている。RAM8は、CPU6の処理の中で、データ
または各種変数の一時記憶場所として活用される。クロ
ック発振器11は、各種タイミングの発生及びCPU6の処理
用クロックの発生を行なう。A program for controlling the CPU 6 is written in the ROM 7. The RAM 8 is used as a temporary storage location for data or various variables in the processing of the CPU 6. The clock oscillator 11 generates various timings and generates a processing clock for the CPU 6.
抵抗14は、実装上長く引き廻してしまったLCDドライ
バ12への信号ラインに直列に挿入され、高周波成分とな
る電流の周波数成分を低減する。The resistor 14 is inserted in series with the signal line to the LCD driver 12 that has been long routed for mounting, and reduces the frequency component of the current that is a high frequency component.
第２図は、CPU6の出力ポートからLCDドライバ12の入
力ポートへ流れる信号電流について説明するための、CM
OSロジックICの等価回路である。FIG. 2 is a CM for explaining a signal current flowing from the output port of the CPU 6 to the input port of the LCD driver 12.
This is an equivalent circuit of an OS logic IC.
CMOSロジックICの出力ポートは、等価的に電源21と、
電流源（Ｐ）22と、電流源（ｎ）25と、スイッチ（Ｐ）
23とスイッチ（ｎ）24とで構成され、第２図ではスイッ
チ（Ｐ）23がオンになりハイレベルを出力している状態
を表わしている。また、入力ポートは等価的に容量27で
表わされる。従って、電流源（Ｐ）22により容量27が充
電されることにより、入力ポートはハイレベルになる。
この容量27が充電される時定数は、容量27の容量値を
Ｃ、抵抗26の抵抗値をＲとすると、RCで表わされ、この
抵抗値Ｒを適当に選ぶことにより、本来のデータを表わ
す電流を伝送し高周波ノイズとなる電流の周波数成分を
低減信号ラインが実現できる。The output port of the CMOS logic IC is equivalent to the power supply 21,
Current source (P) 22, current source (n) 25, switch (P)
FIG. 2 shows a state in which the switch (P) 23 is turned on and outputs a high level. The input port is equivalently represented by a capacitance 27. Therefore, when the capacitor 27 is charged by the current source (P) 22, the input port goes high.
The time constant at which the capacitor 27 is charged is represented by RC, where C is the capacitance value of the capacitor 27 and R is the resistance value of the resistor 26. By appropriately selecting the resistance value R, the original data can be obtained. A signal line can be realized which reduces the frequency component of the current which transmits the represented current and becomes high frequency noise.
以上説明したように本発明は、無線選択呼出受信機の
ロジック系で使われるIC間の信号ラインに抵抗を直列に
挿入することにより、信号ラインに流れる高周波ノイズ
を低減でき、信号ラインからの高周波ノイズの輻射とな
る電流を低減できるので、受信部の受信感度の劣化を防
止できる効果がある。As described above, the present invention can reduce high-frequency noise flowing in a signal line by inserting a resistor in series in a signal line between ICs used in a logic system of a radio selective calling receiver, thereby reducing high-frequency noise from the signal line. Since the current that becomes noise radiation can be reduced, there is an effect that deterioration of the receiving sensitivity of the receiving unit can be prevented.
第１図は本発明の一実施例のブロック図、第２図は第１
図におけるCPU6からLCDドライバ12へ流れる信号電流に
ついて説明するための等価回路図である。 １…アンテナ、２…無線部、３…波形整形回路、４…デ
コーダ、５…PROM、６…CPU、７…ROM、８…RAM、９…
増幅器、10…スピーカ、11…クロック発振器、12…LCD
ドライバ、13…LCD表示部、14…抵抗。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is an equivalent circuit diagram for describing a signal current flowing from a CPU 6 to an LCD driver 12 in the figure. DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... Wireless part, 3 ... Waveform shaping circuit, 4 ... Decoder, 5 ... PROM, 6 ... CPU, 7 ... ROM, 8 ... RAM, 9 ...
Amplifier, 10 speaker, 11 clock oscillator, 12 LCD
Driver, 13 LCD display, 14 Resistor.
Claims (1)
ロック信号によりディジタル処理する信号処理部と、 前記信号処理部で処理された信号を表示する表示部と、 前記信号処理部と前記表示部とを接続する信号ラインに
直列に挿入され前記信号ライン上の信号の高周波ノイズ
となる周波数成分に対するインピーダンスを高くして前
記信号ラインを流れる高周波ノイズとなる電流を低減す
る抵抗と を備えたことを特徴とする無線選択呼出受信機。An antenna; a signal processing unit for digitally processing a signal received by the antenna with a clock signal from a clock oscillator; a display unit for displaying a signal processed by the signal processing unit; and a signal processing unit. And a resistor that is inserted in series with a signal line connecting the display unit and increases the impedance of the signal on the signal line with respect to a frequency component that becomes high-frequency noise to reduce a current that becomes high-frequency noise flowing through the signal line. A radio selective call receiver, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154590A JP2845577B2 (en) | 1990-06-13 | 1990-06-13 | Radio selective call receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154590A JP2845577B2 (en) | 1990-06-13 | 1990-06-13 | Radio selective call receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0445620A JPH0445620A (en) | 1992-02-14 |
| JP2845577B2 true JP2845577B2 (en) | 1999-01-13 |
Family
ID=15587518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2154590A Expired - Lifetime JP2845577B2 (en) | 1990-06-13 | 1990-06-13 | Radio selective call receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2845577B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2944444B2 (en) * | 1995-01-12 | 1999-09-06 | 日本電気株式会社 | Portable radio |
| JP2755207B2 (en) * | 1995-02-28 | 1998-05-20 | 日本電気株式会社 | Wireless selective call receiver with infrared data transmission function |
| JP2795278B2 (en) * | 1997-08-19 | 1998-09-10 | 日本電気株式会社 | Radio selective call receiver |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5890837A (en) * | 1981-11-19 | 1983-05-30 | Nec Corp | Signal detecting circuit |
| JPS6038365Y2 (en) * | 1982-09-07 | 1985-11-15 | 六郎 三原 | fishing line winder |
| JPH046278Y2 (en) * | 1984-12-04 | 1992-02-20 | ||
| JPS63174742U (en) * | 1986-09-29 | 1988-11-14 |
-
1990
- 1990-06-13 JP JP2154590A patent/JP2845577B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445620A (en) | 1992-02-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2834085B2 (en) | Wireless device reporting device | |
| JP2845577B2 (en) | Radio selective call receiver | |
| JPH1070441A (en) | Semiconductor device | |
| US6216385B1 (en) | Radio calling receiver with means to control reception based on service area, time zone, and/or electric field strength | |
| CA2309911A1 (en) | System and method for reducing peak current and bandwidth requirements in a display driver circuit | |
| US20020082056A1 (en) | Vibrator controlling circuit | |
| EP0468726A2 (en) | Paging receiver having a speaker and a LED alternatively driven on receiving a call | |
| CN1033547C (en) | An operational transconductance amplifier with matched outputs | |
| US20030169074A1 (en) | Low-voltage drive circuit and method for the same | |
| JPS62135026A (en) | Radio calling receiver | |
| KR910003050B1 (en) | Paging reciever | |
| JPH1080059A (en) | Voltage control system and terminal device using it | |
| JP2002333906A (en) | Analog module for programmable controller | |
| KR920009383B1 (en) | Small sound radio pager receiver | |
| JPH0537408A (en) | Operating voltage control circuit for radio equipment | |
| US7002392B2 (en) | Converting signals from a low voltage domain to a high voltage domain | |
| JPS59127436A (en) | Integrated circuit with mixing function of singing signal | |
| JP3863403B2 (en) | Transmitting apparatus and transmitting method | |
| JP3076233B2 (en) | Drive circuit of alarm sound device | |
| JP2001274662A (en) | Power switch circuit | |
| JPH05165787A (en) | Small-sized electronic appliance system | |
| JP3084897B2 (en) | Manchester decoder input circuit | |
| JPH0124800Y2 (en) | ||
| JPH06224977A (en) | External interface selection device | |
| JPH09215314A (en) | Dc-dc converter circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071030 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081030 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091030 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091030 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101030 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101030 Year of fee payment: 12 |