JPS6058721A - Ad converting circuit - Google Patents

Abstract

PURPOSE:To utilize advantages of both systems and to attain ease of variable resolution by combining the charge balance type and the feedback for pulse width modulation system. CONSTITUTION:When a clock pulse is fed to a frequency division circuit 9C, a signal BASE2 having a period 2<5> times the clock period and a signal CONTROL having a period 2<5> times thereof is produced to a frequency divider circuit 9C'. A switch 11 is changed over at an equal time interval by the signal BASE2. On the other hand, an output of a comparator 3 is sampled, stored in an FF4 and the output changes over the current of a current source 6 to 1r and 0. The output current of current sources 6, 12 changed over in this way and a current proportional to a voltage Ea to be converted are added and integrated by an integration device 2 and its output is changed as an INT2 in the Figure. In this case, conversion data Ed counting an output pulse AND2 of an AND gate 7 by a counter 8 is outputted. The resolution of 10 bits is provided in this example.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an A
This invention relates to a D conversion circuit, particularly an integral type AD conversion circuit that fully utilizes an integrator.

[Technical background of the invention and its problems]

There are various types of AD conversion circuits, and the ones closest to the integral type include a charge balance type AD converter and a feedback type/Grus width modulation type AD converter.

First, a charge-balanced AD converter will be explained with reference to FIGS. 1, 2, and 3. In Figures 1 and 2, 1 is an amplifier receiving the voltage to be converted Ea, 2 is an integrator, an operational amplifier OP, and a capacitor C1.
It is composed of many resistors such as R. 3 is a voltage comparator that compares the integrated output voltage with a reference potential (OV in this case), 4 is a control flop, and 5 is a current switch, which switches the stain current to Ir or zero according to the Q output of the above-mentioned flip-flop 4. In FIG. 2, it is schematically shown as a switch symbol.

6 is a first current source that generates a constant current Ii; 7 is an AND/DART operation that calculates the AND of the lock pulse and the Q output of the Noritsubu flop 4; 8 is a counter; and 9 is a time pace setting circuit (frequency dividing circuit). be.

That is, the voltage to be converted Effi is converted into a current by the resistor R,
It is added to the current Ir of the current source 6 or zero, and further integrated. This integrated output is compared with the reference potential (Ov) by the voltage comparator 3, and the result is sampled by the entire clock i9 pulse, held in the Noritub flop 4, and the output is used to control the current of the spot current source 6. It operates so as to switch between values (Ir and 0), and constitutes a discrete feedback system. This configuration operates so that the time average value of the charge accumulated in the integrating capacitor C of the integrator 2 becomes zero, and is therefore called a charge-balanced type.

1. Assuming that the average duty ratio of the output of the Noritsu flop 4 is tD, the input voltage Ea is R8·
In order to be equal to Ir-D, during the set time of the time pace setting circuit 9, count the outputs of the AND Goodor, which is the logical product of the output of the 7 ritsunoflop 4 and the clock pulse CP, by the total counter 8, and measure the duty ratio Dffi. By the way, the conversion data E-warm.

In this case, since the switching of the current source 6 is performed in synchronization with the full clock CP, residual charge due to the difference between the input voltage and the current source 6 is accumulated in the integrator 2.

Therefore, the average voltage of the output INTφ of the integrator 2 shown in FIG. 3 changes little by little. Therefore, increasing the length of the time pace improves the conversion resolution.

Although the charge-balanced AD converter has the advantage of being able to easily change the resolution, it has the following drawbacks.

(,) When the duty ratio D is around 0.5, the current source 6 is switched at the clock frequency, so the integrator 2 used needs to have excellent high frequency characteristics.

(b) When the r-neity ratio D is close to 0 or 1, the output waveform of the integrator 2 has a sharp time change in one direction and a very gradual time change in the other direction. In this case, it is affected by the dead zone of the comparator 3, or by the longer switching time of the comparator 3 when the input signal is small. In addition, since the number of times the current source is switched during conversion varies depending on the input signal, the current switch 5
0 The difference in switching time between on and off gives a shadow 41 to the linearity.

Next, a feedback pulse width modulation type AD converter will be explained based on FIGS. 4 and 5. This AD5- conversion circuit converts the output of the comparator 3 into the first current source 6 without sampling it with the clock pulse CP as shown in FIG.
The current of the first current source 6 has a large absolute value and equal positive and negative currents I, -I.
A second current source 12 is provided which outputs
′? The time pace setting circuit is divided into two stages of circuits 9A and 9B, and the second current switch 11 is switched at a duty ratio of 50 with the signal BASEI extracted from the middle. , is different from FIG. 1 in that the period is set to be the total conversion time.

In this case as well, the duty ratio iD of the output of comparator 3
Then, the input voltage E1 becomes equal to R6・■1・D, but since the change in the count nolus and the output of the comparator 3 are performed asynchronously, an error within +1 count is caused by the second current source 1.
This occurs frequently every 2 switching cycles. Therefore, the conversion time must always correspond to the switching period of the second current source 12.

For example, even if the total counting time of counter 8 in Figure 4 is increased by 8-6 = times, the conversion result will be 8 times the error per time.
Since the error is twice as large, the obtained data is simply 1
The value is only 8 times the value in the case of double, and the resolution does not improve.

This is due to the error (
This is because the same amount of the shaded portion) will occur in the next cycle as well.

On the other hand, in the charge-balanced AD conversion circuits shown in Figures 2 and 3, the switching of the current source is performed in synchronization with the clock, so the error decreases as the counting time increases, and the error is reduced by ±1 count. It will be within the error. On the other hand, an AD conversion circuit using a feedback pulse width modulation method has a large error.

Therefore, the switching period of the second current source 12 must be equal to the conversion time.If this type of AD conversion circuit is considered as a discrete time feedback system that operates so that the integrator output is all zero, Feedback is only performed twice during AD conversion, so if the input voltage, which is the signal to be converted, changes, the time required to obtain an accurate AD conversion value will be the same. This is slower than a charge-balanced AD conversion circuit that operates at a clock frequency of .

In this way, it is difficult to make the AD conversion circuit of the feedback type/thousand width modulation method variable resolution, and if the resolution is made variable, the circuit configuration will be complicated. The drawback is that it takes a long time to obtain the conversion results.

However, the sign change of the integrator 20 input current is II DII
rl, the input frequency to the integrator 20 becomes lower for the second time. Also, the time rate of change of the integrator output is II
(depending on the value of I-IIrI), the input voltage to the comparator 30 must not exceed a certain value within one clock cycle, and the effects of dead zones are less compared to the charge-balanced type. . Furthermore, since the influence of the difference in switching time between on and off of the switch is constant, with the number of switching times being two, there is an advantage that it does not affect linearity v.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an AD conversion circuit that takes advantage of the charge balance type and feedback pulse width modulation methods and whose resolution can be easily varied.

[Summary of the invention]

The AD conversion circuit according to the present invention has a first current source that outputs currents of two values, a second current source that outputs positive and negative currents with equal absolute values, and a current that is proportional to the voltage to be converted. An integrator performs addition and integration, the output voltage and a reference potential are compared with a voltage comparator, and the result is sampled using a constant cycle clock and stored in a flip-flop, while the clock is divided by a frequency divider circuit. The current of the second current source is switched at equal time intervals according to the output, and the current of the first current source is switched at equal time intervals.
All of the current sources are switched and fed back by the output of the flip-flop, and the Noculus, which is the AND output of the output of the flip-flop and the clock, is counted by a counter for a time that is an integral multiple of the period of the output of the frequency divider circuit, and the AI ) is output as converted data.

9- [Embodiment of the Invention] FIG. 6 shows an embodiment of the present invention, in which 1 is a buffer amplifier receiving the voltage to be converted Ea, and 2 is an integrator. It is composed of a resistor R6 for converting a current proportional to the voltage to be converted E8, an operational amplifier OP, an integrating capacitor C, and the like. 3 is this integrator 2
output voltage and reference potential C0V)'r: The voltage comparator 4 to be compared samples the output of this comparator 3 with a clock pulse of a constant period and stores it in a flip-flop, 5 is a first current switch, and 6 is a flip-flop. two values, (e.g. Ir and zero)
It is a current source of ml that outputs a total current of 100 ml, and the switching is performed by the switch 5.

7 is an AND gate that performs the logical product of the output of the flip-flop 4 and the clock pulse; 8 is a counter that counts the output pulses of this dart; 9C and 9C' are time base setting circuits (frequency dividing circuits); For example, (A) is connected in cascade with a division ratio of 5, the clock, clock and f pulses are completely frequency-divided, and the signal BASE2 used for switching the current of the second current source 10-, which will be described later, is taken out from the middle, and the subsequent circuit 9C' The output of the counter 8 is used as a signal C0NTR0L for controlling the counter 8. That is, the switching of the second current source is performed at a cycle that is 25 times the clock cycle, and the conversion time is further doubled.

1 is a second current switch, 12 is a second current source, and outputs positive and negative currents I, , -1,ffi having equal absolute values. The current switching of this second current source 12 is performed by a second current switch 11 using the signal BASE R as a control signal.
This is done at equal time intervals.

Note that the current source may be similar to that shown in FIG. 1, or may be a CMOS buffer 1 as shown in FIG.
The configuration includes a voltage diode 14, a resistor 15, etc., which serve as three standards, and a stain light switch.

Next, we will discuss the operation. When the clock pulse is applied to the time pace setting circuit 9C, its output is a signal BABE, ? with a period 25 times the clock period. is generated (see FIG. 8), and a signal C0NTR0L having a period 25 times that period is further generated in the time pace setting circuit 9C' at the subsequent stage.

The signal BASE 2 switches the second switch 11 at equal time intervals. That is, the current I of the second current source 12, -
A switch of I is made in line 8B.

On the other hand, the output of the comparator 3 is sampled by the clock and stored in the Flinno flop 4, and the output of the Flinno flop 4 is used as a dart control signal at the AND gate 7.
The signals are respectively supplied to the first switches 5 as switch control signals SW2, thereby switching the current of the first current source 6, that is, switching between Ir and zero.

The output currents of the current sources 6 and 12 corresponding to the current switching of the current sources 6 and 120 and the current proportional to the converted voltage E are added and integrated by the integrator 2, and the output J'l is as shown in FIG. I
Changes like NT 2.

At this time, the output pulse AND2 of the AND gate 7 is counted by the counter 8 and converted data E is output. This embodiment has a resolution of 10 bits.

In the above embodiment, the first current source 6 outputs a binary current of 1 and 0, but if 2 and 2 are used, then ADr r conversion for positive and negative input voltages is possible. , In general, if it is a binary current of ■yl#Ir2, then the voltage between R3·r1 and R8·■,2 will be converted. However, this is the case where the direction of sinking the current from the integrator is positive.

〔Effect of the invention〕

According to the present invention, the basic period of the integrator input waveform is 25 times the clock period, and the amount of change in the integrator output over time is also ensured to be at least a certain value depending on the value of III-II1. , the conditions for the integrator and comparator of the charge-balanced AD conversion circuit are relaxed.

In addition, the number of times the current sources are switched is constant at 25 times,
The on/off time difference does not affect the linearity, and the response when the input signal changes is as follows: the integrator output converges to zero 26 times during the conversion time. Therefore, it is faster than the AD conversion circuit 13 using the feedback pulse width modulation method. Furthermore, the switching period of the second current source (==
: The residual charge generated within 25
Since it is switched in synchronization with the clock, it is successively corrected and the final result is within ±1 count.

In other words, the drawbacks of the charge balance type and feedback type pulse width modulation systems are eliminated, and the advantages of both are incorporated.

Furthermore, the resolution can be changed by simply changing the counting length of the counter and the counting length of the latter stage of the time pace, and a variable resolution configuration can be achieved relatively easily.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram showing the basic configuration of a charge-balanced AD conversion circuit, Figure 2 is a block diagram showing a schematic configuration of the conversion circuit, Figure 3 is a waveform diagram of each part of the conversion circuit, and Figure 4 is a diagram showing the basic configuration of the charge-balanced AD conversion circuit. The figure is a block diagram showing a schematic configuration of an AD conversion circuit using the feedback pulse width modulation method, FIG. 5 is a waveform diagram of each part of the conversion circuit, and FIG. FIG. 7 is a block diagram showing an example of the current source in the same embodiment, and FIG. 8 is a waveform diagram of each part for explaining the operation of the same embodiment. 2... Integrator, 3... Voltage comparator, 4... 7th,
Pfrog, 5... first current switch, 6... first current source, 7... and f-), 8... counter, 9C and 9 C'... time base setting circuit ( (frequency dividing circuit), No. 1: third current switch, No. 12: second current source. Applicant's agent Patent attorney Takehiko Suzue 15- Yumida

Claims (2)

[Claims] (1) A first current source that outputs two current values, a second current source that outputs positive and negative currents with equal absolute values, and a current proportional to the voltage to be converted and the first and second current sources that output two values of current. An integrator that adds and integrates the output current of a current source, a voltage comparator that compares the output voltage of this integrator with a reference potential, and a flip 70 that samples and stores the output of this voltage comparator with a clock pulse of a constant period. a frequency divider circuit that divides the frequency of the clock pulse, a dart circuit that controls passing or blocking of the clock pulse using the output of the flip-flop as a control signal, and a counter that counts the output pulses of the dart circuit. The current of the second current source is switched at equal time intervals according to the output signal of the frequency dividing circuit, and the current of the first current source is switched and fed back by the output of the clip frog, An AD conversion circuit that counts output pulses of the circuit in the counter for an integer period of the output period of the frequency dividing circuit and outputs the result as AD conversion data. (2) The AD according to claim 1, wherein the counter and the frequency divider circuit generate a counter control signal with a time width that is an integer of the cutting edge period.As the frequency divider circuit, a variable counting length is used. conversion circuit.