JPS6058433B2 - Electronic clock time signal device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time signal device for an electronic watch. -1) A time signal device is proposed in which a time signal sound is generated N times at intervals of seconds starting from the previous second, and the time signal sound is generated at the Nth time.

Conventional time-signaling devices that use time-signal sounds are widely used in mechanical watches, but the time-signal devices used in these mechanical watches are large because they are mechanically constructed. Furthermore, the accuracy is low, making it inappropriate to use it as is in electronic watches. The present invention provides an electronic timepiece having a second counter for counting second signals and an hour counter for counting hour signals, which can be made simple and compact.
Furthermore, the present invention proposes a highly accurate time signal device. The figures will be explained below.

FIG. 1 is a block diagram showing the overall configuration J of an embodiment of the device of the present invention.

In the figure, reference numeral 1 denotes a clock generation circuit, which outputs a second signal Ss that is repeatedly generated every second. 2 is a second counter that counts this second signal Ss, and has an m-ary counter 21 and a hexadecimal counter 22, and has a minute signal gate S that is repeatedly generated every minute.
Output m.

3 is a minute counter that counts this minute signal Sm;
It has a w-adic counter 31 and a hexadecimal counter 32, and outputs a time signal Sh that is repeatedly generated every hour.

4 is a counter for counting the signal Sh at this time;
Constructed as a hexadecimal counter, it is configured to repeatedly count from 1 to 12.

The outputs of these counters 2, 3, and 4 are digitally displayed via a decoder (not shown). FIG. 3 is a diagram showing a specific configuration example of the hour counter 4, in which h is an input signal of the hour signal Sh, 41a to 41e are flip-flops, 42 is a 2-input AND circuit, and 43 is a 3-input AND circuit. Circuit, 44a, 44b are one-choice circuit, 45 is 2 input 0
R circuit, H, i, j, k, l are output signals.

In FIG. 1, 5 is the output signal H, i from the hour counter 4.
, j, kl, signals HO, iO,
This is a signal decoder circuit for outputting jO, kO, and lO, and a specific example of its configuration is shown in FIG. In Fig. 4, 51 indicates 2 inputs. AND circuit, 52 is 2 input NA
There is an ND circuit. FIG. 5 shows signals HO, iO, jO, kO when the input signal Sh to the hour counter 4 is from 1 to 12 o'clock.
, 1O is a truth value chart showing digital values of . The next time after the clock is 1 o'clock again. In FIG. 1, 6 is a second signal decoder circuit which receives signals a-g from the second counter 2 and outputs signals AO, bO, cO, dO, eO, and gO for time reporting control. An example of the configuration is shown in FIG.

In the figure, 61a to 61d are two-input AND circuits, 62a, 6
2b is an exclusive OR circuit, 63a and 63b are inverter circuits, and 64 is a 4-input circuit. NOR circuit, 65 is 2 input NOR
The circuits 66 are 2-input N, AD circuits, and 67 are 2-input 0R circuits. This second signal decoder circuit 6 is connected to the second counter 2.
When the second counter 2 is 598, it is converted into a 01 signal, and when the second counter 2 is in the second, it is converted into a 02 signal, and in the same manner. When the counter 2 indicates 41 seconds, this is converted into a signal of 19 seconds. The relationship between the output signals ad of the w-adic counter 21 of the second counter 2 and the outputs AO to DO of the decoder circuit 6 is shown in the truth value chart of FIG. Note that the decoder circuit 6
The outputs 01, 02, ... 19 are 1 for AO, 2 for shame,
This is the value when C0 is given a weight of 4, d0 is given a weight of 8, and e0 is given a weight of 10. When the second counter 21 of the second counter 2 is between 0 and 9, the output signal D is output. , cO, bO, aO are 0,9,8,
...1, and the signal 10 becomes 01 when the hexadecimal counter 22 of the second counter 2 is 5 seconds, and becomes 10 when it is the seasonal second. Another signal? is the effective period of the output of the decoder circuit 6, and in this example, the second counter 2 is at the ``1'' level during the period from 41 seconds to 5 seconds. Again in FIG. 1, 7 is the output of the decoder circuits 5 and 6. This is a matching circuit that checks the coincidence of the numbers, and a specific example of its configuration is shown in FIG.

In the figure, 71a to 71b are exclusive OR circuits, 72 is a 5-input NOR circuit, and 73 is a 2-input AND circuit. The exclusive OR circuits 71a to 71e respectively receive signals AO, HOl signal BO, IOl signal CO, and signal DO. A match between l5kOl signals 0 and 10 is detected, and when they all match, the NOR circuit 72 outputs a level of ゜゜1゛ level. This output is AND during the period when the signal GO is at the “1” level.
It passes through a circuit 73 and becomes a coincidence output m. In Figure 1,
8 is a 2-input AND circuit for minute detection, and minute counter 3
When the w-adic counter 31 is 9 and the hexadecimal counter 32 is 5, that is, the minute counter 3 is 5, a level output n of ``1'' is output.

9 is a two-input AND circuit receiving signals M and n, 10 is a detection circuit receiving hour signal Sh, 11 is an RS flip-flop, 12 is a gate circuit, and 13 is a sounding device.

The flip-flop 11 is reset when the output of the AND circuit 9 becomes the 46F level, and its output Q becomes the ``1'' level, and the flip-flop 11 is reset when the output of the detection circuit 10 becomes the ``1'' level. The output Q returns to the ゜“0” level. The gate circuit 12 is connected to the flip-flop 1.
It opens when the output Q of 1 is at 6゜r゛ level, and the second signal Ss
is output as a sound signal P, and the sound device 13 is activated every second. FIG. 2 shows each signal when announcing the time of 9 o'clock.

In this example, the AN of coincidence circuit 7 at 8:05, 41 seconds
Signal to D circuit 73? becomes the "゜1" level. Before the time of 9 o'clock is announced, the hour signal Sh to the hour counter 4 indicates 8 o'clock, and the outputs 10, k0, j0 of the hour signal decoder circuit 5 , 10, h0 are 01000, as is clear from FIG.

Therefore, if it becomes 8:05 and 5:00 and the outputs of the second signal decoder circuit 6 are 0, d0, c0, b0, a0, then 01000.
The output m of the coincidence circuit 7 becomes the "1" level, the output q of the AND circuit 9 also becomes the "1" level, and the output Q of the flip-flop becomes the 66r level.
The output P of the gate circuit 12 is ゜゜1 at intervals of 1 second from the 5th hoe.
level, and the sound device 13 operates at 1 second intervals.
The ninth beep starts from minute counter 3 to hour counter 4.
This is the time when the carry signal is issued, that is, just after 9 o'clock.

In this example, the ninth ringing must be the final ringing.

This is achieved immediately after the ninth ring by closing the gate circuit 1, which is achieved by resetting the flip-flop 11 by the output of the detection circuit 10. The detection circuit 10 is configured to respond to a carry signal from the counter 32 and reset the flip-flop 11 while the counter 21 reaches from (1) seconds to 01 seconds. Specifically, this detection circuit 10 includes a delay circuit that slightly delays the carry signal output from the counter 32 when the counter 21 reaches 0 and 2, and a delay circuit that receives this output and outputs a carry signal of The above-mentioned embodiment also includes a mono multi-circuit that outputs a level output.
The system is configured to distinguish it from the warning sound that will be sounded at one-second intervals by then.

Specifically, in the embodiment shown in FIG. 1, the carry output Sh of the counter 32 that counts the minute signal Sm is used to control the sound pitch of the sound device 13, thereby changing the forecast sound to a 440Hz1 hourly sound, for example. Different sounds were obtained by setting the pressure to 880. Furthermore, the flip-flop 11 is directly reset by the carry output Sh of the counter 32, and the gate circuit 12
It is also possible to obtain a forecast signal from the output of and operate the sound device 13, and also apply the carry output Sh of the counter 32 to a different sound device to generate a different sound, for example, a chime sound. It is. As is clear from the above description, according to the present invention, it is possible to easily and inexpensively realize a high-precision time signal device to be added to an electronic clock with a clock counting function, and there is also a difference between the time signal sound and the forecast sound. By doing so, it is possible to achieve reliable time reporting, which has a wide range of applications such as timer devices that require an audible signal, and is of great practical value.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of one embodiment of the device of the present invention, and FIG. 2 is a timing chart for explaining the operation.
FIG. 3 is a logic circuit diagram showing an example of the configuration of the hour counter, FIG. 4 is a logic circuit diagram showing an example of the configuration of the hour signal decoder circuit, and FIG.
Figure 6 is a logic circuit diagram showing a configuration example of a second signal decoder circuit, Figure 7 is its truth value diagram, and Figure 8 is its truth value diagram.
The figure is a logic circuit diagram showing an example of the configuration of a matching circuit.

Claims (1)

[Scope of Claims] 1 A second counter that counts second signals, a minute counter that counts minute signals, an hour counter that counts hour signals, and a second signal whose stepping force decreases as the second counter counts up. a decoder circuit, a time signal decoder circuit that receives the output of the hour counter, a coincidence circuit that receives the outputs of both the decoder circuits and sends out a coincidence output when their output signals match, and receives the output of the minute counter;
a detection circuit that detects the minute; an AND circuit that outputs when it receives the output of the coincidence circuit and the detection signal of the detection circuit; a latch circuit that latches the output of the AND circuit and is reset by a carry signal of the hour counter; A gate circuit that receives the output of this latch circuit and a second signal, and a sounding device that is driven by the output of this gate circuit and generates a time signal, and from the time when the outputs of both decoder circuits match, the digit of the hour counter is The sounding device is driven at intervals of seconds until the alarm time is reached, and the alarm sound is generated a number of times corresponding to the alarm time, and
A time signal device for an electronic clock, characterized in that the last start of the time signal sound coincides with each time signal time. 2. Claim 1, characterized in that the sounding device receives the carry signal of the minute counter and makes the final sound of the time signal sound different from other time sound sounds. The electronic clock time signal device described in Section 1.