JPS605636A - Data transmission system - Google Patents

Abstract

PURPOSE:To prevent lowering of transmission efficiency of short-period data by synthesizing the short period data and long-period data of n bits and sending it to the same transmission line in a transmitting side, and decomposing, rearranging and restoring this in a receiving side. CONSTITUTION:A transmitting device 10 inputs short-period data A1-An to a short-period data unit 11, and inputs long-period data B1-Bm to a long-period data unit 12. A CPU14 adds synchronizing data to data B1-Bm to produce long- period data, and decomposes bits L1-Ll of the long-period data into n bits, and adds decomposed bits L1-Ll and a parity bit P to the data A1-An to produce synthesized data, and sends this data to a transmission line through a transmission controlling unit 13. In a receiving device 20, a CPU24 decomposes the data A1-An and bits L1-Ll from the synthesized data rearranges them after plural samplings and restores the long-period data B1-Bm after executing program searching by detecting synchronizing data. The decomposed and restored data A1-An and B1-Bm are outputted through output units 22, 23 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data transmission method for transmitting two or more types of data with different transmission timings using one transmission path.

(Background technology) Conventional data transmission methods transmit data with fast transmission timing (
One part of the transmission area for data (hereinafter referred to as ``short-cycle data'') was allocated to data whose transmission timing was slow (hereinafter referred to as ``long-cycle data''). Figure 1 shows such a conventional An example of a transmission format using the data transmission method is shown. In the figure, Dt is short-cycle data transmitted within l samples, D2'it: long-cycle data transmitted within n samples, and D3 is short-cycle data transmitted within l samples. Add the long period data number (flat) and long period data BA (
A=1, 2.

..., m) and further adds a parity bit P.

In this way, in the conventional data transmission method, the composite data D
3 is a combination of the short-cycle data D and the long-cycle data D2, Bt, which has the problem of lowering the transmission efficiency of the short-cycle data.

(Object of the Invention) The present invention has been made by focusing on such conventional problems, and even when short-cycle data and long-cycle data are transmitted using the same transmission path, short-cycle data An object of the present invention is to provide a data transmission method that can transmit data without reducing data transmission efficiency.

Hereinafter, the present invention will be explained in detail based on the drawings.

(Implementation and operation of the invention) FIGS. 2 and 3 are block diagrams showing an embodiment of the present invention. FIG. 2 shows the configuration of a transmitting device, and FIG. 3 shows the configuration of a receiving device. .

In FIG. 2, lo is a sending device, short cycle data (Kaninia)11. Long-cycle data input crab unit 12, transmission control unit 13, central processing unit) (CPU) l
4 are connected and configured as shown in the figure. Here, the short-cycle data A1 to An are input into the short-cycle data input unit IIU, 1 sample. long period data input unit)
12 inputs long-period data B1 to Br11 into a plurality of data sets ((number of long-period data + 2) x number of bits). The transmission control unit 13 is a transmission control unit for outputting data synthesized by the central processing unit 14. The central processing unit) 14 includes the units 11 to 13.
control to create and output synthetic data.

In FIG. 3, 2o is a receiving device, and a transmission control unit 21. A short-cycle data output unit 22, a long-cycle data output unit 23, and a central processing unit 24 are connected and configured as shown in the figure.

Here, the transmission control unit 21 inputs the composite data sent from the sending device 10. The short-cycle data output unit 22 removes the long-cycle data from the sent composite data and outputs the short-cycle data Al, 1-A that has been found to be error-free in the parity check. The long-period data output unit 23 extracts and synthesizes long-period data from the sent composite data, searches for the beginning by detecting data for synchronization, and outputs long-period data B1 to B1 for each bit number of the long-period data.
Output Bm. The central processing unit 24 controls the units 21 to 23 to extract short-cycle data A from the composite data.
1 to A, obtain long-period data Bl to Bm.1 FIG. 4 shows the sending device 10 shown in FIG. Short-cycle data, long-cycle data handled by the receiving device 20 shown in FIG.
Indicates the format of synthetic data.

In the figure, D4 is data A! D5 is data B1 to B, which is long-period data and is transmitted using the sending device and receiving device. The synchronization data 1.2 at the beginning of the long-period data D5 is data generated by the sending device, and is used when the receiving device reproduces the long-period data.

D6 is composite data composed of short-cycle data A1 to A11 with a parity pitch (P) added to the beginning of each data, and a part of long-cycle data D5, and is sent from the sending device. Long period data D5 is "1 + L2 +...
・Lx (Ll in Figure 4).

L21..., L is decomposed into l bits), and each time short cycle data D4 is sent out, Ll + r,,, +...,
L, is added to the short-cycle data D4 one by one and sent out, and in the composite data D6 of FIG. Ll, which is a part of data l, is added. Therefore, as a result, short-cycle data D4 is added six times (t is L
The long-period data D5 is sent out once each time it is sent out (number of I+i, 2+...L).

Note that the periodic data TI' is not limited to 1 bit, but is within the range of the number of pits obtained by subtracting the number of bits of data transmitted as short-period data from the number of bits that can be transmitted within one sample. Get any number of bits in .

Next, the processing steps of Fig. 2 and Fig. 3 (1 (medium heat processing unit not shown) 14.24 of this embodiment will be explained according to the flowchart shown in Fig. 5 and Fig. 6, -1-). do.

FIG. 5 is a flowchart v-) showing the processing procedure of the central processing unit 14 shown in FIG. Processing steps 30-3
I will explain about 9 to Akishita. The short-period data D4 shown in FIG. 4 is inputted via the short-period data D4 shown in FIG. 2 (step 30). Next, the counter l is incremented by 1 (step 31).

The value of the counter l determines the number of bits of the long-period data (8 pits for D5 shown in FIG. 4). If they are the same, proceed to step 33; if not, proceed to step 38 (step 32).

If they are the same, counter 1 is cleared and counter 2 is incremented by 1 (step 033). Next, it is determined whether the value of counter 2 is the same as the number of long-cycle data (8m+2). If they are the same, proceed to step 035; if they are not the same, proceed to step 37 (step 34). If they are the same, counter 2 is incremented by 1, and the synchronization date, month, and 2 are created (step 35).

Long cycle data B1 to Bn1 shown in FIG. 2]
Input via data input crab unit 12, step 35
The synchronization data created in 1.2'a = 4J and the fourth
Create long-period data D5 shown in the figure (Step 1).

Zo36). Long side created in step 36” data D5
One data minute' of is set for decomposition, r<sofa (BUF) K (step 37). The first 1 bits are extracted from the decomposition BUF and synthesized with the short-cycle data D4 obtained in step 30, and 9-item bits are added to create synthesized data D6 shown in FIG. 4 (step 38).
. The composite data D6 created in step 38 is outputted via the transmission control unit 13 shown in FIG.
Return to step 039.

By sequentially repeating the processing of steps 30 to 39, it is possible to create and send out the composite data D6.

FIG. 6 is a flowchart showing the processing procedure of the central processing unit 24 shown in FIG. Processing steps 40-5
6 will be explained below. The composite data D6 is taken in via the transmission control unit 21 of the receiving device shown in FIG. 3 (step 40). In step 40, import the synthesized data D6 into short J leap period data and long period data (fourth
In the case of composite data D6 shown in the figure, it is separated into L+) (
Step 41).

Next, check the flags. (The flag is initially in a reset state.) If the flag is reset, the process proceeds to step 43, and if it is set, the process proceeds to step 046 (step 42). If the flag is reset, step 4
After synthesizing the data extracted in step 1 bit by bit, it is determined whether the data is synchronization data l of periodic data D6.

If the synchronization data l is ", go to step 44. If the synchronization data is not l, go to step 5G, and then step 0.
40 to 43156 are repeated to synthesize synchronization data 1 (step 43). Check result synchronization data
If so, a flag is set (step 44), and the value of counter M is incremented by 1 (step 45). The extraction of the synchronization data 1 is completed below, and the process moves on to the extraction of the cycle data 2 and the data B 1 - B . First, the value of the counter N is set to zero. 11 is long period data D5
Glue 1. L2, . It is determined whether the value of the counter N matches the number of bits of the long period data D5. If they match, the process proceeds to step 48; if they do not match, the process proceeds to step 56 (step 47). If they match, clear the contents of counter N in step 48.
), and increments the value of counter M by 1 (step 49).

In step 41, one bit of the long-period data sequentially extracted from the composite data D6 is synthesized, and it is determined whether the synthesized data is the synchronization data 2. If the data is synchronization data 2, the process goes to step 56; if it is not synchronization data 2, the process goes to step 51 (step 7°50). If the synchronization data is not 2, it is determined whether the value of the counter M is 1 or less. If the value of M is less than or equal to 1, the process moves to step 54, and the process starts from extracting the synchronization data l again. If the value of M is 2 or more, the synchronization data 1.2 will be extracted, so the process moves to step 52 and the long period data B1 to Bm are restored (step 51).

If the value of M is 2 or more, one data portion of the long-period data D5 is restored and outputted every l data via the long-period data output unit 23 shown in FIG.
2). Next, it is determined whether the value of the counter M matches the data number (Bm+2) of the long period data D5. If they match, it means that all of the long-cycle data D50B1-Bm have been output, and the process moves to step 54 to perform the next cycle of processing.

If they do not match, the process moves to step 56, and thereafter the remaining data is extracted (step 53). If they match, reset the flag (step 54).

The value of the counter M is cleared (step 55).The short-cycle data D4 obtained by separation in step 41 is outputted via the short-cycle data output unit 22 shown in FIG. 3 (step 56).Step 40 By sequentially turning .about.56 green, it is possible to output the short period data D4 and the long period data 31-13 from the composite data D6.

As described above, in this embodiment, the output device combines short-cycle data with n-bit long-cycle data and outputs the combined result. On the receiving device side, the short-cycle data and long-cycle data bits are decomposed, the n-bit long-cycle data is rearranged after a number of sets of samples, and the long-cycle data is restored by locating the beginning by detecting synchronized data. Therefore, the reliability of long-period data is high, and it is possible to transmit short-period data using one transmission path without interfering with the transmission efficiency of short-period data.

Although the following explanation deals with two types of digital data having different transmission timings, the present invention is not limited to this, and can be similarly implemented even when transmitting more data. In this case, the data transmitted at the timing with the highest transmission speed can be used as short-cycle data, and the other data can be used as long-cycle data, as described above.

(Effects of the Invention) The present invention has the advantage that even when short-cycle data and long-cycle data are transmitted using the same transmission path, the short-cycle data can be transmitted without reducing the transmission efficiency. . The present invention can be used, for example, for seismic waveform data (short-period data), crustal deformation, temperature, water level, atmospheric pressure, tide level, etc.
Examples include transmission/reception processing for synthesizing distortion, tilt, various monitoring data, etc. (long-period data).

[Brief explanation of drawings]

MTr Figure 1 is a conventional transmission format, Figure 2 is a block diagram of a transmitter according to an embodiment of the present invention, Figure 3 is a block diagram of a receiver according to an embodiment of the present invention, and Figure 4 is a block diagram of a receiver according to an embodiment of the present invention. 5 is a flowchart of the processing of the transmitting device shown in FIG. 2, and FIG. 6 is a flowchart of the processing of the receiving device shown in FIG. 3. IO...Sending device, 11...Short cycle data input crab unit, 12...Long cycle data input crab unit, 13゜2
DESCRIPTION OF SYMBOLS 1...Transmission control unit, 14.24...Central processing unit, 20...Receiving device, 22...Short period data output unit, 23...-Long period data output unit, 7. Figure 22, 10 #3UZJ

Claims (2)

[Claims] (1) A sending device that combines two or more types of digital data with different transmission timings into one data and sends it, and a sending device that receives the sent data and converts it into the two or more types of data.
In a data transmission method performed using an original receiving device, the sending device adds synchronization data to each data other than the data sent at the fastest transmission timing among the two or more types of digital data. is divided at a predetermined ratio, the divided data is combined with the data transmitted at the fastest transmission timing and transmitted sample by sample, and the receiving device receives the transmitted data and transmits the data transmitted at the fastest transmission timing. It is characterized by separating the data sent out at a fast transmission timing and the said data combined therewith, receiving a plurality of samples of the separated data, and converting the synchronization data into the detected four-element data. data transmission method. (2) Claim 1, wherein the division is the number of bits that can be transmitted within one sample minus the number of bits of data transmitted at the fastest transmission timing. data transmission method.