JPS605569A - Nonvolatile semiconductor memory - Google Patents
Nonvolatile semiconductor memoryInfo
- Publication number
- JPS605569A JPS605569A JP11353683A JP11353683A JPS605569A JP S605569 A JPS605569 A JP S605569A JP 11353683 A JP11353683 A JP 11353683A JP 11353683 A JP11353683 A JP 11353683A JP S605569 A JPS605569 A JP S605569A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- gate electrode
- insulating film
- film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract 7
- 239000010703 silicon Substances 0.000 claims abstract 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000010408 film Substances 0.000 claims 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 230000015654 memory Effects 0.000 abstract description 13
- 238000009413 insulation Methods 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- 230000014759 maintenance of location Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Abstract
Description
【発明の詳細な説明】
本発明は浮遊ゲートを有する不揮発性半導体メモリに関
する。特に電荷を蓄積する浮遊ゲートとその周囲の絶縁
膜の構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-volatile semiconductor memory having a floating gate. In particular, it relates to the structure of a floating gate that accumulates charge and an insulating film around it.
従来の浮遊ゲート型不揮発性半導体メモリの基本となる
構造を第１図に示す。１はＰ型半導体基板、２はソース
領域、６はドレイン領域、４は薄い第１の絶縁膜、５は
浮遊ゲート電極、６は第２の絶縁膜、７は制御ゲート電
極である。周知のように不揮発性半導体メモリに要求さ
れる最も重要な特性は記憶の保持特性である。即ち、一
度浮遊ゲート電極に蓄えられた電荷がそこに留まる時１
１４Ｊの長いものほど良いメモリと言うことになる。し
かし、不揮発性半導体メモリといえども浮遊ゲート電極
５に蓄えられた電子は決して不変ではなく、時間の経過
とともに少しずつ流れ出しリークしてしまう。つまり経
時変化をしてしまう。これらの揮発する電子は、大部分
が絶縁膜６を通り抜は制御ゲート電極７へと流れ出して
しまう。一方、浮遊ゲート電極５直下の薄い絶縁膜から
はほとんどリークしない。この違いは絶縁膜の材質の差
にある。従来の浮遊ゲート型メモリにおいては薄い絶縁
膜４は基板１の単結晶シリコンを熱酸化して得られる酸
化膜より成り、第２の絶縁膜６はポリシリコンを熱酸化
して得られる酸化膜より成っていたからである。ポリシ
リコンの熱酸化膜は基板の単結晶シリコンの酸化膜に比
べて２分の１程度の耐圧しかなく、リーク′亀流も単結
晶シリコンの酸化膜の１０２〜１０４倍も流れてしまい
、不揮発性半導体メモリの絶縁膜としては不充分な特性
しか備えていなかった。製造上でも製品の歩留りを下げ
る要因の１つになっていた。そこでこれらの欠点を逃れ
るために第２の絶縁膜乙の厚さを大きくとるのであるが
、絶縁膜６のみが厚いことは制御ゲート電極７と浮遊ゲ
ート電極５の間の容量結合を小さくシ、より高い書き込
み電圧を必要としてしまう。このことは書き込み電圧の
低減と高集積化を不可能にし、耐圧を上げるため素子の
設計マージンを大きくとらなければいけないことを意味
する。FIG. 1 shows the basic structure of a conventional floating gate nonvolatile semiconductor memory. 1 is a P-type semiconductor substrate, 2 is a source region, 6 is a drain region, 4 is a thin first insulating film, 5 is a floating gate electrode, 6 is a second insulating film, and 7 is a control gate electrode. As is well known, the most important property required of a nonvolatile semiconductor memory is memory retention property. That is, when the charge once stored in the floating gate electrode remains there, 1
The longer 14J, the better the memory. However, even though it is a non-volatile semiconductor memory, the electrons stored in the floating gate electrode 5 do not remain constant, and gradually flow out and leak as time passes. In other words, it changes over time. Most of these volatilized electrons pass through the insulating film 6 and flow out to the control gate electrode 7. On the other hand, there is almost no leakage from the thin insulating film directly under the floating gate electrode 5. This difference is due to the difference in the material of the insulating film. In a conventional floating gate memory, the thin insulating film 4 is made of an oxide film obtained by thermally oxidizing the single crystal silicon of the substrate 1, and the second insulating film 6 is made of an oxide film obtained by thermally oxidizing polysilicon. This is because it was completed. The thermal oxide film of polysilicon has only about half the withstand voltage of the single crystal silicon oxide film of the substrate, and the leakage current is 102 to 104 times that of the single crystal silicon oxide film, making it non-volatile. It had insufficient properties as an insulating film for semiconductor memories. This was one of the factors that lowered product yields in manufacturing. Therefore, in order to avoid these drawbacks, the thickness of the second insulating film B is increased, but the fact that only the insulating film 6 is thick reduces the capacitive coupling between the control gate electrode 7 and the floating gate electrode 5. This requires a higher write voltage. This makes it impossible to reduce the write voltage and achieve high integration, and means that a large design margin must be provided for the device in order to increase the withstand voltage.
以上に記したようにポリシリコンよりなる浮遊ゲート電
極とポリシリコンを熱酸化して形成した絶縁膜を持つ不
揮発性半導体メモリは素子の設計・製造上ひいては高集
積で低電圧動作可能な記憶素子の設計・製造上の重大な
欠点を有していた。As mentioned above, non-volatile semiconductor memory, which has a floating gate electrode made of polysilicon and an insulating film formed by thermally oxidizing polysilicon, is suitable for device design and manufacturing, as well as for storage elements that are highly integrated and can operate at low voltages. It had serious design and manufacturing flaws.
本発明の目的は上記の欠点を解消するためになされたも
ので、記憶保持特性がよく、シかも低電圧で書き込むこ
とができ、高集積化可能な不揮発性半導体メモリを得る
ことにある。SUMMARY OF THE INVENTION An object of the present invention has been made to eliminate the above-mentioned drawbacks, and is to provide a nonvolatile semiconductor memory that has good memory retention characteristics, can be written to at low voltage, and can be highly integrated.
以下本発明を図面および実施例によって詳細に説明する
。第２図は本発明を適用した基本的な第１の実施例を表
わす断面図である。１１はＮ型半導体基板、１２は酸化
物、窒化物等の薄い絶縁膜１１３は単結晶あるいは単結
晶に近いシリコンよりなる浮遊グー）％＋、ｍ、１４は
単結晶あるいは単結晶に近いシリコンから熱酸化により
形成された絶縁膜、１５は制御ゲート電極である。単結
晶あるいは単結晶に近いシリコンは０ＶＤＬ、たポリシ
リコンをレーザアニール・ランプアニール・ヒータアニ
ール等の手段によって簡単に得られる。The present invention will be described in detail below with reference to drawings and examples. FIG. 2 is a sectional view showing a basic first embodiment to which the present invention is applied. 11 is an N-type semiconductor substrate, 12 is a thin insulating film 113 made of oxide or nitride, etc., is a floating gas made of single crystal or near-single crystal silicon, and 14 is made of single crystal or near-single crystal silicon. An insulating film 15 formed by thermal oxidation is a control gate electrode. Single-crystal or near-single-crystal silicon can be easily obtained at 0 VDL, and polysilicon can be easily obtained by laser annealing, lamp annealing, heater annealing, or the like.
上記構成において、制御ゲート電極１５がＮ型半導体基
板１１に対して正になるように電圧を印加すると、電圧
が充分高いならば電子は絶縁膜１２を通り抜けて浮遊ゲ
ート電極１３に蓄えられる。即ち、情報が記憶される。In the above configuration, when a voltage is applied so that the control gate electrode 15 becomes positive with respect to the N-type semiconductor substrate 11, electrons pass through the insulating film 12 and are stored in the floating gate electrode 13 if the voltage is high enough. That is, information is stored.
この時絶縁膜１４は単結晶あるいは単結晶に近いシリコ
ンを熱酸化して形成された酸化物より成るので、絶＃性
が非常に侵れており、記憶保持特性の良い長寿命の不揮
発性半導体メモリとなっている。そこで当然製造上の歩
留りも向上する。At this time, the insulating film 14 is made of an oxide formed by thermally oxidizing single-crystal or near-single-crystal silicon, so the insulating film 14 has very poor integrity and is a long-life nonvolatile semiconductor with good memory retention characteristics. It is a memory. Naturally, therefore, the manufacturing yield is also improved.
第３図は本発明の第２の実施例を示す断面図である。２
１はＰ型半導体基板、２２はソース領域、２３はドレイ
ン領域、２４は薄い絶縁膜、２５は単結晶あるいは単結
晶に近いシリコンより成る浮遊ゲート電極、２６は単結
晶あるいは単結晶に近イシリコンを熱酸化して形成した
絶ｉ膜、２７は選択ゲート電極である。本実施例におい
ては、第１の実施例と同様の効果ばかりでなく、絶縁膜
２６の絶縁性が優れているため膜厚を薄くしても充分な
絶縁性を得られるため、膜厚を薄くしてオフセットゲー
トの長さ２９を小さくすることができく）書き込み効率
の増大および高集積化か可能となる。FIG. 3 is a sectional view showing a second embodiment of the present invention. 2
1 is a P-type semiconductor substrate, 22 is a source region, 23 is a drain region, 24 is a thin insulating film, 25 is a floating gate electrode made of single crystal or near single crystal silicon, and 26 is made of single crystal or near single crystal silicon. An insulating film 27 formed by thermal oxidation is a selection gate electrode. In this embodiment, not only the same effects as in the first embodiment are obtained, but also sufficient insulation properties can be obtained even if the film thickness is made thin because the insulation film 26 has excellent insulation properties. (This allows the length 29 of the offset gate to be reduced, thereby making it possible to increase write efficiency and achieve high integration.)
第４図は本発明の第３の実施例を示す断面図である。３
１はＰ型半導体基板、６２はソース領域、６３はドレイ
ン領域、３４は薄い絶縁膜、３５は単結晶あるいは単結
晶に近いシリコンよりなる浮遊ゲート電極、６６は単結
晶あるいは単結晶に近いシリコンを熱酸化して形成した
絶縁）ｍ、３ｙは制御ゲート電極である。本実施例にお
いても、絶縁膜３６の絶縁性が優れているため記憶保持
特性が良く、長寿命のメモリとなっている。FIG. 4 is a sectional view showing a third embodiment of the present invention. 3
1 is a P-type semiconductor substrate, 62 is a source region, 63 is a drain region, 34 is a thin insulating film, 35 is a floating gate electrode made of single crystal or near single crystal silicon, and 66 is made of single crystal or near single crystal silicon. Insulators) m and 3y formed by thermal oxidation are control gate electrodes. In this embodiment as well, since the insulating film 36 has excellent insulation properties, the memory retention characteristics are good and the memory has a long life.
以上３つの実施例について説明したが、本発明の適用は
上記の実施例に限るものでないことは言うまでもない。Although the above three embodiments have been described, it goes without saying that the application of the present invention is not limited to the above embodiments.
浮遊ゲート電極とその周囲に絶縁物層を有する半導体素
子であれば適用することができる。Any semiconductor device having a floating gate electrode and an insulating layer around it can be applied.
以上述べたように、本発明による不揮発性半導体メモリ
は、浮遊ゲート電極上の絶縁物層に単結晶あるいは単結
晶に近いシリコンを熱酸化して形成した酸化膜を用いて
いるため、記憶保持特性に優れ長寿命であり、素子形状
によっては書き込み効率の増大、高集積化が可能となる
といった様々な利点を持ち、製造上も絶縁膜に起因する
バラツキを少なく抑え、歩留りを上げる−ことができる
。As described above, the nonvolatile semiconductor memory according to the present invention uses an oxide film formed by thermally oxidizing single crystal or near-single crystal silicon for the insulating layer on the floating gate electrode, so it has good memory retention characteristics. It has various advantages such as excellent performance and long life, increased writing efficiency and high integration depending on the element shape, and can reduce manufacturing variations caused by insulating films and increase yield. .
第１図は従来の浮遊ゲート型不揮発性半導体メモリの断
面図、第２図から第４図はそれぞれ本発明の第１から第
６の実施例を表わす断面図であるｉ 、２１．３１・・
・・・・Ｐ型半導体基板２．２２．３２・・・・・・ソ
ース領域３．２３．３３・・・・・・ドレイン領域４
、１２ 、２４ 、３４・・・・・・薄い絶縁膜！、５
、１３ 、２５ 、３５・・・・・・浮遊ゲート電極
６．１４，２６．６６・・・・・・絶縁ｊ漢７．１５．
３７・・・・・・制御ゲート電極１１・・・・・・Ｎ型
半導体基板
２７・・・・−・選択ゲート電極
２９・・・・・・オフセットゲートの長さ以 上
出願人 株式会社第二精工舎
第１図
第２図
／ｌ ＩＪ ／１
第３図
第４図FIG. 1 is a sectional view of a conventional floating gate type nonvolatile semiconductor memory, and FIGS. 2 to 4 are sectional views showing first to sixth embodiments of the present invention, respectively.
...P-type semiconductor substrate 2.22.32...Source region 3.23.33...Drain region 4
, 12 , 24 , 34...thin insulating film! , 5
, 13, 25, 35...Floating gate electrode 6.14, 26.66...Insulation 7.15.
37...Control gate electrode 11...N-type semiconductor substrate 27...-Selection gate electrode 29...Length of offset gate or more Applicant: Co., Ltd. No. Niseikosha Figure 1 Figure 2/l IJ/1 Figure 3 Figure 4
Claims (3)
縁膜と、前記薄い第１の絶縁膜上に設けられた浮遊ゲー
ト電極と、前記浮遊ゲート電極上に設けられた第２の絶
縁膜と、前記第２の絶縁膜上に少なくともその一部が前
記浮遊ゲート電極上に位置するように設けられた制御ゲ
ート電極とからなる半導体装置において、前記浮遊ゲー
ト電極が単結晶あるいは単結晶に近いシリコン薄膜より
なり、前記第２の絶縁膜が熱酸化膜であることを特徴と
する不揮発性半導体メモリ。(1) A thin first insulating film provided in a region on a semiconductor substrate, a floating gate electrode provided on the thin first insulating film, and a second insulating film provided on the floating gate electrode. and a control gate electrode provided on the second insulating film so that at least a part of the control gate electrode is located on the floating gate electrode, wherein the floating gate electrode is a single crystal or a single crystal. 1. A nonvolatile semiconductor memory comprising a thin silicon film, wherein the second insulating film is a thermal oxide film.
アニール・ランプアニールＳヒータアニールにより形成
された単結晶あるいは単結晶に近いシリコン薄膜である
ことを特徴とする特許請求の範囲第１項記載の不揮発性
半導体メモリ。(2) The nonvolatile device according to claim 1, wherein the floating gate electrode is a single crystal or near-single crystal silicon thin film formed from polysilicon by beam annealing, lamp annealing, and S-heater annealing. semiconductor memory.
ニール・ランプアニール・ヒータアニールにより形成さ
れた単結晶あるいは単結晶に近いシリコンを熱酸化して
形成した二酸化シリコン膜であることを特徴とする特許
請求の範囲第１項または第２項記載の不揮発性半導体メ
モリ。(3) The second insulating film is a silicon dioxide film formed by thermally oxidizing single-crystal or near-single-crystal silicon formed from polysilicon by beam annealing, lamp annealing, and heater annealing. A nonvolatile semiconductor memory according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11353683A JPS605569A (en) | 1983-06-23 | 1983-06-23 | Nonvolatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11353683A JPS605569A (en) | 1983-06-23 | 1983-06-23 | Nonvolatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS605569A true JPS605569A (en) | 1985-01-12 |
Family
ID=14614805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11353683A Pending JPS605569A (en) | 1983-06-23 | 1983-06-23 | Nonvolatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605569A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4938964A (en) * | 1987-12-09 | 1990-07-03 | Showa Denko Kabushiki Kaisha | External dermatological composition |
| US5360756A (en) * | 1993-01-20 | 1994-11-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having a monocrystal silicon layer |
| JP2002150356A (en) * | 2000-11-13 | 2002-05-24 | Japan Cash Machine Co Ltd | Banknote handling device |
-
1983
- 1983-06-23 JP JP11353683A patent/JPS605569A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4938964A (en) * | 1987-12-09 | 1990-07-03 | Showa Denko Kabushiki Kaisha | External dermatological composition |
| US5360756A (en) * | 1993-01-20 | 1994-11-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having a monocrystal silicon layer |
| JP2002150356A (en) * | 2000-11-13 | 2002-05-24 | Japan Cash Machine Co Ltd | Banknote handling device |
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