A7 B7 447 1 2 4 6 12〇twf.doc/〇〇8 五、發明說明（（） 本發明係有關於一種半導體記憶體’特別是有關於一 種分離式閘極快閃記憶體（Split-Gate Flash Memory)。 在近1980年未期，半導體界發展出電氣抹除式可編程 唯讀記憶體（Electrically Erasable Programming R0M’ £EPR0M)。此爲新一代具有低成本、高密度記憶體市場之 記憶體。術語，，快閃，，是使用來描述以一次來程式化或抹除 整個記憶體陣列。快閃記憶體是藉由將熱電子射入到汲極 邊緣來程式化以及藉由從浮置閘極（Floating Gate)至源 極之福勒努德漢隧道效應（Fowier_Nordheim Tunneling) 來實施抹除。 因爲快閃記憶體之記憶單元可維持所儲存之資料，而 不需重新補充（Refreshing)，所以將快閃記憶體歸類成爲 非揮發性記憶體。大部份昔知快閃記憶體在一個記憶體單 元只能儲存單一位元。換句話說，記憶體單兀可儲存1 或”0”位元資料。 許多快閃記憶體製造者使用薄氧化浮置製程來製造電 氣抹除式可編程唯讀記憶體。如第一圖所示，基本單元是 由存取記憶體與一雙多晶矽儲存單元所組成，其中雙多晶 矽儲存單元具有一浮置閘FG以及一控制閘極CG，控制閘 極CG位於浮置閘FG之上方，它們之間具有二氧化矽層。 儲存電晶體之程式化是藉由將電子以福勒努德漢隧道效應 穿透電晶體閘極與汲極間之一薄氧化層以來完成。此薄隨 道氧化層一般大約是90埃。上述結構之缺點在於：當控制 閘極接地時，會將記憶體單元抹除成一負啓始電壓以及汲 4 本紙張尺度適用中國國家標準（CNS)A4規格<210 x 297公爱） ,Ji------訂---------線 (請先閱讀背面之注意事項再填寫本頁)A7 B7 447 1 2 4 6 12〇twf.doc / 〇〇8 V. Description of the invention (() The present invention relates to a semiconductor memory ', especially to a split gate flash memory (Split-Gate Flash Memory). In the late 1980s, the semiconductor industry developed Electrically Erasable Programming ROM (EPR0M). This is a new generation of memory with low cost and high density memory market. The term, flash, is used to describe programming or erasing the entire memory array at one time. Flash memory is programmed by firing hot electrons onto the edge of the drain and by floating Fowier_Nordheim Tunneling from the Floating Gate to the source to implement erasure. Because the flash memory unit can maintain the stored data without refreshing Therefore, flash memory is classified as non-volatile memory. Most flash memories used to store only a single bit in a memory unit. In other words, a memory unit can store 1 bit. Or "0" bit data. Many flash memory manufacturers use a thin oxide floating process to make electrically erasable programmable read-only memory. As shown in the first figure, the basic unit consists of access memory and It consists of a pair of polycrystalline silicon storage units, where the dual polycrystalline silicon storage unit has a floating gate FG and a control gate CG, and the control gate CG is located above the floating gate FG with a silicon dioxide layer between them. The programming is accomplished by passing electrons through a thin oxide layer between the gate and the drain of the transistor with the Fowler-Nudehan tunnel effect. This thin oxide layer is generally about 90 angstroms. The disadvantages of the above structure The reason is that when the control gate is grounded, the memory unit will be erased to a negative starting voltage and drawn. This paper size applies the Chinese National Standard (CNS) A4 specification < 210 x 297 public love), Ji ---- --Order --------- line (please read the notes on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 447124 A7 6120twf.doc/008 gy 五、發明說明（*7 ) 極與源極間之通道會有漏電電流導通。再者，昔知記憶體 需要一約400微安~1毫安之程式化電流。實際運用上，則 需要有一非常大之充電泵來供應足夠的電流。 第2圖係顯示出另一昔知設計之分離式閘極快閃記 憶體單元。因爲縱使對浮置閘極過度抹除，在通道導通 時，控制閘極亦可獲得偏壓，其中控制閘極覆蓋源極與 汲極間之另外部份通道，所以分離式閘極單元可去除過 度容易之敏感度。此設計之缺點在於：會增加記憶體單元 之大小以及記憶體單元製造會遭遇到對準敏感度之問 題。 另一型態之分離式閘極記憶體單元使用所謂源極邊 緣射入技術，其可使程式化期間通道電流爲最小，並且 可藉由一單一電源供應器，使用一嵌入式晶片泵電路來 提供適當電流。但是，在此設計中亦存在有一些缺點。 首先，多晶矽層1(浮置閘極）與多晶矽層2(控制閘極）無 法對準會造成單元電流不對稱。此外，此種設計容易導 致貫穿以及很難縮小記憶體單元尺寸之問題。第二，抹 除機構會減少電子陷入（Electron Trapping)以及降低容 忍性能（Endurance Performance)。 在美國專利號碼5,614,746(Hong等人）、美國專利 號碼 5,674,767(Lee等人）、美國專利號碼 5,789,296(Suiig等人）以及其所引用之參考資料中，描 述這些有關分離式快閃記憶體單元之不同昔知方法。 因此，需要一種可以克服上述問題之新設計快閃記 5 (諳先閲讀背面之注意事項再填寫本頁) 訂· --線. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6120twf.doc/008 五、發明說明（1 ) 憶體單元。 本發明揭露出一形成於一半導體基底之分離式閘極快 閃記憶體單元。上述記憶體單元包括：一深η-井區，其形 成於上述基底中；一 Ρ-井區，其形成於上述深η-井區中； 一選擇閘極結構，其形成於上述Ρ-井區上，其中上述選擇 閘極結構包括：一疊閘極層、一多晶砂層以及一頂部氧化 層；一隧道氧化層，其與上述控制閘極結構相鄰；一浮置間 極，其形成於上述選擇閘極結構上方，並至少延伸至部份 上述隧道氧化層；一源極，其形成於上述Ρ-井區中，並與 上述浮置閘極相鄰；以及一汲極，其形成於上述Ρ-井區中， 並與上述選擇閘極結構相鄰。 爲了使上述本發明之優點能更加容易了解，下文特列 舉出較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖係顯示出一種昔知之堆疊閘極快閃記憶體單元; 第2圖係顯示出一種昔知之分離式閘極快閃記憶體單 元；以及 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) --線· 第3-6圖係顯示出依據本發明之形成一種快閃記憶體 單元之示意剖面圖。 符號說明： 101-ρ型矽基底； 103-深η-井區； 6 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） 447124 A7 6120twf.d〇c/008 gy 五、發明說明) 105-p-井區； 107-閛極氧化層； (請先閱讀背面之注意事項再填寫本頁) 109-第一多晶矽層； 111 -高溫氧化層； 113-選擇閘極結構； 401-邊牆間隔物； 403-隧道氧化層； 501-浮置閘極； 601-形成一內連介電層； S-源極；以及 D-汲極。 窗施例 參考第3圖，提供一 p型矽基底101。一深η-井區103 形成於基底101上。一 Ρ-井區105形成於深η-井區103 中。上述結構可使用傳統佈植技術來形成。 經濟部智慧財產局員工消費合作社印製 接下來，在基底101表面形成一閛極氧化層107。閘 極氧化層107之厚度最好大約在40-120埃之間，並且是 藉由熱氧化（Thermal Oxidation)或化學氣相沉積 (Chemical Vapor Deposition, VCD)所形成。一第一多晶 矽層109形成於閘氧化層107頂部，上述第一多晶矽層109 之厚度最好在1500-4000埃之間。接下來’ 一高溫氧化層 (以下亦稱爲頂部氧化層）111形成於第一多晶矽層丨〇9頂 部，其中第一多晶砂層109之厚度最好爲100埃。 7 本紙張尺i適用中國國家&準（CNS>A4規格（2J〇x297公釐) 447124 經濟部智慧財產局員Η消費合作社印製 A7 6120twf.d〇c/008 B7 五、發明說明（匕） 然後，圖案化及蝕刻上述閘極氧化層107、第一多晶 矽層109以及高溫氧化層111，以形成如第3圖所示之選 擇閘極結構113。上述選擇閘極結構113將連接到一字元 線，並當做快閃記憶體單元之控制閘極。 接下來，參考第4圖，邊牆間隔物401是形成於選擇 閘結構113之邊側。如同傳統形成間隔物之方法，邊牆間 隔物401可藉由沉積一高溫度氧化層，然後實施回蝕刻製 程來形成。在形成間隔物401之後，形成一隧道氧化層403 於選擇閘極結構113間所暴露之基底101上。 接下來，參考第5圖，沉積厚度約在1500-400埃間之 一第二多晶矽層。然後，圖案化及蝕刻上述第二多晶矽層， 以分離式閘極形式形成浮置閘極501。此浮置閘極501至 少與選擇閘極結構113部份重疊，並經過選擇閘極結構113 而延伸至隧道氧化層403上方。 最後’參考第6圖，使用離子佈植技術，形成汲極與 源極區域。特別是在一高溫驅入周期（High Temperature Drive-In Cycle)前立刻形成源極界面，以便能與浮置閘 極501有足夠之重疊，也因而使源極界面比汲極界面深。 在程式化期間，源極界面亦當做控制閘極。在上述驅入周 期後，使用傳統面罩技術，來形成汲極。特別値得注意的 是，在兩相鄰快閑記憶體單兀間，形成一共源極S。在最 後一步驟中’形成一內連介電層（Int er 1 ayer Di e 1 ec t r i c , ILD)601於上述浮置閘極上方，以確保其與任何導電結構 電性隔離。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 447124 A7 6120twf.doc / 008 gy 5. Description of the invention (* 7) The leakage current will flow through the channel between the electrode and the source. Moreover, the memory of the past requires a programmed current of about 400 microamperes to 1 milliamp. In practice, a very large charge pump is required to supply sufficient current. Fig. 2 shows another conventional design of a separate gate flash memory unit. Because even if the floating gate is over-erased, the control gate can also be biased when the channel is turned on. The control gate covers another part of the channel between the source and the drain, so the separate gate unit can be removed. Excessive sensitivity. The disadvantage of this design is that it will increase the size of the memory cell and the memory cell manufacturing will encounter the problem of alignment sensitivity. Another type of discrete gate memory unit uses so-called source edge injection technology, which can minimize channel current during programming, and can use a single power supply and an embedded chip pump circuit to Provide proper current. However, there are some disadvantages in this design. First, the failure to align the polysilicon layer 1 (floating gate) with the polysilicon layer 2 (control gate) will cause cell current asymmetry. In addition, this design easily leads to problems of penetration and difficulty in reducing the size of the memory cell. Second, the erasure mechanism will reduce Electron Trapping and reduce Endurance Performance. U.S. Patent No. 5,614,746 (Hong et al.), U.S. Patent No. 5,674,767 (Lee et al.), U.S. Patent No. 5,789,296 (Suiig et al.), And references cited therein describe these related flash memory cells. Different previous methods. Therefore, a new design flash 5 is needed that can overcome the above problems (谙 Please read the notes on the back before filling this page). (CNS) A4 specification (210 X 297 mm) 6120twf.doc / 008 5. Description of the invention (1) Memory unit. The invention discloses a discrete gate flash memory cell formed on a semiconductor substrate. The memory unit includes: a deep η-well region formed in the base; a P-well region formed in the deep η-well region; and a selective gate structure formed in the P-well. On the area, the selected gate structure includes: a stack of gate layers, a polycrystalline sand layer, and a top oxide layer; a tunnel oxide layer adjacent to the control gate structure; and a floating intermediate electrode, which forms Above the selected gate structure and extending to at least a portion of the tunnel oxide layer; a source electrode formed in the P-well region and adjacent to the floating gate electrode; and a drain electrode formed In the P-well region, and adjacent to the selection gate structure. In order to make the advantages of the present invention more easily understandable, the preferred embodiments are listed below and described in detail with the accompanying drawings as follows: Brief description of the drawings: Figure 1 shows a stack gate known in the past Extreme flash memory unit; Figure 2 shows a previously known discrete gate flash memory unit; and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) -Lines. Figures 3-6 are schematic cross-sectional views showing the formation of a flash memory cell according to the present invention. Explanation of symbols: 101-ρ type silicon substrate; 103-deep η-well area; 6 This paper size is applicable to China National Standard (CNS) A4 specification (2〗 0 X 297 mm) 447124 A7 6120twf.d〇c / 008 gy V. Description of the invention) 105-p-well area; 107-pyridium oxide layer; (Please read the precautions on the back before filling this page) 109-first polycrystalline silicon layer; 111-high temperature oxide layer; 113-selection Gate structure; 401-side wall spacer; 403-tunnel oxide layer; 501-floating gate; 601-form an interconnected dielectric layer; S-source; and D-drain. Window Example Referring to FIG. 3, a p-type silicon substrate 101 is provided. A deep n-well region 103 is formed on the substrate 101. A P-well region 105 is formed in the deep n-well region 103. The above structures can be formed using conventional implantation techniques. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, a pole oxide layer 107 is formed on the surface of the substrate 101. The thickness of the gate oxide layer 107 is preferably between about 40 and 120 angstroms, and is formed by thermal oxidation (Chemical Vapor Deposition, VCD). A first polycrystalline silicon layer 109 is formed on top of the gate oxide layer 107. The thickness of the first polycrystalline silicon layer 109 is preferably between 1500 and 4000 angstroms. Next, a high-temperature oxide layer (hereinafter also referred to as a top oxide layer) 111 is formed on the top of the first polycrystalline silicon layer. The thickness of the first polycrystalline sand layer 109 is preferably 100 angstroms. 7 This paper rule is applicable to China's national & standard (CNS) A4 specification (2J0x297 mm) 447124 Printed by A7, a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 6120twf.d〇c / 008 B7 V. Description of invention (dagger) Then, the gate oxide layer 107, the first polycrystalline silicon layer 109, and the high-temperature oxide layer 111 are patterned and etched to form a selected gate structure 113 as shown in FIG. 3. The selected gate structure 113 will be connected to A word line is used as the control gate of the flash memory cell. Next, referring to FIG. 4, a side wall spacer 401 is formed on the side of the selection gate structure 113. As in the conventional method of forming a spacer, the side The wall spacer 401 can be formed by depositing a high-temperature oxide layer and then performing an etch-back process. After the spacer 401 is formed, a tunnel oxide layer 403 is formed on the substrate 101 exposed between the selected gate structures 113. Then Next, referring to FIG. 5, a second polycrystalline silicon layer having a thickness of about 1500-400 Angstroms is deposited. Then, the second polycrystalline silicon layer is patterned and etched to form a floating gate in the form of a separate gate. 501. This floating gate electrode 501 to It rarely overlaps with the selected gate structure 113 and extends above the tunnel oxide layer 403 through the selected gate structure 113. Finally, referring to FIG. 6, the ion implantation technique is used to form the drain and source regions. Especially The source interface is formed immediately before a High Temperature Drive-In Cycle so as to have sufficient overlap with the floating gate 501, thus making the source interface deeper than the drain interface. During programming The source interface is also used as the control gate. After the above drive-in period, the traditional mask technology is used to form the drain. It is particularly important to note that a common source is formed between two adjacent fast free memory cells. S. In the last step, an interconnect dielectric layer (Inter 1 ayer Diec 1 tric, ILD) 601 is formed over the floating gate to ensure that it is electrically isolated from any conductive structure. 8 Paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
447124 經濟部智慧財產局員工消費合作社印製 A7 6120twf.doc/008 B7 五、發明說明（b ) 第6圖之記憶體單元之操作如下所示:447124 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 6120twf.doc / 008 B7 V. Description of the Invention (b) The operation of the memory unit in Figure 6 is as follows:
選擇閘極 汲極 源極 P -井區 深η-井區 程式化 1.5-2.0V 0V 9-12V 0V 0V 抹除 浮接 浮接 浮接 10-15V 10-15'， 讀取 Vcc 2V 0V 0V 0V 上述記憶體單元運用源極邊緣通道熱電子結構來程式 化。在程式化期間，使選擇閘極導通，並供應9-12V至源 極。將此電壓耦接浮置閘極501，以吸引通道載子，並使 其射入浮置閘極501。此分離式閘極記憶體單元使用源極 邊緣射入，因此程式化電流大約在1〇〇ηΑ-μΑ之間。此低 電流提供使用一嵌入式電流泵之多數記憶體單元程式化之 能力。 上述記憶體單元使用第一多晶矽層來做爲選擇閘極， 以及使用第二多晶矽層來做爲浮置閘極。此可提洪由第一 多晶矽層之大小所定義出之具有固定通道長度之選擇閘 極。因此，不會像昔知分離式閘極快閃技術中，在兩層多 晶矽層與一可變選擇閘極長度間發生貫穿之問題。 本發明之記憶體單元是從Ρ-井區來實施抹除，因此需 實施3-井區技術。在實施抹除期間，將10-15V供應至Ρ-井區與深η-井區。使汲極與源極爲浮接狀態，藉由福勒努 德漢隧道效應，將浮置閘極上之電子經由厚90埃之隧道 氧化層，從第二多晶矽層拉出。與昔知相比，此”通道抹 9 (請先閱讀背面之注意事項再填寫本頁) . --線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 447124 A7 6120twf.doc/008 gy 五、發明說明） 除”提供較佳的容忍性能。 在讀取操作期間，將Vcc供應至選擇閘極，以及2V電 壓洪應至汲極。由於使用第二多晶矽層做爲浮置閘極，所 以此記憶體單元可提供對稱記憶體單元電流。 ' 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 1------------ο',— — 訂—I!-線 (請先閱讀背面之注意事項再填寫本頁)Select gate drain source P-well area deep η-well area stylized 1.5-2.0V 0V 9-12V 0V 0V erase floating floating floating 10-15V 10-15 ', read Vcc 2V 0V 0V 0V The above memory cells are programmed using the source edge channel thermoelectronic structure. During programming, the select gate is turned on and supplies 9-12V to the source. This voltage is coupled to the floating gate 501 to attract the channel carriers and shoot it into the floating gate 501. This split gate memory cell uses source edge injection, so the stylized current is between 100nA and μA. This low current provides the ability to program most memory cells using an embedded current pump. The memory unit uses a first polycrystalline silicon layer as a selection gate, and uses a second polycrystalline silicon layer as a floating gate. This enhances the select gate with a fixed channel length as defined by the size of the first polycrystalline silicon layer. Therefore, the problem of penetration between the two polysilicon layers and a variable selection gate length does not occur as in the known split gate flash technology. The memory unit of the present invention is erased from the P-well area, so the 3-well area technology needs to be implemented. During the erasing period, 10-15V was supplied to the P-well area and the deep n-well area. With the drain and source terminals floating, the electrons on the floating gate electrode were pulled out of the second polycrystalline silicon layer through the tunnel oxide layer with a thickness of 90 angstroms by means of the Fullernudhan tunnel effect. Compared with previous knowledge, this "channel wipe 9 (please read the precautions on the back before filling in this page). --- line. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 447124 A7 6120twf.doc / 008 gy V. Description of the invention) Except for "providing better tolerance performance. During a read operation, Vcc is supplied to the selection gate and the 2V voltage flood should be to the drain. Since the second polysilicon layer is used as the floating gate, the memory cell can provide a symmetrical memory cell current. 'Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. 1 ------------ ο ', — — Order —I! -Line (Please read the notes on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)