JP2536686B2 - Non-volatile memory - Google Patents
Non-volatile memoryInfo
- Publication number
- JP2536686B2 JP2536686B2 JP2301389A JP30138990A JP2536686B2 JP 2536686 B2 JP2536686 B2 JP 2536686B2 JP 2301389 A JP2301389 A JP 2301389A JP 30138990 A JP30138990 A JP 30138990A JP 2536686 B2 JP2536686 B2 JP 2536686B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- control gate
- thin
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、電気的に書き込み、消去可能な不揮発性メ
モリ（以下、EEPROMという）に関するものである。The present invention relates to an electrically writable and erasable non-volatile memory (hereinafter referred to as EEPROM).
［従来の技術］ 近年、殆どあらゆる製品にマイクロコンピュータが内
蔵されるようになってきている。メモリはマイクロコン
ピュータには不可欠なものであり、従来よりSRAMやDRAM
が使用されているが、これらのメモリは電源を切ってし
まうとメモリ内容も消えてしまうという短所を有する。[Prior Art] In recent years, microcomputers have been installed in almost all products. Memory is indispensable for microcomputers, and SRAM and DRAM have traditionally been used.
However, these memories have the disadvantage that the contents of the memory are lost when the power is turned off.
この短所を補ったものがEEPROMであり、電源を切って
メモリ内容が消えないという長所を有する。EEPROMは構
造的に大きく分けてMNOS型とFLOTOX型に分かれる。MNOS
型は、酸化膜と窒化膜界面のトラップに電子を蓄える素
子であり、FLOTOX型は、酸化膜によりどこからも電気的
に絶縁（浮遊）させた多結晶シリコン層に電子を蓄える
素子である。An EEPROM compensates for this disadvantage, and has the advantage that the contents of the memory are not erased when the power is turned off. The EEPROM is structurally roughly divided into MNOS type and FLOTOX type. MNOS
The type is an element that stores electrons in a trap at the interface between an oxide film and a nitride film, and the FLOTOX type is an element that stores electrons in a polycrystalline silicon layer that is electrically insulated (floated) from anywhere by an oxide film.
FLOTOX型は記憶保持時間が長く、MOSプロセスとも整
合が良いことから従来からよく使われている。FLOTOX型
も大きく多結晶シリコン層１層のものと２層のものに分
かれる。この内、１層構造のものは２層構造のものと比
べてプロセスが簡単で、制御ゲート側に単結晶シリコン
酸化膜を使っているので、保持特性が良い等の長所を有
する。The FLOTOX type has long been used because it has a long memory retention time and is well matched to the MOS process. The FLOTOX type is also roughly divided into one with a polycrystalline silicon layer and one with a double layer. Among them, the one-layer structure has an advantage in that the process is simpler than that of the two-layer structure, and the single crystal silicon oxide film is used on the control gate side, so that the holding property is good.
第２図は、従来から用いられている１層多結晶シリコ
ンFLOTOX型EEPROMの構造を示すものである。図中、１は
Ｎ型基板、２はＰ型拡散層で、Ｐ型拡散層（導電層）２
の中にＮ型のMOS（以下、NMOSという）が形成され、ソ
ース3a、ドレイン3b、ゲート5aを有する。このNMOSのド
レイン3bは、100Å程度の酸化膜4b、NMOSのゲート酸化
膜4aと同時に成長させた500Å程度の酸化膜4d及びNMOS
のゲート部５を通して制御ゲート3cへつながっている。
このゲート部５がEEPROMの浮遊ゲートになる。FIG. 2 shows the structure of a conventional single-layer polycrystalline silicon FLOTOX type EEPROM. In the figure, 1 is an N-type substrate, 2 is a P-type diffusion layer, and a P-type diffusion layer (conductive layer) 2
An N-type MOS (hereinafter referred to as an NMOS) is formed in each of the insides, and has a source 3a, a drain 3b, and a gate 5a. The drain 3b of the NMOS has an oxide film 4b of about 100Å, an oxide film 4d of about 500Å grown simultaneously with the gate oxide film 4a of the NMOS, and the NMOS.
It is connected to the control gate 3c through the gate part 5 of.
This gate section 5 becomes the floating gate of the EEPROM.
かかるEEPROMは、NMOSトランジスタをオン・オフする
ことにより、ドレイン3bに電圧を与え、これと制御ゲー
ト3cに印加した電圧とで薄い酸化膜4bを通して電荷のや
りとりを行い、NMOSトランジスタのしきい値を変化させ
る。In such an EEPROM, by turning on / off the NMOS transistor, a voltage is applied to the drain 3b, and this and the voltage applied to the control gate 3c exchange charges through the thin oxide film 4b, and the threshold of the NMOS transistor is changed. Change.
［発明が解決しようとする課題］ ところで、上記１層多結晶シリコンFLOTOX型EEPROM
は、上述のように、プロセスが簡単で、保持特性が良い
という長所を有するが、反面、２層多結晶シリコンタイ
プに比してセル面積が大きく、高集積化には向かないと
いう短所があった。[Problems to be Solved by the Invention] By the way, the above single-layer polycrystalline silicon FLOTOX EEPROM
As described above, the method has the advantages that the process is simple and the retention characteristics are good, but on the other hand, it has the disadvantage that it has a large cell area compared to the two-layer polycrystalline silicon type and is not suitable for high integration. It was
本発明は、上記事由に鑑みなされたもので、その目的
とするところは、従来の長所を生かし、しかもセル面積
の小型化が図れる不揮発性メモリを提供することにあ
る。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a non-volatile memory that can utilize the advantages of the related art and can reduce the cell area.
［課題を解決するための手段］ 本発明は上記課題を解決するため、単結晶基板上に、
トンネル電流注入用の薄い酸化膜（トンネル酸化膜）
と、遊離ゲートを絶縁する比較的厚い酸化膜とを有し、
前記トンネル酸化膜下に形成されたドレインと、比較的
厚い酸化膜下に形成されたソースと、前記浮遊ゲートの
一部からなるゲートとで構成されるMOSトランジスタ
と、前記ソース及びドレインと絶縁分離された制御ゲー
トとを有する１層導電ゲート層型の電気的書き込み／消
去可能な不揮発性メモリにおいて、前記制御ゲートを二
つに分け、一つは前記トンネル酸化膜と同程度の薄い酸
化膜で浮遊ゲートとカップリングさせ、これを書き込み
／消去専用の制御ゲートとすると共に、他方は前記MOS
トランジスタのゲート酸化膜と同程度の比較的厚い酸化
膜で浮遊ゲートとカップリングさせ、これを読み出し専
用の制御ゲートとしたことを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the present invention provides:
Thin oxide film for tunnel current injection (tunnel oxide film)
And a relatively thick oxide film that insulates the free gate,
A MOS transistor including a drain formed under the tunnel oxide film, a source formed under a relatively thick oxide film, and a gate formed of a part of the floating gate, and an insulating isolation between the source and the drain. In a one-layer conductive gate layer type electrically writable / erasable non-volatile memory having a control gate, the control gate is divided into two, one of which is a thin oxide film having the same thickness as the tunnel oxide film. The floating gate is coupled to it, and this is used as a control gate only for writing / erasing, and the other is the above-mentioned MOS.
The floating gate is coupled with a relatively thick oxide film that is as thick as the gate oxide film of the transistor, and this is used as a read-only control gate.
［実施例］ 以下、本発明を実施例に基づき説明する。第１図は本
発明に係る不揮発性メモリの製法の一例を示す工程図で
ある。[Examples] Hereinafter, the present invention will be described based on Examples. FIG. 1 is a process drawing showing an example of a method for manufacturing a nonvolatile memory according to the present invention.
まず、Ｎ型半導体基板（ｎ−Sub）１上にフォトリソ
グラフィ工程、イオン注入工程を経てＰ型拡散層（Ｐ−
Well）２を形成した後、素子間分離部にLOCOS4cを形成
する（第１図（ａ）参照）。First, a P-type diffusion layer (P-) is formed on the N-type semiconductor substrate (n-Sub) 1 through a photolithography process and an ion implantation process.
Well) 2 is formed, and then LOCOS 4c is formed in the element isolation portion (see FIG. 1A).
その後、将来浮遊ゲートとなるべき部分の下のＰ型拡
散層２にＰ（リン）をドープしてＮ型拡散層3b,3c,3dを
形成し、全面酸化膜除去した後、ゲート酸化膜（500
Å）4aを形成し、将来トンネル酸化膜及び薄い酸化膜と
なるべきところの酸化膜4b1′,4b2′をフォトリソグラ
フィ工程、フッ酸エッチングにより除去し、その後に薄
い（約100Å）酸化膜4b1,4b2を形成する（第１図（ｂ）
参照）。Then, P (phosphorus) is doped into the P-type diffusion layer 2 below a portion to be a floating gate in the future to form N-type diffusion layers 3b, 3c, 3d, and the entire surface oxide film is removed. 500
Å) The oxide film 4b 1 ′, 4b 2 ′ that forms the tunnel oxide film and thin oxide film in the future is removed by a photolithography process and hydrofluoric acid etching, and then a thin (about 100 Å) oxide film is formed. 4b 1 and 4b 2 are formed (Fig. 1 (b))
reference).
次に、減圧CVD（LPCVD）工程によりＰドープ多結晶シ
リコンを4500Å堆積させ、フォトリソグラフィ工程とRI
E工程により、将来、NMOSトランジスタのゲート且つメ
モリの浮遊ゲートになる部分５を残して多結晶シリコン
を除去する。その後、多結晶シリコン５をマスク材とし
てAs（ヒ素）をドープ、拡散してNMOSトランジスタのソ
ース3aとドレイン3bを形成し、本発明に明る不揮発性メ
モリを実現する（第１図（ｃ）参照）。Next, a low pressure CVD (LPCVD) process is used to deposit 4500 liters of P-doped polycrystalline silicon, and a photolithography process and RI are performed.
By the step E, the polycrystalline silicon is removed leaving the portion 5 which will be the gate of the NMOS transistor and the floating gate of the memory in the future. Then, using polycrystalline silicon 5 as a mask material, As (arsenic) is doped and diffused to form the source 3a and the drain 3b of the NMOS transistor, thereby realizing a bright nonvolatile memory according to the present invention (see FIG. 1 (c)). ).
次に、本発明に係る書き込み電圧について説明する。
書き込み電圧をＶ、NMOSトランジスタのドレイン部に設
けた薄いトンネル酸化膜4b1の両端に印加される電圧をV
0とすると、書き込み電圧Ｖは次式のようになる。Next, the write voltage according to the present invention will be described.
The write voltage is V, and the voltage applied across the thin tunnel oxide film 4b 1 provided at the drain of the NMOS transistor is V
When set to 0 , the write voltage V is given by the following equation.
Ｖ＝（１＋CFG/CCG）V0 但し、CCGは制御ゲート部の容量、CFGはNMOSドレイン
部の容量である。V = (1 + C FG / C CG ) V 0 where C CG is the capacitance of the control gate and C FG is the capacitance of the NMOS drain.
電子を注入させるためにはトンネル酸化膜4b1に印加
させる電界強度は約15MV/cm程度必要で、このためトン
ネル酸化膜4b1の厚みが決まっているとすると、前記V0
はほぼ固定された値となる。従って書き込み電圧Ｖを下
げたい場合、CFG/CCGの値を小さくしなければならな
い。この内CFGはNMOSトランジスタの形でほぼ決まって
しまい、決局CCGを大きくする必要があり、これは制御
ゲートの面積増大を招くことになる。これを避ける為
に、制御ゲートの酸化膜厚をトンネル酸化膜4b1と同程
度に薄くして制御ゲートの面積を減少させる方法は、こ
の薄い酸化膜を通して浮遊ゲートに蓄積された電荷が逃
げやすくなる為、素子の電荷保持特性を悪くする。In order to inject electrons, the electric field strength applied to the tunnel oxide film 4b 1 needs to be about 15 MV / cm. Therefore, assuming that the thickness of the tunnel oxide film 4b 1 is fixed, V 0
Is a fixed value. Therefore, when it is desired to reduce the write voltage V, the value of C FG / C CG must be reduced. Of these, C FG is almost decided in the form of an NMOS transistor, and it is necessary to increase the decision point C CG , which causes an increase in the area of the control gate. In order to avoid this, the method of reducing the control gate area by making the control gate oxide film as thin as the tunnel oxide film 4b 1 makes it easy for the charge accumulated in the floating gate to escape through this thin oxide film. Therefore, the charge retention characteristic of the device is deteriorated.
本発明では、制御ゲートを二つに分け、一つはトンネ
ル酸化膜4b1と同程度の薄い酸化膜4b2で浮遊ゲート５と
カップリングさせ、これを書き込み／消去専用の制御ゲ
ート3cとし、他方の制御ゲート3dは従来通りNMOSトラン
ジスタのゲート酸化膜4aと同程度の比較的厚い酸化膜4a
で浮遊ゲート５とカップリングさせ、これを読み出し専
用の制御ゲート3dとする構成にすることにより、セル面
積を小さくすることができる。In the present invention, the control gate is divided into two, one of which is coupled to the floating gate 5 by a thin oxide film 4b 2 which is as thin as the tunnel oxide film 4b 1, and this is used as a control gate 3c dedicated to writing / erasing, The other control gate 3d is a relatively thick oxide film 4a which is as thick as the gate oxide film 4a of the NMOS transistor as in the conventional case.
The cell area can be reduced by coupling the floating gate 5 to the read-only control gate 3d.
書き込み／消去時には薄い酸化膜4b2を通して電圧を
かけるため、従来の厚い酸化膜の構造のものに対して制
御ゲートの面積を小さくすることができる。また、読み
出し時には厚い酸化膜4aでカップリングされた制御ゲー
ト3dを使い、薄い酸化膜4b2でカップリングされた制御
ゲート3cを電気的に浮かすことにより、電荷保持特性の
劣化を防ぐことができる。Since a voltage is applied through the thin oxide film 4b 2 during writing / erasing, the area of the control gate can be made smaller than that of the conventional structure having a thick oxide film. Also, use the coupled control gate 3d with a thick oxide film 4a at the time of reading, thin the electrically float that the coupled control gate 3c oxide film 4b 2, it is possible to prevent the deterioration of the charge retention characteristics .
［発明の効果］ 本発明は上記のように、制御ゲートを二つに分け、一
つは前記トンネル酸化膜と同程度の薄い酸化膜で浮遊ゲ
ートとカップリングさせ、これを書き込み／消去専用の
制御ゲートとすると共に、他方は前記MOSトランジスタ
のゲート酸化膜と同程度の比較的厚い酸化膜で浮遊ゲー
トとカップリングさせ、これを読み出し専用の制御ゲー
トとしたことにより、セル面積を小さくすることがで
き、しかも、電荷保持特性の良い不揮発性メモリを提供
することができる。[Effects of the Invention] As described above, the present invention divides the control gate into two parts, one of which is coupled to the floating gate by a thin oxide film which is as thin as the tunnel oxide film, and which is dedicated to write / erase. The cell area is reduced by using it as a control gate and the other as a read-only control gate, which is coupled to the floating gate with a relatively thick oxide film that is about the same as the gate oxide film of the MOS transistor. In addition, it is possible to provide a non-volatile memory having good charge retention characteristics.
第１図（ａ）〜（ｃ）は本発明に係る不揮発性メモリの
製法の一例を示す工程図、第２図は従来例を示す断面図
である。 １……Ｎ型半導体基板、２……Ｐ型拡散層、3a……ソー
ス、3b……ドレイン、3c,3d……制御ゲート、4a……比
較的厚い酸化膜、4b1……トンネル酸化膜、4b2……薄い
酸化膜、4c……素子間分離酸化膜、５……浮遊ゲート、
5a……ゲート。1 (a) to 1 (c) are process drawings showing an example of a method of manufacturing a nonvolatile memory according to the present invention, and FIG. 2 is a sectional view showing a conventional example. 1 ... N-type semiconductor substrate, 2 ... P-type diffusion layer, 3a ... source, 3b ... drain, 3c, 3d ... control gate, 4a ... relatively thick oxide film, 4b 1 ... tunnel oxide film , 4b 2 ... thin oxide film, 4c ... element isolation oxide film, 5 ... floating gate,
5a ... gate.
Claims (1)
い酸化膜（トンネル酸化膜）と、浮遊ゲートを絶縁する
比較的厚い酸化膜とを有し、前記トンネル酸化膜下に形
成されたドレインと、比較的厚い酸化膜下に形成された
ソースと、前記浮遊ゲート一部からなるゲートとで構成
されるMOSトランジスタと、前記ソース及びドレインと
絶縁分離された制御ゲートとを有する１層導電ゲート層
型の電気的書き込み／消去可能な不揮発性メモリにおい
て、前記制御ゲートを二つに分け、一つは前記トンネル
酸化膜と同程度の薄い酸化膜で浮遊ゲートとカップリン
グさせ、これを書き込み／消去専用の制御ゲートとする
と共に、他方は前記MOSトランジスタのゲート酸化膜と
同程度の比較的厚い酸化膜で浮遊ゲートとカップリング
させ、これを読み出し専用の制御ゲートとしたことを特
徴とする不揮発性メモリ。1. A single crystal substrate having a thin oxide film for tunnel current injection (tunnel oxide film) and a relatively thick oxide film for insulating a floating gate, which is formed under the tunnel oxide film. One-layer conductivity having a drain, a source formed under a comparatively thick oxide film, a MOS transistor including a gate formed of a part of the floating gate, and a control gate insulated from the source and the drain In a gate layer type electrically writable / erasable non-volatile memory, the control gate is divided into two, one of which is coupled with a floating gate by a thin oxide film which is as thin as the tunnel oxide film, and this is written. / Use as a control gate exclusively for erasing, and the other side is coupled with the floating gate by a relatively thick oxide film that is about the same as the gate oxide film of the MOS transistor, and reads it. Non-volatile memory, characterized in that the control gate of use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2301389A JP2536686B2 (en) | 1990-11-06 | 1990-11-06 | Non-volatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2301389A JP2536686B2 (en) | 1990-11-06 | 1990-11-06 | Non-volatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171984A JPH04171984A (en) | 1992-06-19 |
| JP2536686B2 true JP2536686B2 (en) | 1996-09-18 |
Family
ID=17896285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2301389A Expired - Fee Related JP2536686B2 (en) | 1990-11-06 | 1990-11-06 | Non-volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536686B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10136582A1 (en) * | 2001-07-27 | 2003-02-27 | Micronas Gmbh | Method for producing a non-volatile semiconductor memory and non-volatile semiconductor memory |
| JP5690873B2 (en) * | 2013-06-07 | 2015-03-25 | イーメモリー テクノロジー インコーポレイテッド | Erasable programmable single poly non-volatile memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7500550A (en) * | 1975-01-17 | 1976-07-20 | Philips Nv | SEMICONDUCTOR MEMORY DEVICE. |
| JPH07120716B2 (en) * | 1985-03-30 | 1995-12-20 | 株式会社東芝 | Semiconductor memory device |
-
1990
- 1990-11-06 JP JP2301389A patent/JP2536686B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04171984A (en) | 1992-06-19 |
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