JPS6055694A - Method of surface treating circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to VLSI manufacturing, particularly to a method for surface treatment of a substrate when processing Bt, W, or their compounds by reactive ion etching (hereinafter referred to as RIE).

In particular, the present invention relates to a method for easily removing redeposited substances generated by RIE processing, mask layers, etc. that have been altered in quality by RIE and are difficult to remove.

[Background of the invention]

The effects of the present invention and the problems of the conventional method will be explained using FIG. FIG. 1(a) shows a base layer 1 on a wiring board 11.
2 is formed, a processed layer 13 is formed thereon, and a mask layer 14 made of photoresist or the like having an opening 15 for processing the processed layer is shown. The base layer 12 is made of At or Atzos for wiring.
The layer 13 to be processed may be an insulating layer such as Sing, etc., or W, A7, or a compound containing them. The mask layer 14 may be a photoresist whose main component is a novolac resin, or a resin in which the openings 15 are generally formed by irradiation with X-rays or electron beams. Furthermore, JP-A-51-
A layer including a plurality of materials as described in Japanese Patent No. 107775 may be used.

In this explanation, we will use AZ1350J Regis (product name of AZ Corporation) as an example.Next, as shown in FIG. When exposed to the RTE atmosphere, the mask layer 14 is altered and portions thereof are etched away. At the same time, the processed layer 13 is also etched,
A desired opening 17 is formed. 17 Karuniko IIIE
In the etching of S'02, etc., which is the layer 13 to be processed,
A large amount of re-deposition 16 occurs around the opening 17.

Next, the mask layer 14 that is no longer needed is removed. Oxygen plasma or a resist stripper (phenolic solvent) is generally used as a removal method. However, the mask layer 14 that has changed in quality due to exposure to T (IE) is extremely difficult to remove and requires a long treatment, or as shown in FIG. A layer 18 may be generated.Furthermore, even if a residue layer 18 is not generated, re-deposition 1 as shown in FIG.
6 cannot be removed. According to the experience of the inventors, it has been found that this redeposited matter 16 is difficult to remove even with a liquid that etches the workpiece 1113 and the underlying layer 12.6 As described above, in the conventional method, Residue layer and T when removing mask layer
Problems include that the wiring board 11 is contaminated due to redeposition due to Fi and that processing accuracy is significantly reduced.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention addresses the drawbacks of the conventional methods by providing a method that does not generate a residue layer and completely removes re-deposition.

[Summary of the invention]

The feature of the present invention is that a wiring board subjected to RIE treatment is immersed in a strong alkaline solution having a pH of 13 or higher, as explained in FIGS. 1(a) to 1(d). This soaking process is the first
As shown in Figure (b), the mask layer 14 may be removed during or immediately after IE, or as shown in Figures (C) and (d). After that, the residue layer 1
8 or redeposited matter 16 may be present. Suitable strong alkaline liquids include aqueous solutions such as NaOH and KO)I, and hydrazine hydrate, but are not limited to these as long as they have a pH of 13 or higher.

[Embodiments of the invention]

Example 1 This will be explained using FIG. As first shown in FIG. 2A, the wiring board 11 was made of S11, the underlying layer 12 was At, the layer 13 to be processed was StO with a thickness of about 2 pm, and the mask layer 14 was made of novolac resin heat-treated at about 200 t. Next, as shown in the same figure), CF4:H2-2: 1
The opening 17 was formed by etching the layer 13 to be processed by RTE using a gas of (volume ratio). Next, as shown in FIG. 2C, the mask layer 14 was removed by oxygen RIE (including plasma etching), but a residue layer 18 with a thickness of 0.1 μm or less and redeposited matter 16 remained. Next, cut wiring board 1
1 was immersed in 100% hydrazine hydrate at room temperature for 5 minutes or more, as shown in the same figure (e), a residue layer of 18° redeposited matter 1 was obtained.
6 were completely removed. Moreover, it was found that the base layer 12 was hardly etched. In addition, the layer 13 to be processed is W, and is processed by RIE using Si;'s gas (see FIG. 1).
Although no re-deposition 16 was observed when openings were formed as shown in Figure (C), oxygen plasma and resist stripping agent (phenol solution, trade name J-loo) were used as shown in Figure (C).
A large amount of residue layer 18 was formed which could not be removed by the following methods. However, the wiring board 11 after RIE shown in Figure 1) is immersed in 100 grams of hydrazine hydrate.

As shown in FIG. 3(e), the mask layer 14 completely disappeared.

The temperature of the strong alkaline solution and the immersion time are as follows:
If necessary, it can be determined quite easily by simple experimentation.

〔Effect of the invention〕

As described above, it has been found that by using the present invention, it is possible to completely remove the mask resin layer and redeposited substances that have been degraded by RIE, which were conventionally difficult to remove. According to the present invention, the precision of microfabrication using RIB can be greatly improved, and contamination of the substrate can also be prevented.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are cross-sectional views showing each step in an embodiment of the surface treatment method of the present invention. DESCRIPTION OF SYMBOLS 11... Wiring board, 12... Foundation layer, 13... Layer to be processed, 14... Mask layer, 15... Opening formed in mask layer, 16... Redeposited matter, 17 Shaping according to the river mask layer Figure 1 (d) (e) 459-

Claims (1)

[Claims] 1. Form a desired mask layer of photosensitive resin, X-ray resist, electron beam resist, etc. on a predetermined layer to be processed (referred to as the layer to be processed) on the wiring board, and 1. Cover by reactive ion etching. The method of etching and processing the processed layer includes the step of immersing the patterned wiring board in a strong alkaline solution with a hydrogen ion concentration of pH 13 or more during or after the start of etching the processed layer by reactive ion etching. A method for surface treatment of a wiring board, characterized in that: