JPS6055668A - Semiconductor nonvolatile memory device - Google Patents

Abstract

PURPOSE:To enable the control of the lower and upper limit values of the threshold voltage value corresponding to memory information by a method wherein the second region of a nonvolatile memory transistor channel is put in parallel with a channel region, having a high impurity concentration of the same conductivity type as that of a semiconductor substrate, and covered with a charge accumulated region. CONSTITUTION:After field oxide films 2 are selectively formed on the surface of the Si substrate 1, a gate oxide film 5 is formed, and then the surface of the substrate 1 is selectively exposed by removal of desired parts. The first high impurity concentration region of P-conductivity type is formed in the surface of the substrate 1 at the active region where no Si thin film 4 remains, and the second one 17 of P type conductivity type in the surface of the substrate at the active region. After an Si thin film is reduced in resistance, a control gate is formed by etching in such a manner that a floating gate 4 and the first and second region 17 are covered. A transistor 14 at the region covered with the floating gate is modified in the threshold voltage value to an arbitrary value according to the rewrite pulse conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor nonvolatile memory device, and particularly to a semiconductor nonvolatile memory device suitable for improving write margins.

[Background of the invention]

A basic cell of a conventional electrically rewritable semiconductor nonvolatile memory device (hereinafter abbreviated as nonvolatile memory) has a cross section, an equivalent circuit, and rewritable characteristics as shown in FIG. In FIG. 1, l is a semiconductor substrate, 2 is a field oxide film for isolation between elements, 3 is a tunnel barrier insulating film that controls charge transition between the charge storage layer 4 and the semiconductor substrate 1, and 5 and 8 are control transistors 13. They are a gate insulating film and a gate electrode, respectively. 6 and 7 are a second gate insulating film and a control gate electrode of the nonvolatile memory transistor 14 whose threshold voltage can be changed to an arbitrary value. 9 is a drain diffusion layer of the control transistor 13 connected to the data line; 10 is a diffusion layer between the source of the control transistor 13 and the drain region of the nonvolatile memory transistor 14; 11 is a source diffusion layer of the nonvolatile memory transistor 14; 12 is a protective insulating film.

As is clear from FIG. 1, the basic cell of a conventional nonvolatile memory is composed of two transistors, and it is essentially difficult to miniaturize the basic cell in terms of integration. Another disadvantage of conventional non-volatile memory is that the non-volatile memory transistor 14
The point is that the range in which the threshold voltage value can be changed is uniquely determined by the rewriting pulse conditions applied to the control gate 7.

The charge transition mechanism is the direct tunnel effect through the entire tunnel barrier insulating film 3, or the Fowler-Nordheim (1'i
'owler-NQrdl+eim) In a nonvolatile memory that uses the tunnel effect, when a full positive high voltage is applied to the control gate 7, electrons are injected from the semiconductor substrate l into the charge storage I@4, and the threshold voltage after the high voltage application is removed. is modified in the positive direction and becomes the state shown in (b) of FIG. 1(C). Conversely, when a negative high voltage is applied to the control gate 7, electrons are emitted from the charge storage layer 4, and the threshold voltage value after the high voltage is removed is changed in the negative direction and is expressed as fl) in FIG. 1(C). . ”1
The states (a) and ←) correspond to the "0" and "1" states of the stored data.The above states depend only on the height and pulse width of the rewriting high voltage pulse applied to the control game 17. However, if the above pulse conditions differ even slightly between basic cells, the 1 and 0 states of the nonvolatile memory in each basic cell will differ for each basic cell.Therefore, it is necessary to estimate sufficient child digits for the rewrite pulse conditions. Non-volatile memory has the disadvantage that if the operating conditions are not set, all rewrite malfunctions will occur.The reason why the rewrite pulse conditions mentioned above differ between each basic cell is, for example, the presence of wiring resistance of the control gate 7. This is unavoidable in non-volatile memory integrated circuits that consist of a combination of basic cells.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a nonvolatile memory in which the lower and upper limits of threshold voltage values corresponding to 1 and 0 of stored information can be controlled to desired values. Another object of the present invention is to provide a nonvolatile memory suitable for large-scale integrated circuits in which one bit can be constructed from one transistor.

[Summary of the invention]

In order to achieve the above object, the present invention provides l pi i
The channel region of one nonvolatile memory transistor consists of three regions.

That is, the first region is a region covered with a charge storage layer, and the threshold voltage value is changed depending on the switching pulse conditions. The second region is connected in series with the first region, and has a threshold voltage value set by channel ion implantation as desired. The second region is a region that determines the lower limit of the changeable threshold voltage value in the nonvolatile memory transistor. The third region is connected to the source and drain regions and is configured in parallel with the first and second regions. The threshold voltage value of the third region is controlled by channel ion implantation and is set larger than the threshold voltage value of the second region, and the region determines the upper limit of the modifiable threshold voltage value in the nonvolatile memory transistor. It is. In a nonvolatile memory transistor whose channel region is configured as described above, it is possible to inject (or release) more than a certain amount of positive or negative charge gold into the charge storage layer by applying a switching pulse that meets a certain condition or more. In other words, the lower limit and upper limit of the threshold voltage value are limited by the threshold voltage values in the second and third regions, respectively, regardless of the amount of accumulated charge.

Therefore, by applying a rewrite pulse above a certain condition, the modified threshold voltage value is set to a constant value regardless of the rewrite pulse condition, and defects such as bit-to-bit variation in read speed can be improved.

In order to configure one bit with one transistor according to the present invention, the threshold voltage in the second region described above is set to a positive value for fn channel transistors and a negative value for p channel transistors.

The above corresponds to the rewrite inhibit mode, that is, the condition in which the nonvolatile memory transistor is cut off with the control gate potential set to zero potential.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to Examples.

For convenience of explanation, the explanation will be made using drawings, but please note that important parts are shown enlarged.

2 to 6 are diagrams showing embodiments of the semiconductor non-volatile memory device according to the present invention, with a specific resistance of 1 digit p conductivity type 10Ω-
It is a silicon substrate of σ. After selectively forming a 0.8 μm thick filled oxide film 2 on the silicon substrate 1i using a known device isolation technique, the semiconductor surface of the active region is exposed and a 30 nm clean gate oxide R5 is formed. . Thereafter, a desired portion of the gate oxide film 5 is selectively removed by photolithography, and the entire surface of the silicon substrate 1 is selectively exposed through the opening 15. Next, after removing and cleaning the remaining photoresist film, using oxygen gas (02) diluted with silicon gas (N, ), the Og/N a ratio was 3X.
], 0-' thermal oxidation for 1050C140 minutes was performed to form a 5Ωm
A silicon oxide film was formed. Next, a silicon thin film 4 with a thickness of 0.2 μm is deposited on the entire surface by chemical vapor phase reaction, and then phosphorus ions of 5×10"crn-' are implanted on the entire surface by total ion implantation, and then an activation heat treatment is performed. The silicon thin film 4 was then etched to a sufficiently low resistance by photolithography.Then, the silicon thin film 4 was etched into a band shape so as to locally cover each of the pair of oxide film openings 15.

Subsequently, 2×10"Crn-" boron ions are implanted with a total acceleration energy of 25 KeV, and the surface of the silicon substrate 1 in the active region where the band-shaped silicon thin film 4 is not left is doped with the first high impurity impurity of p conductivity type. A concentration region was formed. Next, the photoresist film used in the photolithography was removed, and the silicon thin film 4 was etched again in a direction perpendicular to the first photolithography by a second photolithography. The arsenic ions left on the photoresist film 16' used in the second photolithography were heated at 80K.
Ion implantation was performed with an acceleration energy of eV to form a source diffusion layer 11 and a drain diffusion layer 1 (l).The above ion implantation conditions are such that the impurity concentration is approximately the maximum on the surface of the silicon substrate 1 directly under the gate oxide film.Continued. Then, using the photoresist film 16 used in the second photolithography as a mask, the silicon thin film 4 was side-etched at a rate of 0.3 μm on each side to form a floating gate 4. Next, the remaining photoresist film 16 was etched. 7X
10 "cm-" boron ion = i30KeV
The ions were implanted with an acceleration energy of . By the above ion implantation, the floating gate 4 was formed in the second high impurity concentration region 17 of the ip conductivity type on the lfi surface of the silicon substrate in the active region where the floating gate 4 is not left. Thereafter, a two-layer insulating film 6 consisting of a silicon oxide film of 915 nm formed by dry thermal oxidation of 90 nm and a silicon nitride film of 3 Q nm formed by chemical vapor reaction is formed on the surface of the silicon substrate 1 and on the floating gate 4. Next, the silicon thin film 7 was deposited again on the entire surface of the 7 silicon films by chemical vapor phase reaction.The resistance of the silicon thin film 7 was made sufficiently low by ion implantation of phosphorus, and then the floating gate 4 and the first high impurity concentration region were formed by photolithography. Then, a control gate was formed by etching to cover the second high impurity concentration region 17Th.Next, using known techniques, a protective insulating film was formed, a contact hole was formed, and wiring connections were made according to a desired circuit configuration. All non-volatile memory was manufactured.

The threshold voltage value of the nonvolatile memory manufactured through the above manufacturing process was +0.7v. Then control game (9) 100ns to 1 with +20V pulse height on the door.
When pulses with various widths of 0 μs were applied and the threshold voltage values after the pulse application were measured, they were all 6. It was Ov. In this state, -20
Pulses having a pulse height of V and various widths from 1 ounces to 10 μs were applied, and the threshold voltage value after the pulse application was measured and found to be 0.7 V regardless of the pulse conditions.

From the above results, it can be seen that the nonvolatile memory transistor according to this example is represented by an equivalent circuit as shown in FIG. 5, and has rewrite characteristics as shown in FIG. 6.

That is, the region covered by the floating gate in the channel region is represented by the transistor 14, and the threshold voltage value is changed to an arbitrary value according to the rewriting pulse conditions. A transistor 18 connected in series with the transistor 14 corresponds to the second high impurity concentration region 17, and its threshold voltage value is determined by the amount of channel ion implantation and has a value of +6V.

Transistor 1 connected in parallel with each of the above transistors
9 is formed in self-alignment with the floating gate 4 (
10) represents the first high impurity concentration region of p-conductivity type and has a threshold voltage value of 6. It is Ov. As is clear from the equivalent circuit shown in FIG. 5, even if the threshold voltage value of the transistor 14 is changed as shown in FIG.
Threshold voltage value v? The upper limit value is limited by the transistor 19 as shown in (c). Therefore, under conditions that satisfy a certain rewriting pulse height or width, the nonvolatile memory according to this embodiment can obtain rewriting characteristics that do not depend on the one rewriting pulse condition. Furthermore, in this embodiment, if the threshold voltage value of the part 17 of the channel region corresponding to the transistor 18 is set to a positive value, as long as the control gate 7 is kept at zero potential, the voltage will be applied to the drain 10. Since the non-volatile memory transistor iJ' can be kept in the cut-off state regardless of the pulse conditions, one non-volatile memory transistor based on this embodiment can be used for one bit.

[Effects of the Invention] According to the present invention, each threshold voltage value corresponding to the l(11) and 0 memory states of a semiconductor nonvolatile memory device can be maintained at the set value regardless of the full rewrite pulse conditions, so that the rewrite pulse This has the effect that the number of digits has been significantly improved and the range of variation in read speed has been kept extremely small.

Further, according to the present invention, a semiconductor nonvolatile memory device in which one bit is composed of one transistor can be realized, which is extremely suitable for high integration.

In the embodiments of the present invention, an example in which a floating gate is used as a charge storage layer has been described, but the charge storage layer may be formed at an interface between different types of insulating films, such as a combination of a silicon oxide film and a silicon nitride film, or within an insulating film. A structure using a trap, a so-called MNO8 structure or MAO8 structure, may also be used.

Further, in the above embodiments, a semiconductor non-volatile memory device based on an n-channel transistor has been described, but the present invention can also be applied to a semiconductor non-volatile memory device based on a p-channel transistor, or even a complementary type (referred to as 0MO8).

[Brief explanation of the drawing]

(12) NF2 diagrams are diagrams showing the cross section, unit cell configuration, and refill characteristics of conventional semiconductor nonvolatile memory devices, and Figures 2 to 4
The figures are a sectional view and a plan view showing an embodiment of the present invention, FIG. 5 is an equivalent circuit diagram of a cell of a semiconductor non-volatile memory device according to the present invention, and FIG. 6 is a unit cell of a semiconductor non-volatile memory device according to the present invention. ni (13) Figure 1 Threshold - No E I Straight □ Heat 3 Figure (B) 3 ''! /I r mouth Figure 3 (A) /IJ t+ Pidge

Claims (1)

[Claims] 1. a source and drain region having a conductivity type opposite to that of the semiconductor substrate provided on one surface of the semiconductor substrate; a first insulating film provided on a channel region inserted in the source and drain regions; A semiconductor non-volatile memory device having a charge storage region provided on a part of the insulating film of No. 1 and electrically isolated from the outside, and a control gate provided so as to cover at least an acoustic flux of the charge storage region. The first part of the channel region is not controlled by the charge storage region. and a second region, the second region has a high impurity concentration of the same conductivity type as the semiconductor substrate, and is configured in parallel with the channel region covered with the charge storage region. Semiconductor non-volatile memory device.