JPS605528A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS605528A
JPS605528A JP11320183A JP11320183A JPS605528A JP S605528 A JPS605528 A JP S605528A JP 11320183 A JP11320183 A JP 11320183A JP 11320183 A JP11320183 A JP 11320183A JP S605528 A JPS605528 A JP S605528A
Authority
JP
Japan
Prior art keywords
wafer
furnace
washed
dry etching
water
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11320183A
Other languages
Japanese (ja)
Inventor
Yoshiaki Tanimoto
谷本 芳昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11320183A priority Critical patent/JPS605528A/en
Publication of JPS605528A publication Critical patent/JPS605528A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To prevent the corrosion of an Al wiring after an wafer was drawn out in the air by a method wherein the wafer formed with the aluminum wiring body according to a dry etching, wherein reaction gas of the chlorine system is used, is heated to specific temperatures, and after that, the wafer is washed with water. CONSTITUTION:A wafer formed with an aluminum wiring body according to a dry etching, wherein reaction gas of the chlorine system is used, is heated to temperatures of not less than 100 deg.C and not more than 200 deg.C, and after that, the wafer is washed with water. For example, a wafer 11 which ended the dry etching is held for one 1min-5min in a furnace, whose interior has been filled up with N2 gas and has been kept at 180 deg.C, as the wafer 11 has been put in the furnace, and following that, the wafer 11 is washed with pure water for about one minute using an ordianry spinner 12. The time to heat the wafer 11 in the furnace is continued for a period of time of exceeding a little 1min, because the heating time is somewhat short in one minute. Following that, a resist removed by an ordinary ashing technique in the following process and processes such as the formation of an insulating film, etc., are performed. As a result, the amount of chlorine remaining in the wafer is significantly reduced, thereby enabling to upgrade the yield of products and the reliability thereof.

Description

【発明の詳細な説明】 (1ン発明の技術分野 本発明は半導体装置の製造方法、詳しくは”rルミニウ
ム(Atり配線体のドライエツチングの後におりる^p
配線体の腐蝕を防止する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device.
The present invention relates to a method for preventing corrosion of wiring bodies.

(2)技術の背景 半導体装置の集積度を高める傾向に対応して、ドライエ
ツチングによって2μm程度の幅のへl配線体を形成す
ることが行われる。その例を第1図の断面図を参照して
説明すると、例えばウェハ上に成長された燐・シリケー
I−・ガラス(IIsG )の絶縁11央1の上にΔβ
膜を例えば蒸着によっ゛C1戊長し、この^l股をパタ
ーニングしてへβ配線体2を形成する。そのためには、
へβ膜上にレジスト膜を例えばスピンコード法(回転塗
布法)で形成し、このレジストM)4に露光現像等の処
理(パターニング)を行ってレジスト膜3を形成し、こ
のレジスト膜3をマスクにして塩素系の反応ガス(例え
ば四塩化炭素(tJ!す)、三塩化ホウ素(Bcz3)
等のガス)を用いるプラズマエツチングでAt股をエツ
チングして前記した幅のB配線体2を形成する。
(2) Background of the Technology In response to the trend toward increasing the degree of integration of semiconductor devices, dry etching is used to form thin interconnects with a width of about 2 μm. An example of this will be explained with reference to the cross-sectional view of FIG. 1. For example, if Δβ
The film is lengthened by evaporation, for example, and the length is patterned to form the β wiring body 2. for that purpose,
A resist film is formed on the β film by, for example, a spin code method (rotary coating method), and this resist M) 4 is subjected to processing (patterning) such as exposure and development to form a resist film 3. Use a mask with chlorine-based reactive gases (e.g. carbon tetrachloride (tJ!), boron trichloride (Bcz3))
The B wiring body 2 having the width described above is formed by etching the At crotch by plasma etching using gases such as etching gases.

(3)従来技術と問題点 上記シたA7?のトライエツチングの後にウェハを大気
中に取り出すと、エツチングされたへl声線体3の側部
やレジスト中に残留した塩素によっ’(FIJ蝕バツバ
フル生し、それによっζいわゆるiの虫食い現象が発生
ずる。これば、水酸化塩化アルミニウムが空気中の湿気
にさらされ加水分解し塩酸となって八!を第1図に斜線
をイ」シて示すように腐蝕する。この虫食いによってA
β配線体は2μmの幅に設計したものが約半分程度の輸
(1μm)となり高抵抗のものになる。
(3) Prior art and problems A7? When the wafer is taken out into the atmosphere after the try-etching, chlorine remaining on the side of the etched film body 3 and in the resist causes "FIJ erosion", which causes the so-called worm-eaten phenomenon. When aluminum hydroxide chloride is exposed to moisture in the air, it hydrolyzes and becomes hydrochloric acid, corroding as shown by the diagonal lines in Figure 1. Due to this worm attack, A
The β wiring body designed to have a width of 2 μm becomes about half the width (1 μm), resulting in a high resistance one.

上記したANの虫食いの防止策としてエツチング後に真
空中で四弗化炭素(Ch )プラズマ、酸素(02)プ
ラズマ等の後処理を行い、レジストをはとんと取り去っ
て後にウェハを大気中に出すことかなされる。
As a measure to prevent the above-mentioned AN from being eaten by insects, it may be necessary to perform post-treatment such as carbon tetrafluoride (Ch 2 ) plasma or oxygen (02) plasma in a vacuum after etching, to thoroughly remove the resist, and then expose the wafer to the atmosphere. be done.

しかし、CFl、lを用いる後処理においてはレジスト
だけでなく下地のll5G IJがエツチングされる問
題があり、他力 02を用いる後処理においてはへl配
線体上にAn203映が形成され後工程でのレジストの
アッシングにおいてレジストが完全に除去されないこと
がある。またはアルゴン(^r)でたたく後処理におい
ては、レジストを硬くしそれの除去を難しくする。また
以上いずれの方法においても時間がかかりすぎる問題が
ある。
However, in the post-processing using CFl,l, there is a problem that not only the resist but also the underlying ll5G IJ is etched, and in the post-processing using CFl, 02, an An203 film is formed on the ferrite wiring body, and in the post-process. During resist ashing, the resist may not be completely removed. Alternatively, post-treatment by hitting with argon (^r) hardens the resist and makes it difficult to remove. In addition, both of the above methods have the problem of taking too much time.

(4)発明の目的 本発明は上記従来の問題に漏の、ウェハ」二に成長した
Aβ膜のトライエツチングによるi配線体の形成におい
C、ウェハを大気中に取り出した後の八βの局蝕を防止
する半導体装置の製造方法を提供することを目的とする
(4) Purpose of the Invention The present invention solves the above-mentioned conventional problem, and aims at forming an i-wiring body by tri-etching an Aβ film grown on a wafer. An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents corrosion.

(5)発明の構成 そしてこの目的は本発明によれは、塩素系の反応ガスを
用いるトライエツチングによりアルミニウムの配線体か
形成されたウェハを、100℃以上200℃未満の温度
に加熱し、しかる後にウェハを水で洗浄することを特徴
とする半導体装iイの製造方法を提供することによって
達成され、または前記トライエツチングの終ったウェハ
に、100°C以上200°C未満の水蒸気を吹き付け
て当該ウェハをbし浄するごとによっ−ζも達成される
(5) Structure and object of the invention According to the present invention, a wafer on which an aluminum wiring body is formed by tri-etching using a chlorine-based reactive gas is heated to a temperature of 100°C or more and less than 200°C, and then This is achieved by providing a method for manufacturing a semiconductor device, which is characterized in that the wafer is subsequently washed with water, or by spraying water vapor at a temperature of 100°C or more and less than 200°C on the wafer after the above-mentioned trial etching. -ζ is also achieved each time the wafer is cleaned.

(6)発明の実施例 以T本発明実施例を図面により詳説する。(6) Examples of the invention Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

本願発明者は、前記した塩素系の反応ガスを用いるトラ
イエツチングが終った直後における残留塩素量を螢光X
線分析によって測定し、その量を100と設定した。
The inventor of the present application has determined the amount of residual chlorine immediately after the tri-etching using the above-mentioned chlorine-based reaction gas by using fluorescent X.
It was determined by line analysis and the amount was set as 100.

同しドライエツチングの終ったウェハを窒素(N2 )
ガスを充填した100℃の炉内に5分間置い゛(残留塩
素量を測定したところ、その量は前記例“(100であ
ったものに比べ半分の50に減少した。
The wafer after dry etching is exposed to nitrogen (N2).
When the amount of residual chlorine was measured by placing it in a gas-filled furnace at 100° C. for 5 minutes, the amount was reduced to 50, half of that in the previous example (100).

続い−Cウェハをスピンナー上に載置し、純水で1力間
ウェハを洗浄したとごろ、残留塩素量は前記の設’JJ
I (ll’iに幻し20に減少したことと、前記炉内
の温度が100°C;411:i’!iでは前記の効果
が発生しないこととが6(II認された。
Continuing - After placing the C wafer on the spinner and cleaning the wafer with pure water for one time, the amount of residual chlorine was determined by the above setting.
It was recognized in 6(II) that the temperature in the furnace was 100° C.;

そこで、本発明の方法においては上記の実験か得られた
原理を応用し、塩素系の反応ガスを用いるトライエツチ
ングの直後に、ウェハをレジストに変化を与えない程度
の温度に熱し、統い゛Cウェハを水で洗浄するものであ
る。ウェハのエツチングにマスクとして使用したレジス
トは通常200℃程度で軟化するくだれる)から、ウェ
ハは200°C未14i、好ましくは180°C程度に
熱すればよいごとが実証された。
Therefore, in the method of the present invention, the principle obtained from the above experiment is applied, and immediately after tri-etching using a chlorine-based reactive gas, the wafer is heated to a temperature that does not cause any change in the resist. C. The wafer is washed with water. Since the resist used as a mask for etching the wafer usually softens and collapses at about 200°C, it has been demonstrated that the wafer can be heated to less than 200°C, preferably to about 180°C.

本発明の第1実施例においては、I・ライエツチングが
終ったウェハを、 N2カスを充填し、180℃に保た
れた炉内に、1分〜5分間入れ′Cおき、続いて辿當の
スピンナーを用い1分権度ウェハを純水で洗浄する。
In the first embodiment of the present invention, a wafer that has been subjected to I-writing is placed in a furnace maintained at 180°C for 1 to 5 minutes, filled with N2 gas, and then subjected to tracing. The 1-degree spinner is used to clean the 1-degree wafer with pure water.

炉内でのウェハの加熱は、1分ではやや短いので1分を
若干超える時間継続する。水洗に1分を要するとして残
留塩素の除去には2分をやや超える時間で足り、このこ
とは従来技術において必要とされた時間に比べると大幅
な短縮である。しかも、ウェハの残留塩素量を測定した
とごろ、前記の100の設定値に比べ15であること、
ずなわら1/6以上も残留塩素量が少ないことが確認さ
れた。
The heating of the wafer in the furnace continues for slightly more than one minute, since one minute is rather short. If rinsing takes 1 minute, removing residual chlorine takes just over 2 minutes, which is a significant reduction in time compared to the time required in the prior art. Moreover, when the amount of residual chlorine on the wafer was measured, it was 15 compared to the above-mentioned set value of 100.
It was confirmed that the amount of residual chlorine was 1/6 or more lower than Zunawara.

本願発明者は第1実施例から、ウェハを前記範囲の温度
に熱した後に純水で洗って残留塩素量を減少しうる効果
があるのであれば、処理の終ったウェハにO1j記什囲
の水蒸気を噴射すれば(100℃以上200℃未満の温
水は64られないから)同様の効果か発生ずるのではな
いかと嵩え、かかる考えに従って実験を行ったところ、
第1実施例の場合と同様に好結果を得た。かくして、本
発明の第2実施例においては、180℃の炉内にウェハ
を置く代りに、iji+記したドライエツチングの終了
したウェハ11を第2図に示すスピンナー12上に直ち
に載1がする。スピンナー12は図示しない100°C
〜200°Cの加熱容量をもつヒータを内蔵するもので
あっC、ウェハを保温する。スピンナーを例えば110
00rpで回転し、ノスル13から100℃以上200
℃未l&iの範囲内の温度に加熱された水蒸気をウェハ
11に向けζ吹き付ける。この高温水非気を1分吹きイ
1けた後にウェハの残留塩素量を測定したところ、1)
11記した100の設定値に対し−(15の値が観測さ
れ、第1実施例同様残留塩素量か大幅に減少しているこ
とか裏イ」けられた。
Based on the first embodiment, the inventor of the present application has determined that if the wafer is heated to a temperature within the above range and then washed with pure water to reduce the amount of residual chlorine, then the wafer after the treatment should be washed with the O1j description. I suspected that a similar effect could be produced by injecting water vapor (because hot water above 100°C and below 200°C cannot be heated), so I conducted an experiment based on this idea.
Good results were obtained as in the case of the first example. Thus, in the second embodiment of the present invention, instead of placing the wafer in a 180 DEG C. furnace, the dry-etched wafer 11 marked iji+ is immediately placed on the spinner 12 shown in FIG. Spinner 12 is heated to 100°C (not shown)
It has a built-in heater with a heating capacity of ~200°C to keep the wafer warm. Spinner for example 110
Rotates at 00 rpm, from nozzle 13 to 100℃ or more 200
Water vapor heated to a temperature within a range of 1&i is blown toward the wafer 11. After blowing this high-temperature water without air for 1 minute, we measured the amount of residual chlorine on the wafer and found that 1)
A value of -(15) was observed with respect to the set value of 100 as shown in 11, indicating that the amount of residual chlorine had significantly decreased as in the first example.

引続き次工程で通當のアノシンク技術でレンストを除去
し、絶縁膜形成等の上程を行う。 へe配線体の形成に
おいて第1と第2実施例のいずれを実施するかはウェハ
にそれまでに施行されたウェハプロセス、半導体装置の
種類等に応して定め、またヒータの加j1%温度、水蒸
気の温度等も111記したドライエツチングの種類等に
j心して適宜選足する。
Subsequently, in the next process, the resist is removed using the conventional anosink technique, and the upper steps such as forming an insulating film are performed. Whether to carry out the first or second embodiment in forming the wiring body is determined depending on the wafer process that has been applied to the wafer up to that time, the type of semiconductor device, etc. , the temperature of the water vapor, etc. are selected as appropriate, keeping in mind the type of dry etching described in 111.

(7)発明の効果 以上詳細に説明した如く、本発明の力演によれば、従来
技術に比べ、より短い時間で、ウエノ1の残留塩素量を
大幅に減少することが可能となり、微細化が要求される
半導体装置製造の歩留りと製品の信頼性向上にすJ果大
である。
(7) Effects of the invention As explained in detail above, according to the performance of the present invention, it is possible to significantly reduce the amount of residual chlorine in Ueno 1 in a shorter time than with the conventional technology, and This is extremely important for improving the yield and product reliability of semiconductor device manufacturing, which is required.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はへβ配線体の虫食いを示す断面図、第2図は本
発明の力演を実施するスピンナーを示す斜視図である。 1−−絶縁j挨、2− へβ配線体、3−レジスト映、
11− ウェハ、12− スピンナー、■3− ノスル 第11 第2図 二二二二:A 酋 、+2
FIG. 1 is a sectional view showing worm-eaten parts of the beta wiring body, and FIG. 2 is a perspective view showing a spinner for carrying out the powerful operation of the present invention. 1--insulation, 2-β wiring body, 3-resist film,
11- Wafer, 12- Spinner, ■3- Nostle No. 11 Fig. 2 2222: A, +2

Claims (1)

【特許請求の範囲】 (11塩素系の艮応ガスを用いるトライエツチングによ
りアルミニウムの配線体が形成されたウェハを、100
℃以上200℃未満の温度に加熱し、しかる後にウェハ
を水で洗浄することを特徴とする半導体装置の製造方法
。 (2)前記トライエツチングの終ったウェハに、100
“C以上200°C未満の水蒸気を吹き付けて当該ウェ
ハを洗浄することを特徴とする特許請求の範囲第1項記
載の半導体装置の製造方法。
[Scope of claims]
A method for manufacturing a semiconductor device, which comprises heating the wafer to a temperature of .degree. C. or more and less than 200.degree. C., and then cleaning the wafer with water. (2) On the wafer after the trial etching, 100
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer is cleaned by spraying water vapor at a temperature higher than or equal to 200°C.
JP11320183A 1983-06-23 1983-06-23 Manufacture of semiconductor device Pending JPS605528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11320183A JPS605528A (en) 1983-06-23 1983-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11320183A JPS605528A (en) 1983-06-23 1983-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS605528A true JPS605528A (en) 1985-01-12

Family

ID=14606112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11320183A Pending JPS605528A (en) 1983-06-23 1983-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS605528A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224233A (en) * 1989-02-27 1990-09-06 Hitachi Ltd Sample treatment method end device
JPH08335571A (en) * 1996-01-29 1996-12-17 Hitachi Ltd Plasma treatment apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224233A (en) * 1989-02-27 1990-09-06 Hitachi Ltd Sample treatment method end device
JPH08335571A (en) * 1996-01-29 1996-12-17 Hitachi Ltd Plasma treatment apparatus

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