JPS6054465A - Three-dimensional integrated circuit device - Google Patents
Three-dimensional integrated circuit deviceInfo
- Publication number
- JPS6054465A JPS6054465A JP16392083A JP16392083A JPS6054465A JP S6054465 A JPS6054465 A JP S6054465A JP 16392083 A JP16392083 A JP 16392083A JP 16392083 A JP16392083 A JP 16392083A JP S6054465 A JPS6054465 A JP S6054465A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- dimensional
- equation
- yield
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Abstract
Description
【発明の詳細な説明】
＋ａｌ 発明の技術分野
本発明は三次元集積回路装置（三次元ＬＳ Ｉ）に係か
り、特に設計時、所望の歩留Ｙｃ以上で製造するための
能動素子形成層の積層数Ｍ。を有する三次元ＬＳＩに関
する。DETAILED DESCRIPTION OF THE INVENTION +al Technical Field of the Invention The present invention relates to a three-dimensional integrated circuit device (three-dimensional LSI), and in particular, it is related to a three-dimensional integrated circuit device (three-dimensional LSI). Number of layers M. The present invention relates to a three-dimensional LSI having a three-dimensional LSI.
（ｂｌ 技術の背景
周知のように、半導体集積回路（ＩＣ）は■、Ｓｌ、Ｖ
ＬＳＩと二次元（平面）領域で微細化、高築積化されて
きたが、それは高度に集積化すれば高速動作等、極めて
利点が多いからである。しかしながら、微細化にも限度
があり、例えばＭＯＳＦＥＴのゲート長が１μｍあるい
はそれ以下ではホットエレクトロン効果が顕著に現れる
というような微細化に伴う物理的限界が見えてきた。(bl Technology Background As is well known, semiconductor integrated circuits (IC) are
LSIs and two-dimensional (planar) areas have been miniaturized and built up in large scale because highly integrated devices have many advantages, such as high-speed operation. However, there is a limit to miniaturization, and physical limits associated with miniaturization have become apparent, for example, when the gate length of a MOSFET is 1 μm or less, the hot electron effect becomes noticeable.
一方、絶縁基板上に半導体層を被着し、ビーム・アニー
ルして結晶基板として、その半導体結晶基板に素子を形
成し、更にその上に配線層を設けて、これを多層に積み
上げる構造が開発されており、これにより三次元ＬＳＩ
が太き（クローズアンプしてきた。On the other hand, a structure has been developed in which a semiconductor layer is deposited on an insulating substrate, beam annealed to form a crystal substrate, an element is formed on the semiconductor crystal substrate, a wiring layer is further provided on top of the semiconductor layer, and these are stacked in multiple layers. This allows three-dimensional LSI
It's thick (close amp).
上記のような微細化の限界を考え合わせると、立体的な
三次元ＬＳＩは今後にＩＣが発展するための最大課題で
あると思われる。Considering the limitations of miniaturization as described above, three-dimensional three-dimensional LSIs are considered to be the biggest challenge for the future development of ICs.
（Ｉ〕）従来１に術と問題点
ごの１１、・うな三次元Ｔ、ＳＴにおいて、どのような
１−１漬の三次元１．３Ｉを形成するかは設計上極めて
重要な問題である。今後、例えば論理回路ＬＳＩにおい
て５０万ゲートの二次元ＬＳＩを２層に積層するか、ま
たＩｎ万ゲ−１−の二次元Ｌ Ｓ Ｉを１０１Ｍに積層
するかの選ＩＲを迫られることが当然予想される。(I) Conventional techniques and problems in 1. 11. What kind of 1-1 dipping three-dimensional 1.3I should be formed in the three-dimensional T and ST is an extremely important design issue. . In the future, for example, in logic circuit LSIs, it is natural that IRs will have to choose between stacking 500,000 gates of two-dimensional LSIs in two layers, or stacking 101 million gates of two-dimensional LSIs of 101M. is expected.
通常、二次元ＬＳＩのプロセスおよび設計は性能、−１
ス１．納明の３つを考慮して決定されるが、：ＩストＬ
：１Ｉｉ４！ ＜ ７１Ｆ留（ｖｉｃｌｄ ）に左右さ
れる。三次元１．ｓｌにとってｂ １ａも重要なことは
採算に合うかどうかのご１スト問題である。Usually, the process and design of two-dimensional LSI has a performance of -1
S1. It is determined by taking into account three factors: I St. L
:1Ii4! <71F (vicld). Three dimensions 1. For SL, the important thing about B1A is the question of whether it is profitable or not.
（（１）発明の目的
本発明は１１″ｌ−１！スおよび設計の定数が与えられ
ている場合に、′ｆ−＞ｉ４価格１以下のコストで製作
するだめの１１シ動素子形成層の積層数を有する三次元
ＬＳ１を１！Ｉ！案するものである。((1) Purpose of the Invention The present invention provides an 11-shift element forming layer that can be manufactured at a cost of 1 or less when 11''l-1! space and design constants are given. A three-dimensional LS1 having the number of laminated layers of 1!I! is proposed.
（＋り発明の構成
その目的は、三次元ＬＳＩにおける能動素子形但し、Ｍ
ｏはＭ。≧１を満足する整数
ｎ；単層の工程数
ａ；回路密度に関する比例定数
Ｄ；平均欠陥密度
に；チップ当たりの能動素子数
ｙｏ ；平均工程歩留
Ｙｃ Ｈ所望の歩留
ｌｏｇ ；自然対数
からなる式で与えられる積層数ＭＯを有する三次元集積
回路装置によって達成される。(Constitution of the invention The purpose is to form an active element in a three-dimensional LSI.
o is M. Integer n that satisfies ≧1; number of single-layer processes a; proportionality constant D related to circuit density; average defect density; number of active elements per chip yo; average process yield Yc H desired yield log; from natural logarithm This is achieved by a three-dimensional integrated circuit device having the number of stacked layers MO given by the following equation.
（ｆｌ 発明の実施例
以下、詳細に説明すると、本発明にかかる積層数決定方
法は二次元ＬＳＩの歩留計算法を基礎にしているため、
まず二次元ＬＳＩの歩留計算法の概要を説明する。(fl Embodiments of the Invention To explain in detail below, the method for determining the number of laminated layers according to the present invention is based on the yield calculation method of two-dimensional LSI,
First, an overview of the yield calculation method for two-dimensional LSI will be explained.
欠陥密度はポアソン分布に依存すると仮定する。It is assumed that the defect density depends on the Poisson distribution.
そうすると、工程数ｎによって完成される半導体ウェハ
ーのウコーハ 歩留Ｙは次式で表わされる。Then, the yield Y of semiconductor wafers completed by the number of steps n is expressed by the following equation.
、二こに、ｙ、、 １１１１．、Ｉ’１μ、１−それぞ
れ１番目工程の工程ル留、欠陥に関連ある面積、欠陥密
度で、本式におしする一／ｉ’Ｙｌのｎ ｙ ｙ、（る
因子は各工程歩留の積、指数関数因子は欠陥密度と面積
に依存する歩留を表すものである。, Nikoni, y,, 1111. , I'1μ, 1 - the process yield of the first process, the area related to defects, and the defect density, which are expressed in this formula as 1/i'Yl, (the factor is the yield of each process. The product of , an exponential factor, represents the yield depending on defect density and area.
欠陥密度り、・とこ１結晶欠陥のみならずゴミの付着な
ど、電気的特性に及ぼず色々の欠陥を意味しており、欠
陥に関連ンを）る面積Ａｊとはそれの起こり易い６ｆ１
賎の面積、ｒｌ’！ Ｉ’ｌ’Ｊにはチソプ−ヒの能動
素子領域の占める面積を意味している。Defect density refers to not only crystal defects but also various defects that do not affect electrical characteristics, such as adhesion of dust, and the area Aj related to defects is the area 6f1 where it is likely to occur.
Area of sieve, rl'! I'l'J means the area occupied by the active element region of the chip.
（＋ ｌ ＪＣＩＩ油ｉｌｌであるから、これを簡単し
て、Ｙ −Ｙ ＋＋ ０１１１１ （−ｎ、Ａ、Ｄ）
−−−−−−（２）と１１シ定する。こごに、ｙｏは全
工程数ｎの平均工程歩留、Ａはチップ面積、Ｄはチップ
面積の欠陥密度とする。(+l Since it is JCII oil ill, this can be simplified as Y -Y ++ 01111 (-n, A, D)
-------- (2) and 11 are determined. Here, yo is the average process yield of the total number of processes n, A is the chip area, and D is the defect density of the chip area.
また、チップ面積へとチップ当たり素子数Ｋ（Ｉ−クン
ジスタ、ゲー １などの能動素子を素子と略称する）と
の関係番、１、
Ａ（Ｋ）＝ａ−に２ −−−−−−−−−−−−−−−
−−−−−＋３１と仮定する。Ａ（Ｋ ）は素子数Ｋを
有するチップ面積を表わし、ａは回路密度に関する比例
定数である。このように素子数の２乗にチップ面積が比
例するわけは、素子が増えると配線数が増加するからで
あり、理論的証明もなされており、且つ（３）式はＣＭ
ＯＳゲートアレイの実際の製品の値と良い一致を示す。In addition, the relationship between the chip area and the number of elements per chip, K (active elements such as I-Kunjista and Ge1 are abbreviated as elements), is 1, A(K) = a- and 2. −−−−−−−−−
−−−−−+31. A(K) represents the chip area with the number of elements K, and a is a proportionality constant regarding circuit density. The reason why the chip area is proportional to the square of the number of elements is that the number of wires increases as the number of elements increases, and this has been theoretically proven, and equation (3) is
It shows good agreement with the actual product value of OS gate array.
（３）式を（２）式に入れると、次式が得られる。When formula (3) is inserted into formula (2), the following formula is obtained.
ＹＫ） ＝ ）Ｆｏ ｅｘｐ （−ｎ・ａ−１）Ｋ２）
−−・−＋４１この（４）式は歩留Ｙ（Ｋ ）が素子
数Ｋに依存することを示しているものである。YK) = )Fo exp (-n・a-1)K2)
--.-+41 This equation (4) shows that the yield Y(K) depends on the number K of elements.
以上に説明した二次元ＬＳＩの式を基礎にして、三次元
ＬＳＩにおける同様の式を計算する。この場合、素子を
形成した層の積層数をＭとすれば、上記工程数ｎｔ−Ｍ
倍繰り返して形成すると考えてよいから、二次元式のｎ
は三次元式ではＭ Ｘ ｎと置き換えられる。Based on the formula for the two-dimensional LSI explained above, a similar formula for the three-dimensional LSI is calculated. In this case, if the number of laminated layers forming the element is M, then the number of steps nt-M
Since it can be considered that it is formed by repeating twice, the two-dimensional formula n
is replaced with M X n in the three-dimensional formula.
また、三次元における見掛は上のチップ面積はＡ（Ｋ）
＝ａ・（Ｋ／Ｍ） ２−−−−−−−（５）となり、−
次元におりる（３）式は三次元では（５）式に代わる。Also, the apparent area of the upper chip in three dimensions is A(K)
=a・(K/M) 2−−−−−−(5), −
Equation (3) in three dimensions is replaced by equation (5) in three dimensions.
これら２つの条件を（２）式に入れると、（４）式に代
わって次式かえられる。When these two conditions are put into equation (2), equation (4) is replaced by the following equation.
Ｙ（Ｋ、Ｍ） −Ｙ ｏ ｅｘｐ （−ｎａＤＫ２／Ｍ
）−（６）この式の有頂のｙ。は工程に関連する歩留で
あり、後項は欠陥に関連する歩留、例えば作業間違いや
’ｊｅｌ Ｗｉ装置の／＆障などが関係する歩留である
。（６）式１１、Ｍ＝１とずれば、（４１Ｊｙがえられ
るから二次元ＬＳＩを含む弐＾なる。Y (K, M) -Y o exp (-naDK2/M
)-(6) the eclipsed y of this equation. is the yield related to the process, and the latter term is the yield related to defects, such as work errors and/& failures of the 'jel Wi equipment. (6) Equation 11, if M=1, then (41Jy is obtained, so it becomes 2, which includes a two-dimensional LSI.
この（ｆｉ１式において、歩留Ｙ （ＫＭ）がＭに関し
極大値をもら、その時のＭ＝ＭＯが最適の素子形成Ｉｔ
４の積ＩＨ数と１１′る。７Ｅた、（６）式をＭで偏微
分する（）Ｙ／２１Ｍ・−０）と、
ＭＯ−Ｋｂ昂ラフ１７７７了−−−一−＋７１なる式か
えられる。この式でＭ、≧２とするにはＹ ＋Ｉ≧ｅｘ
ｐ （−ａ、Ｄ、に２／ ４ ） −−−−−一ζ８）
の条１！１が必要になる。In this formula (fi1), the yield Y (KM) takes a maximum value with respect to M, and then M=MO is the optimal element formation It
The product of 4 is IH number and 11'. 7E, by partially differentiating the equation (6) with respect to M ()Y/21M・-0), the equation becomes MO-KbRough1777R---1-+71. In this formula, to make M≧2, Y +I≧ex
p (-a, D, 2/4) ------1ζ8)
Article 1!1 is required.
ここにえられた（７）式のＭ。で（６）式のＭを置換し
れて計算すると、次の（９）式かえられる。M in equation (7) obtained here. When calculating by replacing M in equation (6), the following equation (9) can be obtained.
Ｙ（Ｋ） −ｅｘｐ （−２ｎａ−Ｄ−に２／ Ｍ（１
）−＋９１この式はＭＯを一定値とした場合に、歩留Ｗ
Ｋ ”）と素子数にとの関係を示す式となる。Y(K) -exp (-2na-D- to 2/M(1
)-+91 This formula shows that when MO is a constant value, the yield W
The equation shows the relationship between K'') and the number of elements.
ところで、三次元ＬＳＩを採算に合うように生産するに
は、所望の歩留Ｙｃ以上（例えば０．５以上）で製造し
なければならない。それには（９）式においてＹ≧Ｙｃ
として、次式がめられる。By the way, in order to produce a three-dimensional LSI profitably, it must be manufactured at a desired yield Yc or higher (for example, 0.5 or higher). For this, in equation (9), Y≧Yc
The following formula can be obtained.
この０１式に示されるＭＯが所望の歩留Ｙｃ以上で生産
できる積層数になり、これを素子形成層の積層数として
設計すれば採算に合った生産が可能になる。The MO shown in equation 01 is the number of laminated layers that can be produced with a desired yield Yc or more, and if this is designed as the number of laminated layers of the element forming layer, profitable production becomes possible.
一例として、この０１式に一定条件を与えて積層数Ｍｏ
と素子数にとの関係を図に示す。条件はｎ＝２０工程
ａ＝２Ｍ１０ｄ／（素子）２
ｎ＝０．０５／ｃｄ
ｙｏ＝０．９９
としたもので、実線■はＹｃ−０，５のとき、実線■は
Ｙｃ＝０．７のとき、実線■はＹｃ＝０．９のときの境
！Ｉ％！線を＞７＜ シ、これらの実線の内側の任意の
点を選ＩＪｉ！ シて素子数Ｋに対する積層数ＭＯを選
べば、所望の歩留Ｙ ｃ、以上で製造することができる
。As an example, by giving a certain condition to this formula 01, the number of laminated layers Mo
The relationship between and the number of elements is shown in the figure. The conditions are n=20 process a=2M10d/(element)2 n=0.05/cd yo=0.99, solid line ■ indicates Yc-0,5, solid line ■ indicates Yc=0.7 When , the solid line ■ is the boundary when Yc=0.9! I%! Line >7< shi, select any point inside these solid lines IJi! By selecting the number MO of stacked layers relative to the number K of elements, it is possible to manufacture with a desired yield Y c or more.
（ＩＴＩ 発明の効果
以りの説明から判るように、本発明によれば採算に合わ
−１！て製造した三次元ＬＳＩが得られるため、三次元
１．、 Ｓ Ｉの発屏に著しく役立つものである。(ITI) As can be seen from the explanation given below, the present invention allows for the production of a three-dimensional LSI that is economically produced. It is.
図は本発明により得られる所望歩留Ｙｃに対する積層数
Ｍ（、と素子数にとの関係図表の例である。
ＬｏｇにThe figure is an example of a graph showing the relationship between the desired yield Yc obtained by the present invention and the number of laminated layers M (,) and the number of elements.
Claims (1)
ｏはＭＯ≧１を満足する整数 ｎ；単層の工程数 ａ；回路密度に関する比例定数 Ｄ；平均欠陥密度 に；チップ当たりの能動素子数 ｙｏ ；平均工程歩留 Ｙｃ ；所望の歩留 １０ｇ；自然対数 からなる式で与えられる積層数ＭＯを有することを特徴
とする三次元集積回路装置。[Claims] The number of laminated active element forming layers in a three-dimensional LSI, provided that M
o is an integer n that satisfies MO≧1; number of single layer processes a; proportionality constant D related to circuit density; average defect density; number of active elements per chip yo; average process yield Yc; desired yield 10g; A three-dimensional integrated circuit device having a number of stacked layers MO given by a formula consisting of natural logarithms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16392083A JPS6054465A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16392083A JPS6054465A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6054465A true JPS6054465A (en) | 1985-03-28 |
| JPH0518258B2 JPH0518258B2 (en) | 1993-03-11 |
Family
ID=15783332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16392083A Granted JPS6054465A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054465A (en) |
-
1983
- 1983-09-05 JP JP16392083A patent/JPS6054465A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0518258B2 (en) | 1993-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008535239A5 (en) | ||
| JP2002299457A (en) | Method for wiring semiconductor integrated circuit and structure thereof | |
| US6205570B1 (en) | Method for designing LSI circuit pattern | |
| US6305004B1 (en) | Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing | |
| CN106407496A (en) | Methods of designing a layout of a semiconductor device and methods of manufacturing a semiconductor device using the same | |
| JP3917683B2 (en) | Semiconductor integrated circuit device | |
| US20080074929A1 (en) | Application specific semiconductor integrated circuit and its manufacturing method thereof | |
| JP2002110801A (en) | Wiring resistance compensation method | |
| US9231046B2 (en) | Capacitor using barrier layer metallurgy | |
| JPS6054465A (en) | Three-dimensional integrated circuit device | |
| Raghavan et al. | Artificial Intelligence (AI) based methodology to minimize asymmetric bare substrate warpage | |
| JP3247600B2 (en) | Pattern generation method | |
| CN106716626A (en) | Devices and methods to reduce stress in an electronic device | |
| KR100676606B1 (en) | Method for forming dummy pattern for cmp process | |
| JP3117686B2 (en) | LSI circuit pattern design method | |
| US10593631B2 (en) | Warping reduction in silicon wafers | |
| CN103116663B (en) | Fill method and the redundancy metal fill pattern look-up table method for building up of redundancy metal | |
| US7763968B2 (en) | Semiconductor device featuring large reinforcing elements in pad area | |
| JPH06138643A (en) | Glass mask for semiconductor device and its production | |
| JP2001230322A (en) | Semiconductor integrated-circuit device and semiconductor integrated-circuit wiring apparatus | |
| CN105140217B (en) | A kind of preparation method of three-dimensional integrated device | |
| CN105097768A (en) | Capacitor structure and manufacturing method thereof | |
| Raman et al. | Utilizing Thermo-Mechanical CPI Simulation to Define a 7nm Package Envelope | |
| CN112349679B (en) | Connection network of integrated circuit, chip and electronic equipment | |
| US8492267B1 (en) | Pillar interconnect chip to package and global wiring structure |