JPS6053872A - Timepiece apparatus with timer - Google Patents

Abstract

PURPOSE:To enable the good coupling of timer function and alarm function, by inhibiting the timing operation of a timer apparatus in such a state that alarm informing operation due to an alarm switch is imposssible. CONSTITUTION:When an alarm switch 26 is opened to bring about an alarm operation possible state, a signal A is brought to a low level to close AND gates 24, 28 and an alarm stop state is obtained to establish an alarm informing operation impossible state. At the same time, the gate of an inhibiting circuit 48 is closed by the low level signal A to cut off a drive pulse supplied to the motor 36 of an analogue timer apparatus 6 and the timing operation of the apparatus 6 is inhibited. On the other hand, when the switch 26 is closed to form an alarm informing operation possible state, the inhibition of the apparatus 46 due to the apparatus 48 is released and the generation of melody sound is performed by a melody signal generating apparatus 50 through the apparatus 6. Therefore, timer function and alarm function are coupled well and a quiet sleep can be gotten in bedtime and the possible state of alarm sound information can be confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer-equipped clock device that combines an alarm device and a timer device to provide a new timer function in addition to the normal alarm and timer functions.

BACKGROUND ART Conventionally, timer-equipped clock devices have been devised that combine a clock device and a timer device, and have the advantage of being able to utilize two functions with one clock device.

First, in a clock device, an analog clock is used that appropriately decelerates the rotation of a motor driven based on a reference signal, displays the time, and outputs an alarm start signal from a reference contact at a set time to perform an alarm notification operation. A digital clock that converts signals measured by a counter sequentially based on a device or reference signal into numerical values, displays the time, and outputs an alarm start signal from an alarm coincidence detection circuit at a set time to perform an alarm notification operation. There is a device.

Similarly, in a timer device, when the timer set display board is rotated in the cent direction, the motor driven based on the reference signal starts full operation, and the rotation of the motor is appropriately decelerated and the timer set display board is displayed. The timer time is set in the timer counter by an analog timer device that rotates in the non-setting direction and outputs a timer end signal from the timer contact after the set time elapses, or a timer center switch, and the timer time is counted by operating the start switch. 11. There is a digital timer device that starts IC operation and outputs a timer end signal from a timer coincidence detection circuit after a tenth period of time has elapsed.

The conventional timer+1 clock device is a combination of a clock device and a timer device. According to this device, the clock device can be used as an alarm clock; Boiling time, cooking time, etc. can be measured.

The present invention makes it possible to implement a new timer function by controlling the timer device in the conventional timer-equipped timer device according to the set conditions of the alarm function of the timer device.

A characteristic configuration of the present invention is that, in a timepiece having a timer device and a timer device, the alarm notification operation of the timepiece device can be operated to switch between an operable state and an inoperable state, and a ringing switch is inoperable. The reason is that the timer device's operation at the time of tears is prohibited during state manipulation.

The present invention will be described in detail below based on preferred embodiments.

FIG. 1 is an external view of an embodiment in which the present invention is applied to a timer clock device in which an analog clock device and an analog timer device are combined, and FIG. 2 is a circuit block diagram thereof.

The timer clock device 2 is composed of an analog clock device 4 and an analog timer device 6.

In the analog clock device 4, a highly accurate reference signal from a reference signal generator 8 using crystal oscillation or the like is divided by a desired frequency in a frequency dividing circuit 10, and a 2 Hz pulse is alternately generated by a waveform shaping circuit 12. It is supplied to inverters 4a and 14b. As a result, the motor 6 is driven every second, and the rotation of the motor 6 is appropriately decelerated by the wheel train 18 of the clock to display the time on the hour, minute, and second display side. The reference contact 22 is used to output an alarm start signal at the alarm time set by the user, and is based on the cam displacement of the reference cam mechanism consisting of the hour hand wheel and the reference wheel of the clock train 18, for example. The contact plate is controlled to close, and at the alarm time, a signal of ``HJ'' is output to the output H which is supplied to the AND gate 24. The signal of ``H-1'' output to this output H is the alarm start signal. The AND gate 24 is also supplied with the output A of the noise stop switch 26, and the output (■) is also supplied to the AND gate 28.The AND gate 28 is supplied with the frequency dividing circuit 1.
constant periodic signals φ1 (e.g. 2Hz) and φ2(
For example, 1.024 T(z) is supplied at the same time, and when the alarm start signal is output with the alarm switch 26 in the closed state, an audible alarm signal is output to the output J. Therefore, the driver 30 is driven and the speaker 3
2, an alarm sound will be sounded. When the ring stop switch 26 is closed, the alarm notification operation is enabled, and when it is opened, it is disabled.

On the other hand, the analog timer device 6 performs a timekeeping operation by supplying pulses from the waveform shaping circuit 12 to the inverters 34a and 34b, and drives the motor 36 every second when supplied. The rotation of the motor 36 is appropriately decelerated by the timer train 38, causing the timer display plate 40 to rotate. The timing operation is performed using the output B of the timer contact 42 and the output A of the alarm switch 26.
controlled by That is, the above outputs A and B +d
It is supplied to AND gates 44 and 46. At the same time, the AND gates 44 and 46 are supplied with pulses from the waveform shaping circuit]2, and the outputs are sent to the inverters 34a and 34b.
supply to. Therefore, the pulse from the waveform shaping circuit 12 is supplied to the inverters 34a5 and 34b at the output A.
This clockwise operation is performed only when and B are "ra". The AND gates 44 and 46 constitute a prohibition circuit 48, and the timekeeping operation is prohibited when the ring stop switch 26 is in the open state.

Further, the thermal timing operation is not performed even when the output B is "L", and this is when the timer display board 40 is in a non-cent state (FIG. 3(d)).

The timer contact 42 will be explained below using FIGS. 3 and 4.

The rotatable timer display plate 4 has a shaft 42a supported in a shaft hole 6 formed in the exterior (not shown).
frt on the back side of 0, contactable electric wires Jf42b, 42c, 4 corresponding to J'1 points B', C', D' and E'.
2d and 42e are printed. Here, when the timer display board 40 is in the state (D), that is, in the non-set state, the timer display board 40 is in the state (E).
As shown in , 19 points B'il: Non-conducting and output B
tI'ir L J, therefore, the ringing switch 2
Even if 6 is in the closed state, no timekeeping operation is performed. When this timer display board 40 is rotated in the cent direction as shown in (A) (the timer set time is set to 55 minutes in the figure)
, (f), the contact B' becomes conductive and the output B becomes [H-1, causing a ringing sound. d) If the switch 26 is in the closed state, a timing operation is performed. The total operation is performed by rotating the timer display board 40 in the operating direction, and this continues until the state (d) and (e) are reached again.

In this embodiment, as a non-preferred embodiment of the new timer function described in -1-, a melody signal is generated, which is characterized in that a melody sound is generated during 1... while the analog timer device 6 is performing a timekeeping operation. Melody signal generator 5 for generating
To explain 0, the output A of the ringing switch 26
And when the output B of the timer contact 42 becomes rHj, the output F of the Nantes gate 52 to which the outputs A and B are supplied becomes "L".
” and releases the reset state of the address counter 54. Therefore, the constant period signal φ from the frequency dividing circuit]0 is supplied to the clock terminal φ of the address counter 54. starts counting the addresses, and the melody ROM 56
The encoded signals within are read out sequentially. This encoded signal is subjected to processing such as decoding and interpolation in the DA converter 58, and is converted into an analog melody signal, which is output as an output G. The melody signal output to the output G is supplied to the driver 60, and a melody sound is generated from the speaker 62.

Furthermore, this embodiment is characterized in that the volume of the melody is lowered based on the timekeeping operation, and the voltage control device 6 lowers the total voltage supplied to the driver 60 based on the timekeeping operation.
4 is provided.

The power output is provided by P-MOS transistors (hereinafter referred to as transistors) 66, fi8, and 70. Resistor 72°74.7
The voltage is supplied to the driver 60 through a voltage control device 64, which is a parallel circuit consisting of circuits 6 and 78.

According to this, if all of the transistors 66, 68 and 70 are on, the combined resistance of the parallel circuit is low, and therefore a relatively high voltage is supplied to the driver 60, but if any of the transistors 66, 68 and 70 Each time the driver 60 is turned off, the combined resistance increases and the voltage supplied to the driver 60 decreases. As a result, the amplification degree of the driver 60 is lowered in four steps, and the volume of the melody sound is also lowered in four steps. The gates of transistors 66, 68 and 70 receive the output 0.0 from timer contact 42. D and E are each supplied,
The output C! , D, and E become H-1, transistors 66, 68, and 70 are turned off, respectively.
The distribution power is 0. The reason why D and E become "H" is that contacts c', T1' and E' are in a conductive state in FIG. 4, and contact C' is conductive when the timer remaining time is 40 minutes or less and contact D ' is conductive when the remaining time of the timer is 20 minutes or less, contact E
' is set to be conductive by the electrodes 42c, 42d and 4.2e so that the remaining time of the timer 9- is 10 minutes or less.

The characteristic operation of this embodiment will be explained below using FIGS. 3 and 4.

In the initial state shown in FIG. 3, the ring stop switch 26 is in the open state, the timer display board 40 is in the non-set state (d), and the outputs A and B are "L", so the output F is "rH". Therefore, the melody signal generator 50 does not operate. Manually rotate the timer display board 40 in the setting direction (a)
When the state is set, the timer contact 42 becomes in the state (to), and the output B becomes "H". However, in this state, since the ring stop switch 26 is in the open state, the clocking operation is hardly performed by the lock 11-circuit 48. When the noise stop switch 26 is closed, the output A becomes "HJ", the function of the inhibit circuit 48 is canceled, and the pulses from the waveform shaping circuit #+12 are sequentially supplied to the inverters 34a and 34b.As a result, the motor 36 is sequentially The timer display board 40 is rotated in the operating direction.
Due to the f closed state, the output becomes "L", and as described above, the operation of the melody signal generator 50 is started and a melody signal is output to the output G. At this time, the timer contact 42 is
Since the outputs C, D, and E are all "L-1," the driver 60 is supplied with the highest priority, and the melody volume is output at level 4.Then, the timer remaining time is 40 minutes. When the time has been counted up to (b), the timer display board 40
, the timer contact 42 is in the state (1.), and the output C is "
H”. Therefore, transistor 66 is turned off, and the volume of the melody is reduced to level 3. Similarly, when the remaining time on the timer reaches 20 minutes, the timer display will display 40 digits C)
, the timer contact 42 is in the state (H), and the output is also "H".
”. Therefore, transistor 68 is also turned off, and the volume of the melody is reduced to level 2. Further, when the remaining time of the timer reaches 10 minutes (not shown), the output m also becomes ruJ, the transistor 70 is also turned off, and the volume of the melody decreases to level 1. Then, when the timer display board 40 becomes (d) and the timer contact 42 becomes (e) again, the output B becomes "L" and the timing operation is stopped, and the output F
Since the signal becomes "H", the operation of the melody signal generator 50 is also stopped. Below, the noise stop switch 26 is in the closed state (d
l It is also possible to repeat the same operation as the one described above by rotating the timer display board 40 in the cent direction. The thermal timer set time is up to 6 in this example.
It can be freely set up to 0 minutes. When the alarm time arrives, an alarm start signal is output and the output H becomes ru.
Since the sound stop switch 26 is in the closed state, the sound output also becomes "H". As a result, an alarm signal is output to the output J, and alarm notification is performed. Of course, if the ring stop switch 26 is opened, the alarm notification can be completely stopped, and the system returns to the initial state.

According to the above embodiment, if the above-mentioned operation is performed just before going to sleep, the melody will be sounded for the desired time, and in addition to the effect of confirming that the alarm notification operation is enabled, the melody will be sounded. Does the user feel sleepy? It is also possible to induce the user to sleep comfortably and wake up comfortably with a single device. Furthermore, when the ringing switch 26 is closed to cancel the ringing condition, the melody is announced, and it is also possible to confirm that the ringing ringing has been canceled.

Note that in this embodiment, the melody is broadcast only during the period when the analog timer device 6 is performing the clocking operation, but during the same period, it is also possible to control the power on/off of other electrical equipment (radio, television, etc.). A similar effect can be obtained even if a device is provided.

Next, a case will be described in which a timer-equipped timer device that achieves the same effects as the above embodiment is obtained by combining a digital timer device and a digital timer device.

FIG. 5 shows its appearance, and FIG. 6 shows the entire circuit block diagram.

Clock device with timer 80 kl: Consists of a digital clock device 82 and a digital timer device 84.

In the digital clock device 82, a highly accurate reference signal from a reference signal generator 86 is frequency-divided to a desired frequency by a frequency dividing circuit 88, and is supplied to a 13-second counter 90 which outputs a minute pulse every 60 seconds. The minute pulse of the second counter 9o is used to measure time by a minute counter that outputs an hour pulse every 60 minutes. The time signal is then supplied to the display 98 via the decoder/driver 96 to enable time display. - The number output circuit 100 is for outputting the full alarm start signal at the alarm time set in the alarm setting circuit 102 by the user, and includes the count values of the minute counter 92 and the hour counter 94 and the set value of the alarm setting circuit 102. When the contents match, an "H" signal is output to the output S supplied to the AND gate 104. The "H" signal output to this output S is an alarm start signal. And gate 104 has a ring stop switch 10
The output a of 6 is also supplied, and the output t is sent to the AND gate l.
Supply to O8.

The constant period signals φ and φ2 from the frequency dividing circuit 88 are simultaneously supplied to the AND gate 108, and when the alarm start signal 14- is output with the stop switch 106 in the closed state, the output becomes 1]. Outputs an alarm signal that is an audible signal. This alarm signal is a game. When the hot buzzer switch 106 is in the closed state (ON operation), it is in an alarm-1 state where the notification operation is possible, and on the other hand, when it is in the open state (OWF operation), it is in the inoperable state.

On the other hand, by operating the 10 minute set switch 114 and the 1 minute 7 minute switch 116 of the digital timer device 84, the counters 118 and 120 are set at the timer time and all minute pulses from the second counter 90 are counted backwards, thereby performing a timekeeping operation. This autopsy operation is controlled by the output 0 of the or game 1-122 which outputs the timer end signal and the output a of the alarm switch 06. i.e., the outputs a and o i;i are supplied to the AND gate 124 . At the same time, the antigame 1-1, 24 is supplied with the minute pulse from the second counter 90, and the output is supplied to the clock terminal φ of the counter 18 via the orgame 1-1.26. Furthermore, the output j from which the carry signal of the counter 118 is output is also supplied to the clock terminal φ of the counter 120 via the AND gate] 28 and the OR gate 130, and the output n from which the carry signal of the counter 120 is output is connected to the OR gate together with the output port. 1122. With the above configuration, the time measurement operation is performed only when the outputs a and 0 are "H". The prohibition circuit 132 is completely configured by the AND gate 124, and the ringing stop switch 106
Timing operation is prohibited when is open. Further, the thermal timing operation is not performed even when the output 0 is "L", which means that the count values of the counters 118 and 120 are both "O".

When the 10-minute set switch 114 is operated, a single pulse is output to the output C of the one-shot circuit 134, and is supplied to the OR gate 130 and the AND gate 136.

Therefore, the counter 120 counts single pulses and sets a timer time of ]00 minutes. Here, the counters 118 and 120 are switched to up counters when the ring stop switch 106 is open, and are switched to down counters when it is closed. On the other hand, the AND gate 136 is connected to the frequency dividing circuit 88
A constant periodic signal φ2 from 1 is also supplied, and the output d is supplied to the OR gate 11.0. Therefore, each time the 10-minute set switch 1.14 is operated, an operation confirmation sound at pulse intervals outputted from the one-shot circuit 134 is notified. Similarly, when the 1-minute set switches 11 and 6 are operated, a single pulse is output to the output f of the one-shot circuit 138,
It is supplied to ORG-1 126 and AND gate 140. Therefore, the counter] 18 counts single pulses and sets a timer time on the order of one minute. On the other hand, the AND gate 140 receives the fixed period signal φ from the frequency dividing circuit 88.
3 (for example, 2048H2) and supplies the output g to the OR gate 110. Therefore, 1 minute set switch 11
Each time 6 is operated, an operation confirmation sound at pulse intervals output from the one-shot circuit 138 is sounded and is notified at a different frequency from the above-mentioned operation confirmation sound.

Outputs a and 0 are supplied to the Nantes gate 5217- in the melody signal generator 50, and as in the previous embodiment,
Only when the outputs a and 0 are rnJ, a melody signal is supplied to the driver 60 and the melody is announced from the speaker 62.

Furthermore, a voltage control device 64 similar to the previous embodiment is provided, and the output of the timer contact 42 is 0. Instead of D and E, the outputs p, q and r of the decoder 142 are connected to the transistor 66.6.
8 and 70 "3" to "0", output p to "H", r
It is configured so that the output q is set to "H" when lJ is "0", and the output r is set to rnJ when it is "0". The one-shot circuit 144 supplies a single pulse to the carry convex of the counter 20 when the stop switch 106 is closed.

The characteristic operation of this embodiment will be explained below using FIG. 7.8.

Figure 7 shows the opening set operation when the timer is used.
Normally, the ring stop switch 106 is kept in an open state to prohibit the timekeeping operation, and a counter 1818- and a 1.20 f up counter are set.

First Jtll J & counter] 18 and 120
]・If the value is “0”, the outputs j and n
is [TJ j, so the output O is also "L".

For example, if you operate the 10 minute semester I switch] 14, as mentioned above, you will receive an operation confirmation notification and the counter 120 will display 1.
Up counting is performed. Therefore, the output n is “I(”
As a result, the output O also becomes "H". When the switch 116 is operated, as mentioned above, an operation confirmation notification with a different frequency from the above sounds and the counter 11
A 1-up count at 8 is performed. Therefore, the output J is also "H1 eclipses. Hereafter, while listening to the notification sound of 21 fi ←, set the desired timer time 7) i. When the timer time is 7 nodes, the carry signal of counter 18 is output by AND gate 128. Supply to counter 120 is prohibited.

Figure 8 (d) shows the operation when the ring stop switch 106 is closed after setting the timer time to 55 minutes. becomes "L", and as mentioned above, the melody signal is output to the output G, and the counters 118 and 120
is switched to a down counter. At this point, the output is o,
Both p and q are TJ J, so the melody sound is announced at level 4.
8 becomes open, and the outputs k and l become "H". Therefore, normally the counter 120 would down-count, but in this embodiment, the one-shot circuit 14
By supplying the single-pulse carry from 4 to the human power convexity, the above-mentioned down count is avoided. Hereinafter, since the AND gate [24] is in an open state, minute pulses are sequentially output bK, and the counter 118 is counted down by one. Counter 118 when timer time is set
Since the count value of ``is 5-1'', when the pulse for the 6th look is supplied, the count value becomes ``0'' and a carry signal is output, and in synchronization with output j, output k and ``are also rLJ.
becomes. Then, by the next minute pulse, the output j becomes FT-T
J, and in synchronization with this, the outputs k and 1 become "H" and the counter 120 counts down by one. At this time, the count value of the counter 120 is "4". The counter 120 is counted down by 1 every time 10 J2J lower pulses are supplied. When the count value of the counter 120 becomes "3", the 111 force p of the decoder 142 becomes "■
)”. As a result, transistor 66 is turned off,
The melody sound is lowered to level 3. When the counter value of the counter] 20 becomes "1", the transistor 68 is turned off, and when the count value becomes "0", the transistor 70 is turned off, and the melody tone decreases from level 2 to level 1, respectively.

Then, after the count value of counter 120 becomes "0", the count value of counters 1 to 8 becomes "0", a timer end signal is output, output 0 becomes "TJ", and output F becomes "H". becomes. As a result, the output of the melody signal to the output G is stopped, and the notification of the melody sound is stopped. Further, the AND gate 124 is closed, the minute pulse is no longer output to the output terminal, and the timekeeping operation is also stopped. In this state, the desired timer time can be set by operating the 1-0 minute switch 21-chi 114 and the 1-minute set switch 116 again, and the time measurement operation is performed in the same manner as described above. When the alarm setting time arrives, an alarm signal is output to the outputs U and V to notify an alarm sound, and the alarm notification can be stopped by opening the sound stop switch 106.

In this way, in this embodiment, even when the digital clock device 82 and the digital timer device 84 are combined, the same effect as that when the analog clock device 4 and the analog timer device 6 are combined can be obtained. Furthermore, since the timer time setting can be confirmed by sound, it can be easily set even in the dark.

FIG. 9 shows another embodiment of the above-mentioned new timer function, and the same members as in the above-mentioned embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted.

The output B of the timer contact 42 built into the analog timer device 6 is supplied to the inverter 146, and the output of the inverter 146 is supplied to the AND gate 148 together with the output A of the start switch 26. The outputs of -1-1 and 48 are supplied to a single pulse circuit 150 which outputs a single pulse as an output M. A single pulse is output to the output M when the chime stop switch 26 is in the closed state and the timer display board 40 is in the non-set state shown in FIG. 3(d). This output M is a frequency dividing circuit] Constant surrounding signal φ from 0
2 is supplied to the AND gate 1 152, and a notification signal indicating that the timer display board 40 is in a non-set state is output to the output N of the AND gate 152. This output N is supplied to the driver 60.

The operation will be explained below based on FIG.

It is also possible to use it as a normal timer function, and it is sufficient to set the timer time to 10 times with the switch 26 closed. As a result, the crying operation is performed, and after the timer time has elapsed, a timer end signal is output, and the output B becomes "L", and a single pulse is output to the output M. As a result, a notification signal is output to the output N, and a notification sound is output from the speaker 62.

The following is a characteristic operation of this embodiment, in which a desired timer time can be set in advance. That is, when the ring stop switch 26 is in the open state, the timekeeping operation is prohibited by the prohibition circuit 48, and even if the timer time is set and the output B4zrnj of the timer contact 42 is output, the timekeeping operation is not performed. Therefore, when the 11-1 switch 26 is turned to the closed state, the prohibition of the operation at the time of tears by the prohibition circuit 48 is canceled and a total of 9 operations are started. Then, after the timer time has elapsed, a notification sound is issued from the speaker 62 as described above. Stop ringing switch 2 during timekeeping operation
Once 6 is opened, the prohibition circuit 48 prohibits the timekeeping operation, and when it is closed again, the prohibition is canceled and the timekeeping operation continues. Since the ringing stop switch 26 is kept in the closed state, an alarm sound is output from the speaker 32. Therefore, according to the characteristic operation of this embodiment, it is possible to set the alarm time as the final target time, and then set the intermediate time as the timer time.1.2 types of times can be set. It can be managed by the switch 26. For example, when working late at night, it is troublesome to manage break times, etc., and it is often impossible to carry out scheduled activities, but according to this embodiment, the above-mentioned problem can be solved. If you set the alarm time at 11:00 when you have to wake up the next morning, and set the break time, for example, 11:11 when you take a nap, as the timer time, all you have to do is close the ringing switch 26 when it's time to take a full nap. That's fine. As a result, after the timer period has elapsed, a notification sound is generated and the user can wake up from the nap. When you wake up, you can immediately continue your work without having to think about when to wake up the next morning.Furthermore, when you finish work, you don't have to think about when to wake up the next morning. You can do this by getting some sleep. In other words, in this example, the time to take a nap and the time to wake up the next morning can be managed simply by operating the ring stop switch 26. However, in the present embodiment 25-, since the timekeeping operation can be prohibited once, it is also possible to manage the total rest time.

Further, in this embodiment, when the timer display board 40 is in the non-set state, the output B is "L", and the output K is "r I-T", when the ring stop switch 26 is closed, the notification sound is still notified. Ru. Therefore, this notification sound makes it possible to recognize that the timer time has not been set, and also confirms that in the other usage example 17, the ring stop switch 26 is in the closed state to be in the operable state.

Although this embodiment has been described using an example in which the analog clock device 4 and the analog timer device 6 are combined, it is also possible to implement the example by combining the digital clock device 82 and the digital timer device 84, and the timer end signal A device for controlling power on/off of other electrical equipment may be provided.

As described above, the present invention makes it possible to implement a new and very convenient timer function by controlling the timer device in a conventional timer-equipped clock device according to the set conditions of the alarm function of the clock device. It is something.

[Brief explanation of drawings]

FIG. 1 is an external view of a timer device 1 that combines an analog clock device 4 and an analog timer device 4 according to the present invention. FIG. 2 is a circuit block diagram showing the overall configuration of FIG. 1. FIG. 3 is a time chart showing operation 2 of FIG. 1.2. FIG. 4 is a diagram showing the configuration and operation of the timer contact 42. FIG. 5 is an external view of a timer-equipped clock device in which a digital clock device 82 and a digital timer device 84 are combined according to the present invention. FIG. 6 is a circuit block diagram without showing the overall configuration 2 of FIG. 5. 7 and 8 are time charts showing the operation of FIG. 5. FIG. 9 is a circuit block diagram showing another embodiment of FIG. 1. 27- FIG. 10 is a time chart showing the operation of FIG. 9. 4. Analog clock device, 6. Analog data 17 units, ffq. 2・106 ・Ring 1”-me switch, 48・132
...Prohibited IL circuit, 50... Melody signal generating device, 64... Voltage control device. Applicants for the above patents: Rhythm Jigoku Kogyo Co., Ltd. 28- JP-A Sho GO-53872 (10) JP-A [IHGO-53872 (14)]

Claims (1)

[Claims] (1) Output an alarm start signal at the alarm set time,
In a watch that has an alarm device that performs an alarm notification operation in response to the alarm start signal, and a timer device that starts a time measurement operation in response to the operation start operation and outputs a timer end signal after 10 minutes has elapsed, the entire alarm notification operation is performed. A ringing switch that can be operated to switch between an enabled state and an inoperable state, and a prohibition circuit that prohibits the timing operation of the timer device when the ringing switch is operated in an inoperable state. A clock device with a timer, which is characterized by: