JPS6053054A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6053054A JPS6053054A JP16051783A JP16051783A JPS6053054A JP S6053054 A JPS6053054 A JP S6053054A JP 16051783 A JP16051783 A JP 16051783A JP 16051783 A JP16051783 A JP 16051783A JP S6053054 A JPS6053054 A JP S6053054A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- pattern
- glass
- package
- sealing glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体装置の信頼性向上、特にガラス封止型
パッケージからなる半導体装置の信頼性向上に適用して
有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to improving the reliability of semiconductor devices, particularly to improving the reliability of semiconductor devices made of glass-sealed packages.
［背景技術］
封止材としてガラスを用いるセラミック等からなる気密
封止型パッケージは、比較的安価であり、そのパンケー
ジの優れた気密性ゆえに画性能才導体装置用パンケージ
として広（利用されている（工業６周査会１９８０年発
行のｒｌｃ化実装技術１１３８ページ）。[Background Art] A hermetically sealed package made of ceramic or the like that uses glass as a sealing material is relatively inexpensive, and because of its excellent airtightness, it has been widely used as a pancase for image quality conductor devices. (RLC Implementation Technology, page 1138, published by the Industrial Sixth Survey Committee in 1980).
ところが、ガラス自体は極めて脆い性質であるため、上
記パ・７ケージの封止部は衝撃強度が非當に小さいとい
う欠点を有している。However, since glass itself is extremely brittle, the sealing portion of the package has a disadvantage in that the impact strength is extremely low.
そこで、封止部の衝撃強度を向上させるために、パッケ
ージ封止部の接着面積を大きくし、接着月であるガラス
との接触面積を拡大せしめて、該」７、ｊ止部の強度を
上げることが考えられる。Therefore, in order to improve the impact strength of the sealing part, the adhesive area of the package sealing part is increased, and the contact area with the glass, which is the bonding area, is expanded to increase the strength of the sealing part. It is possible that
しかし、単にガラスとの接触面積を拡げただのでは、パ
ッケージを加熱封着する際に、キャビティ内の空気等の
ガス状物質がパッケージ外に逃げにくくなるため、ガス
が封着後のガラス内に気泡として残り、その気泡が原因
でパッケージの気密性が害されたり、接着強度が低下す
るとし−う問題′、；生しることが本発明者によって明
らかにされた。However, simply increasing the contact area with the glass makes it difficult for gaseous substances such as air inside the cavity to escape outside the package when the package is heat-sealed. The inventors have discovered that the air bubbles remain and the airtightness of the package is impaired and the adhesive strength is reduced due to the air bubbles.
［発明の目的］
本発明の目的は、ガラス封止型パッケージからなる半導
体装置において、該パッケージの加熱封着の際に、封止
ガラス内に気泡が残る場合であっても、パッケージの気
密性を害することを防上し、゛１′−導体装置の信頼性
を向上させることにある。[Object of the Invention] An object of the present invention is to improve the airtightness of the package in a semiconductor device made of a glass-sealed package, even if air bubbles remain in the sealing glass during heat-sealing of the package. The object of the present invention is to prevent damage to the 1'-conductor device and improve the reliability of the conductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうり代表的なものの概要
を而１ｊに説明すれば、次の通りである。[Summary of the Invention] A typical outline of the invention disclosed in this application is as follows.
ずなわら、ガラス封止型パッケージの」：４止を、キャ
ビティ側に形成した第１の封止ガラスｉｌ（分と、その
外周に空隙部を隔てて形成した連続した第２の封止ガラ
ス部分で行うように構成することにより、第１の１・（
止ガラス部分には主に接着強度を、第２のＪ’４１＋１
ガラス部分には気６・）性をもノこ−Ｕ、もって半導体
装置の信頼性を向上するものである。In a glass-sealed package, a first sealing glass plate is formed on the cavity side, and a continuous second sealing glass plate is formed on the outer periphery of the first sealing glass plate with a gap between them. By configuring it to be performed in parts, the first 1.(
The adhesive strength is mainly applied to the glass stopper part, and the second J'41+1
The glass portion also has air resistance, which improves the reliability of the semiconductor device.
［実施例１コ
第１図（ａｌば、本発明の一実施例であるビングリソド
パソケージからなる半導体装置の概略断面図、第１図（
ｂｌは、本実施例１である半導体装置のパッケージに適
用するキャップであって、その裏面に封止用ガラスを印
刷した加熱封着前のガラスパターンを示す図で、第１図
（Ｃ１は、この封止ガラスを印刷したパノケージキャ、
プの概略断面図である。Embodiment 1 FIG.
bl is a cap applied to the semiconductor device package of Example 1, and is a diagram showing a glass pattern before heat sealing with sealing glass printed on the back side; A pano cage printed with this sealing glass,
FIG.
本実施例１である半導体装置は、セラミックからなるパ
ッケージの基板１とキャップ２とを有し、該キャンプ２
は封止ガラスである第２の封止ガラス部分としての帯状
パターン３および第１の封止ガラスとしての内側パター
ン４を介して気密封止されたキャビティ５を有している
。キャビティ５内においては、基板１の上にペレソｉ・
６が取り（＝Ｊけられ、該ペレット６の電極バンドと導
電層７とはワイヤ８でボンディングして電気的に接続さ
れ、さらに該導電層７は基板１の内部を通して該基板１
の裏面に取り付けられた外部電極であるピン９と電気的
に接続されてなるものである。The semiconductor device according to the first embodiment has a package substrate 1 and a cap 2 made of ceramic.
has a cavity 5 hermetically sealed via a strip pattern 3 as a second sealing glass portion and an inner pattern 4 as a first sealing glass. Inside the cavity 5, a pereso i.
6 is removed (=J is removed, the electrode band of the pellet 6 and the conductive layer 7 are electrically connected by bonding with a wire 8, and the conductive layer 7 is passed through the inside of the substrate 1
It is electrically connected to a pin 9, which is an external electrode attached to the back surface of the.
第１図（ｂｌおよび（Ｃ）は本実施例１である半導体装
置に適用する簡のパンケージキャ・ノブの裏面の状態を
示すものであるが、本実施例１である半導体装置は、パ
ッケージ封止部における封止ガラスのパターン形状にそ
の特徴がある。FIGS. 1 (bl and C) show the state of the back side of the simple package cap applied to the semiconductor device of this embodiment 1. Its characteristic lies in the pattern shape of the sealing glass in the sealing part.
すなわち、第１図（ａｌに示すように、キーｔ”；／プ
２の封止ガラスのパターン形状は、バツケージ封止面の
最外周部に所定ｒｐの帯状パターン：３を設り、その内
側に所定ｌ〕の空隙部１０を１％でて広い中に封着した
状態の内側パターン４を形成してなり、ごれらの多重パ
ターン３と４により、強大な接着強度で強固に気密封止
されたバツケージを提供するものである。In other words, as shown in FIG. The inner pattern 4 is formed by forming a sealed inner pattern 4 with a gap 10 of a predetermined length of 1% in a wide area, and the multiple patterns 3 and 4 form a strong airtight seal with strong adhesive strength. It provides a bag cage that is stopped.
ごこて、第２の封止ガラス部分である外周側の・１１！
−状パターン３の役割は、加熱封着ＩＬ’ｌに空隙部ｌ
Ｏに達した内部ガスを効率よ＜（１（状パターン３の内
部または接着部を通って抜の出るようにし、内部ガスが
抜は出た後の帯状パターン３は表面張力により自己修復
し、最終的に完全に気密な状５６で封止を完成するもの
である。すなわち、気密封止は第２の封止ガラス部分で
保証される。したがって、第２の封止ガラス部分は破断
なく連続した一つのパターンとして最外周部に形成され
る。このため、帯状パターン３の巾は、封着温度、その
温度におけるガラスの表面張力、粘度および」−１止ガ
ラスの厚さ等に応じて完全な気密封止を可能とするよう
最適寸法とされる。11 on the outer circumferential side of the iron, which is the second sealing glass part!
The role of the −-shaped pattern 3 is to attach the void l to the heat-sealed IL'l.
The internal gas that has reached O is efficiently discharged through the inside of the shaped pattern 3 or through the adhesive part, and after the internal gas has been discharged, the strip pattern 3 repairs itself due to surface tension. Finally, the sealing is completed in a completely airtight state 56. That is, the hermetic sealing is guaranteed in the second sealing glass part. Therefore, the second sealing glass part is continuous without breaking. Therefore, the width of the strip pattern 3 is completely determined depending on the sealing temperature, the surface tension and viscosity of the glass at that temperature, and the thickness of the glass. The dimensions are optimized to enable airtight sealing.
また、第１の封止ガラス部分である内側パターン４の役
割は気密性よりも接着強度の向上にある。Further, the role of the inner pattern 4, which is the first sealing glass portion, is to improve adhesive strength rather than airtightness.
したがって、多少の気泡が封止ガラス内に残存すること
は許されるので、本実施例１のように広い中で一面にガ
ラスを封着することができる。その結果、基板１とキャ
ップ２とを強大な接着力で封止することができるのであ
る。なお、第１の」、１止ガラス部分は、このように連
続した一つのパターンである必要はない。Therefore, since some bubbles are allowed to remain in the sealing glass, the glass can be sealed all over a wide area as in the first embodiment. As a result, the substrate 1 and the cap 2 can be sealed with strong adhesive force. Note that the first one-stop glass portion does not need to be one continuous pattern like this.
なお、上記半導体装置の製法は、第１図（ｂｌにその裏
面形状を、第１図ｆｃ）にその断面形状を示ずＪ−うに
、加熱封着前に予め印刷等の方法でキャップ２の裏面に
所定のパターンと厚さで封止ガラスを被着し、ごの封止
カラスを加ｆ・（）溶用：させろことにより、ベレノ（
−６およびワイート８のボンディング後の基板１をキャ
ップ２で気密封止するものである。すなわち、キャップ
２の裏面に所定の形状で１＝１止ガラスのパターンを形
成する他は全て通常の製法を用いて所期の半導体装置を
得ることができるものである。The manufacturing method for the semiconductor device described above is such that the back surface shape is shown in BL and the cross-sectional shape is shown in FIG. By applying sealing glass to the back side in a predetermined pattern and thickness, and adding the sealing glass of
The substrate 1 after bonding of -6 and Wight 8 is hermetically sealed with a cap 2. That is, the desired semiconductor device can be obtained by using all normal manufacturing methods except for forming a 1=1 stop glass pattern in a predetermined shape on the back surface of the cap 2.
［実施例２］
」二記半導体装置において、そのパッケージ封止部のガ
ラスパターンについて第１図ｆｂｌに示す第１の封止ガ
ラス部分としての内側パターンに第２図に示すようにキ
ャビティ５と空隙部１０とを連通ずる放射状空隙部１１
を形成してもよい。この場合、空隙部１１を通してキャ
ビティ４のガスが容易に空隙部ｌＯに到達できるため、
内側パターン１２に気泡か残ることがなく、気泡残存を
未然に防止できることから接着性の向上と同時に接着強
度の画一化が可能となる。[Example 2] In the semiconductor device described in Section 2, regarding the glass pattern of the package sealing part, a cavity 5 and an air gap are formed in the inner pattern as the first sealing glass part shown in FIG. A radial gap portion 11 communicating with the portion 10
may be formed. In this case, the gas in the cavity 4 can easily reach the cavity lO through the cavity 11,
Since no air bubbles remain in the inner pattern 12 and the air bubbles can be prevented from remaining, it is possible to improve the adhesiveness and at the same time to standardize the adhesive strength.
［実施例３コ
本実施薊３は上記実施例１である半導体装置に適用する
パッケージキャップ２の裏面に形成する封止ガラスのパ
ターンに関するもので、該キャップ裏面に第３図に示す
ような、所定ｒｌＪの第２の封止ガラス部分としての帯
状パターン３の内側に、第１の封止ガラス部分として同
様の帯状ガラスパターン４ａ、４ｂおよび４ｃを多重の
内側パターン４に形成したものである。すなわち、帯状
パターン３の内側に帯状パターン４ａを所定中の空隙部
１０を隔てて形成し、さらにその内側に帯状ガラスパタ
ーン４ｂ、４Ｃをそれぞれ空隙部１０ａおよび１０ｂを
隔てて形成した四重パターンの封止ガラス構造からなる
ものである。[Embodiment 3] This embodiment 3 relates to the pattern of the sealing glass formed on the back surface of the package cap 2 applied to the semiconductor device of the above-mentioned embodiment 1, and the back surface of the cap has a pattern as shown in FIG. On the inside of the strip pattern 3 as the second sealing glass portion having a predetermined rlJ, similar strip glass patterns 4a, 4b and 4c as the first sealing glass portion are formed as a multiple inner pattern 4. That is, a quadruple pattern in which a strip pattern 4a is formed inside the strip pattern 3 with a predetermined gap 10 in between, and strip glass patterns 4b and 4C are formed inside the strip pattern 3 with gaps 10a and 10b in between, respectively. It consists of a sealed glass structure.
第３図に示す封止ガラスパターンを有するキャップでパ
ンケージを加熱融着にて封止した場合は、最外周部の帯
状パターン３の他にも連続した一つのパターンである封
止ガラス４ａ、４ｂまたは４Ｃのいずれか１つが気密性
を保つことば容易であり、残りの２つに気泡が残存し気
密性を欠いていたとしても、該封止ガラスパターンを有
する半導体装置の信頼性の向上を達成できるものである
。When the pan cage is sealed by heat fusion with a cap having the sealing glass pattern shown in FIG. Or, even if any one of the 4Cs maintains airtightness, and the remaining two contain bubbles and lack airtightness, the reliability of the semiconductor device having the sealed glass pattern can be improved. It is possible.
［効果］
（１）、ガラス封止型パッケージの封止面におりる封止
ガラスの形状を内側パターンの外周部に所定ｒｌＪの空
隙部を隔てて連続した所定中の・１１Ｖ状に形成するこ
とにより、封止面積の広いパッケージであっても十分に
気密性が保持できるため、該パッケージからなる半導体
装置の信頼性をＩｉ東にさ−Ｕるごとができる。[Effects] (1) The shape of the sealing glass that falls on the sealing surface of the glass-sealed package is formed into a continuous predetermined medium 11V shape on the outer periphery of the inner pattern with a gap of a predetermined rlJ in between. As a result, even if the package has a large sealing area, sufficient airtightness can be maintained, so that the reliability of the semiconductor device made of the package can be greatly improved.
（２）、上記ｆｉ＋に記載した封止ガラスのうり内側パ
ターンを全面に封着する形状にすることに、ｌ゛す、該
パッケージの封止強度を増大できるため、該パッケージ
からなる半導体装置の信頼（’Ｉを向上さＵｏることか
できる。(2) By forming the inside pattern of the sealing glass described in fi+ above into a shape that seals the entire surface, the sealing strength of the package can be increased. Confidence ('I can be improved).
（３１に記（２）に記載した内側パターンにおいて、そ
の一部にキャビティと外周側の連続・：１１状パターン
の内側に形成した所定中の空隙部とが連ｉｊ’［！ し
ている空隙部を形成することにより、内側パターンによ
るパッケージの封止強度を一定に制御できイ）ため、半
導体装置の信頼性の画一化が可ｆｉヒとなる。(In the inner pattern described in (2) in Section 31, the cavity and the continuous outer peripheral side/: A void in a predetermined hollow formed inside the 11-shaped pattern are connected to each other in a part thereof.) By forming the inner pattern, it is possible to control the sealing strength of the package by the inner pattern to a constant level, thereby making it possible to standardize the reliability of semiconductor devices.
（４）、上記（１）に記載した封止ガラスのうち内側パ
ターンをさらに所定巾の空隙を隔てた周囲に連続し、か
つ、複数の所定中の帯状に形成することにより多重の気
密封止の作用で、パッケージの完全な気密封止が達成で
きる。(4) Multiple hermetic sealing is achieved by forming the inner pattern of the sealing glass described in (1) above into a plurality of predetermined strips that are continuous around a gap of a predetermined width. Through this action, complete hermetic sealing of the package can be achieved.
（５）、上記（１１および（２）により、気密性が高く
、かつ接着強度の大きなパッケージとすることができる
ので、該パッケージからなる半導体装置を極めて信頼性
の高いものとすることができる。(5) With the above (11 and (2)), a package with high airtightness and high adhesive strength can be obtained, so that a semiconductor device made of the package can be made extremely reliable.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、第２図に示ず封止ガラスの内側パターンにお
ける放射状空隙部として示したものは、必ずしも放射状
である必要はなく、また複μの空隙部として示しである
が目的達成のためには一本であっても十分であるし、さ
らに実施例よりも多数本からなるものであってもよい。For example, the radial voids in the inner pattern of the sealing glass not shown in FIG. A book may suffice, or it may consist of a larger number of books than in the embodiment.
また、第３図に示す帯状パターンの本数はこれにｉ限る
ものでなく、外周部帯状パターン以外に少なくとも他に
一本の帯状パターンが形成されているものであればよく
、また、第３図に示す本数を超えるものであってもよい
。Further, the number of strip patterns shown in FIG. 3 is not limited to i, but may be any number as long as at least one strip pattern is formed in addition to the outer peripheral strip pattern. The number may exceed the number shown in .
なお、上記実施例においては、１１止カラスをパッケー
ジのキャンプ裏面に印刷した場合について説明したが、
これに限るものでなく、基板のｔ＝Ｊ止面に印刷等で被
着してもよいごとはいうまでｔ）ない。In addition, in the above example, the case where the 11-stop crow was printed on the back side of the package was explained.
It goes without saying that the present invention is not limited to this, and that it may be applied to the t=J top surface of the substrate by printing or the like.
［利用分野］
以上の説明では主として本発明者によっζなされた発明
をその背景となった利用分野であるビングリノＩ−パッ
ケージからなる半導体装置であって、パッケージの封止
面積が大きいものに適用した場合について説明したが、
それに限定されるものではなく、たとえば、他のセラミ
ック等からなるガラス封止型バ、ケージからなる半導体
装置であれば広く適用でき、特に封止面積の大きなパッ
ケージからなるものに適用して極めて有効な発明である
。[Field of Application] In the above explanation, the invention made by the present inventor will mainly be applied to the field of application which is the background thereof, which is a semiconductor device consisting of a Binglino I-package, which has a large sealing area. I explained the case where
It is not limited to this, but can be widely applied to semiconductor devices made of glass-sealed packages or cages made of other ceramics, etc., and is particularly effective when applied to devices made of packages with a large sealing area. This is a great invention.
第１図（ａｌは、本発明の実施例１である半導体装置の
概略断面図、
第１図（ｂｌは、第１図（ａｌの半導体装置に適用する
前の封止ガラスを印刷したパッケージキャップの裏面図
、
第１図（Ｃ）は、第１図（ｂ）のパッケージキャップの
断面図、
第２図は本発明の実施例２である半導体装置のキャップ
の裏面図、
第３図は本発明の実施例３である半導体装置のキャップ
の裏面図である。
−１・・・基板、２・・・キャップ、３・・・帯状パタ
ーン、４・・・内側パターン、４ａ、４ｂ。
４Ｃ・・・帯状パターン、５・・−キャビティ、６・・
・ペレット、７・・・導電層、８ ・・ワイヤ、９・
・ ・ビン、１．０．１０ａ、１０ｂ、］１・・・空隙
部、■２・・・内側パターン。
代理人 弁理士 高 橋 明 夫
（ｃｙ−）第
第 ２ 図
１図
（層
σ
第 ３ 図
１０７０洗１０Ｌｐ
）／／
第１頁の続き
０発 明 者 白 井 優 之 小平市上水本町１４５
幡地発スンタ内
０発 明 者 本 多 厚 小平市上水木町１４５幡地
発スンタ内
株式会社日立製作所デバイス開
株式会社日立製作所デバイス開FIG. 1 (al is a schematic cross-sectional view of a semiconductor device according to Example 1 of the present invention, FIG. 1 (bl is a package cap printed with sealing glass before being applied to the semiconductor device in FIG. 1 (al) 1(C) is a sectional view of the package cap of FIG. 1(b), FIG. 2 is a back view of the cap of the semiconductor device according to Embodiment 2 of the present invention, and FIG. 3 is a sectional view of the package cap of FIG. 1(b). It is a back view of the cap of the semiconductor device which is Example 3 of the invention. -1...Substrate, 2...Cap, 3...Strip pattern, 4...Inner pattern, 4a, 4b. 4C.・・Strip pattern, 5...-cavity, 6...
- Pellet, 7... Conductive layer, 8... Wire, 9...
・・Bin, 1.0.10a, 10b, ]1...Gap, ■2...Inner pattern. Agent Patent Attorney Akio Takahashi (cy-) No. 2 Fig. 1 (Layer σ No. 3 Fig. 1070 wash 10 Lp) // Continued from page 1 0 Inventor Yuyuki Shirai 145 Josui Honmachi, Kodaira City
From Hatachi to Suntaai 0 Inventor Atsushi Honta 145 Kamimizuki-cho, Kodaira City Hatachi to Suntaai Hitachi Device Development Co., Ltd. Hitachi Device Development Co., Ltd.
Claims (1)
て、バ、ケージ封止面におけるガラスのパターン形状が
内側パターンの外周部に所定中の空隙部を隔てて連続し
た所定ｌ〕の帯状パターンで構成されていることを特徴
とする半導体装置。 ２、内側パターンが、帯状パターンの内側に形成された
空隙部とキャビティとを連通ずる空隙部を有しているこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
。 ３、内側パターンが、所定中の帯状空隙部を隔てて、所
定中の多重帯状パターンを形成してなることを特徴とす
る特許請求の範囲第１項記載の半導体装置。[Claims] 1. In a semiconductor device consisting of a glass-sealed package, the glass pattern shape on the cage sealing surface has a predetermined shape that is continuous to the outer periphery of the inner pattern with a predetermined gap in between.] A semiconductor device comprising a band-like pattern. 2. The semiconductor device according to claim 1, wherein the inner pattern has a cavity that communicates with the cavity formed inside the strip pattern. 3. The semiconductor device according to claim 1, wherein the inner pattern is formed by forming a predetermined multiple band-like pattern with predetermined band-like voids separated therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16051783A JPS6053054A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16051783A JPS6053054A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6053054A true JPS6053054A (en) | 1985-03-26 |
Family
ID=15716665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16051783A Pending JPS6053054A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6053054A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0279044U (en) * | 1988-12-06 | 1990-06-18 | ||
| JPH0423326U (en) * | 1990-06-18 | 1992-02-26 | ||
| JP2006247833A (en) * | 2005-03-07 | 2006-09-21 | Samsung Electronics Co Ltd | Mems element package and its manufacturing method |
| WO2007061059A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| WO2007061062A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Method for manufacturing wafer level package structure |
| WO2007061056A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| WO2007061047A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Wafer level package structure and method for manufacturing same |
| JP2009049203A (en) * | 2007-08-20 | 2009-03-05 | Nippon Carbide Ind Co Inc | Ceramic package and method of manufacturing the same |
| JP2012009969A (en) * | 2010-06-23 | 2012-01-12 | Nippon Dempa Kogyo Co Ltd | Piezoelectric device and method of manufacturing the same |
| JP5204891B2 (en) * | 2009-02-25 | 2013-06-05 | セイコーインスツル株式会社 | Package, package manufacturing method, and piezoelectric vibrator manufacturing method |
-
1983
- 1983-09-02 JP JP16051783A patent/JPS6053054A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0279044U (en) * | 1988-12-06 | 1990-06-18 | ||
| JPH0423326U (en) * | 1990-06-18 | 1992-02-26 | ||
| US7719742B2 (en) | 2005-03-07 | 2010-05-18 | Samsung Electronics Co., Ltd. | MEMS device package and method of manufacturing the same |
| JP2006247833A (en) * | 2005-03-07 | 2006-09-21 | Samsung Electronics Co Ltd | Mems element package and its manufacturing method |
| US8067769B2 (en) | 2005-11-25 | 2011-11-29 | Panasonic Electric Works Co., Ltd. | Wafer level package structure, and sensor device obtained from the same package structure |
| WO2007061056A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| WO2007061047A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Wafer level package structure and method for manufacturing same |
| WO2007061054A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Wafer level package structure and sensor device obtained from such package structure |
| US7674638B2 (en) | 2005-11-25 | 2010-03-09 | Panasonic Electric Works Co., Ltd. | Sensor device and production method therefor |
| WO2007061062A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Method for manufacturing wafer level package structure |
| US8026594B2 (en) | 2005-11-25 | 2011-09-27 | Panasonic Electric Works Co., Ltd. | Sensor device and production method therefor |
| WO2007061059A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| US8080869B2 (en) | 2005-11-25 | 2011-12-20 | Panasonic Electric Works Co., Ltd. | Wafer level package structure and production method therefor |
| JP2009049203A (en) * | 2007-08-20 | 2009-03-05 | Nippon Carbide Ind Co Inc | Ceramic package and method of manufacturing the same |
| JP5204891B2 (en) * | 2009-02-25 | 2013-06-05 | セイコーインスツル株式会社 | Package, package manufacturing method, and piezoelectric vibrator manufacturing method |
| JP2012009969A (en) * | 2010-06-23 | 2012-01-12 | Nippon Dempa Kogyo Co Ltd | Piezoelectric device and method of manufacturing the same |
| US8729775B2 (en) | 2010-06-23 | 2014-05-20 | Nihon Dempa Kogyo Co., Ltd. | Piezoelectric vibrating devices and methods for manufacturing same |
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