JPS6052584B2 - How to solder Ag lead wires - Google Patents

How to solder Ag lead wires

Info

Publication number
JPS6052584B2
JPS6052584B2 JP53057644A JP5764478A JPS6052584B2 JP S6052584 B2 JPS6052584 B2 JP S6052584B2 JP 53057644 A JP53057644 A JP 53057644A JP 5764478 A JP5764478 A JP 5764478A JP S6052584 B2 JPS6052584 B2 JP S6052584B2
Authority
JP
Japan
Prior art keywords
solder
lead wire
layer
solder layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53057644A
Other languages
Japanese (ja)
Other versions
JPS54149578A (en
Inventor
義夫 野中
詮 菊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53057644A priority Critical patent/JPS6052584B2/en
Publication of JPS54149578A publication Critical patent/JPS54149578A/en
Publication of JPS6052584B2 publication Critical patent/JPS6052584B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明はＡｇリード線を半導体基体に半田付けする方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of soldering Ag leads to a semiconductor substrate.

従来、〜リード線を半導体基体に半田付けする場合、半
導体基体のＡｇリード線を取付ける面を例えばＮｉ層の
形成によつて半田に対してぬれ易くした後、Ｐｂ−Ｓｎ
系半田を用いて〜線を基体表面に半田付けしている。Conventionally, when a lead wire is soldered to a semiconductor substrate, the surface of the semiconductor substrate on which the Ag lead wire is attached is made easily wettable by solder by forming a Ni layer, for example, and then soldered with Pb-Sn.
The wires are soldered to the surface of the substrate using solder.

この場合所望の接着強度を得るために、先に本願発明者
等によつて提案（特願昭ロー３３０花号：特開昭５４−
１２５９６９号公報）された電気抵抗溶接により、Ａｇ
リード線とＰｂ−Ｓｎ系半田層とを仮接着した後、再加
熱（再ソルダー）することが望ましい。しかしながら、
この方法では第１図に示すようにＡｇｌＪ−ド線の回り
に半田が過剰に吸い寄せられ、この結果半導体装置が例
えばトランジスタの場合にはＶＢＢ（Ｓａｔ）特性が、
ダイオードの場合にはＦＶｙ＄ｆ性がそれぞれ悪くなる
欠点がある。第１図で、１は半導体基体、２はＮｉ層、
３はＰｂ−Ｓｎ系半田層、４は〜リード線、５は再ソル
ダーにより形成されるＡｇ−Ｓ丁哄晶層である。In this case, in order to obtain the desired adhesive strength, the inventors of the present application first proposed (Patent Application Showro 330 flower name: Japanese Patent Application Laid-Open No. 54-1999)
125969) by electrical resistance welding, Ag
After temporarily bonding the lead wire and the Pb-Sn solder layer, it is desirable to reheat (re-solder). however,
In this method, as shown in FIG. 1, solder is excessively attracted around the AglJ- wire, and as a result, when the semiconductor device is a transistor, for example, the VBB (Sat) characteristic becomes
In the case of diodes, there is a drawback that the FVy$f characteristics are deteriorated. In FIG. 1, 1 is a semiconductor substrate, 2 is a Ni layer,
3 is a Pb-Sn based solder layer, 4 is a lead wire, and 5 is an Ag-S solder crystal layer formed by re-soldering.

本発明の目的は、接着強度が高くかつ半田の吸い寄せの
少ない〜リード線と半導体基体との半田付け方法を提供
することにある。本発明の特徴とするところは、Ｓｎ薄
膜で被覆した〜リード線をＰｂ−Ｓｎ系半田層に仮接着
した後〜リード線近傍の半田層の溶融する温度で再ソル
ダーする点にある。An object of the present invention is to provide a method of soldering a lead wire and a semiconductor substrate, which has high adhesive strength and attracts less solder. The feature of the present invention is that the lead wire coated with the Sn thin film is temporarily bonded to the Pb--Sn solder layer and then re-soldered at a temperature at which the solder layer in the vicinity of the lead wire melts.

このようにＡｇリード線をＳｎ薄膜で被覆しておけば、
Ｐｂ−Ｓｎ系半田層と〜リード線とがＢｒ＠膜を介して
Ａｇ−Ｓｎ♯、晶を形成するため接着強度を高くでき、
かつ再ソルダーの壽βｎ薄膜の存在によりＡｇｌＪ−ド
線近傍の半田層が他より先に溶融し半田層全体を溶融す
ることなく接着が可能となり、この結果〜リード線の周
囲への半田の吸い寄せを極力低減することができるので
ある。従つて本発明によれば半田付けによるＶＢＢ（Ｓ
ａｔ）或いはＦＶＤ特性の悪化を防止することができる
。また、本発明によれば、上記の良効果の他に再ソルダ
ー温度を低減できる効果もある。本発明に使用するＰｂ
−Ｓｎ系半田としてはＰｂ９５％−Ｓｎ５％〜Ｐｂ５０
％−Ｓｎ５０％半田が好ましい。以下本発明の実施例を
第２図により説明する。If the Ag lead wire is coated with a Sn thin film in this way,
Since the Pb-Sn solder layer and the lead wire form Ag-Sn# crystal through the Br@ film, the adhesive strength can be increased.
In addition, due to the presence of the thin βn film of the re-solder, the solder layer near the AglJ- wire melts before the others, making it possible to bond without melting the entire solder layer, and as a result - the solder is attracted around the lead wire. can be reduced as much as possible. Therefore, according to the present invention, VBB (S
at) Alternatively, deterioration of FVD characteristics can be prevented. Further, according to the present invention, in addition to the above-mentioned good effects, there is also the effect of reducing the re-soldering temperature. Pb used in the present invention
-Sn-based solder: Pb95%-Sn5%~Pb50
%-Sn50% solder is preferred. Embodiments of the present invention will be described below with reference to FIG.

工程ａは、所定のＰＮ接合を形成した半導体基体１１の
リード付けすべき面にＮｉ層の如き半田に対してぬれ性
の優れた金属層１２を形成する工程である。工程をは、
金属層１２上にＰｂ−Ｓｎ系半田層１３を形成する工程
である。半田層１３を形成する方法としては、例えば半
導体基体１１を溶融した半田バス内に漬ける方法、また
半田塊或いは半田箔を金属層１２上に載置して加熱溶融
する方法などがある。工程ｃは、Ｓｎ薄膜１４で被覆し
たＡｇｌＪ−ド線１５を半田層１３に対し、前述の特願
昭関−３３０７６号に開示されている如き電気抵抗溶接
により半田層１３をわずかに溶融させて仮付する工程で
ある。工程ｄは、再ソルダー工程である。この工程は前
述したように、ＡｇｌＪード線１５近傍の半田層部分が
溶融するに十分な温度で行なわれ、これによつて、半田
の吸い寄せも殆んど生じることなくＡｇＩＪ−ド線１５
の全周面が半田で被覆される。以上の工程により、接着
強度が高くかつ半田の吸い寄せによる電気的特性劣化の
ない半田接着部を得ることができる。Step a is a step of forming a metal layer 12 having excellent solder wettability, such as a Ni layer, on the surface of the semiconductor substrate 11 on which a predetermined PN junction is formed, on which leads are to be attached. The process is
This is a step of forming a Pb-Sn based solder layer 13 on the metal layer 12. Methods for forming the solder layer 13 include, for example, a method in which the semiconductor substrate 11 is immersed in a molten solder bath, and a method in which a solder lump or solder foil is placed on the metal layer 12 and heated and melted. In step c, the AglJ-do wire 15 coated with the Sn thin film 14 is applied to the solder layer 13 by electric resistance welding as disclosed in the above-mentioned Japanese Patent Application No. 33076, to slightly melt the solder layer 13. This is a temporary attachment process. Step d is a re-soldering step. As mentioned above, this process is carried out at a temperature sufficient to melt the solder layer near the AglJ wire 15, and as a result, the solder layer near the AglJ wire 15 is hardly attracted to the AgIJ wire 15.
The entire circumferential surface of is covered with solder. Through the above steps, it is possible to obtain a solder bonded portion that has high adhesive strength and is free from deterioration of electrical characteristics due to solder attraction.

要するに本発明はＡｇｌＪード線全体にＳｎ薄膜を被覆
しておいた点に特徴があります。本発明によれば、Ａｇ
リード線近傍の半田が上記Ｓｎ薄膜の溶融によりＳｎリ
ツチとなり、低融点でもつてＡｇリード線全体がぬれま
す。一方、Ａｇリード線より少し遠ざかつている部分の
半田は比較的Ｐｂリツチ（前述の実施例の如くＰｂ量が
Ｓｎ量に比べて多いかもしくは等しい）であるために溶
融点は高く、それゆえにＡｇリード線へ吸い寄せられる
ことがない。本発明は上記実施例に限定されることなく
種々の変形が可能である。In short, the present invention is characterized in that the entire AglJ wire is coated with a Sn thin film. According to the invention, Ag
The solder near the lead wire becomes rich in Sn due to the melting of the Sn thin film mentioned above, and even at a low melting point, the entire Ag lead wire gets wet. On the other hand, the solder in the part that is a little further away from the Ag lead wire is relatively rich in Pb (the amount of Pb is greater than or equal to the amount of Sn, as in the previous example), so its melting point is high; It will not be attracted to the lead wire. The present invention is not limited to the above embodiments, and can be modified in various ways.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来法により半田接着部構造を示す概略断面図
、第２図ａ乃至ｄは本発明の一実施例による接着工程を
示す概略断面図である。 １１・・・・・・半導体基体、１３・・・・・・Ｐｂ−
Ｓｎ系半田層、１４・・・・・・Ｓｒ４膜、１５・・・
・・・Ａｇリード線。FIG. 1 is a schematic cross-sectional view showing the structure of a solder bonded part according to a conventional method, and FIGS. 2A to 2D are schematic cross-sectional views showing a bonding process according to an embodiment of the present invention. 11...Semiconductor substrate, 13...Pb-
Sn-based solder layer, 14...Sr4 film, 15...
...Ag lead wire.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基体の半田に対してぬれ易く処理された面に
ＰｂリッチまたはＰｂ、Ｓｎ量の等しいＰｂ−Ｓｎ系半
田層を形成する工程と、前記半田層表面に対し、全体が
Ｓｎ薄膜で被覆したＡｇリード線を仮接着する工程と、
Ａｇリード線近傍部分の半田を溶融する温度で前記仮接
着状態にあるＡｇリード線及び半田を加熱する工程とを
具備することを特徴とするＡｇリード線の半田付け方法
。1. A process of forming a Pb-rich solder layer or a Pb-Sn based solder layer with equal amounts of Pb and Sn on a surface of a semiconductor substrate that has been treated to be easily wetted by solder, and covering the entire surface of the solder layer with a thin Sn film. A step of temporarily bonding the Ag lead wire,
A method for soldering an Ag lead wire, comprising the step of heating the temporarily bonded Ag lead wire and solder at a temperature that melts the solder in the vicinity of the Ag lead wire.
JP53057644A 1978-05-17 1978-05-17 How to solder Ag lead wires Expired JPS6052584B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53057644A JPS6052584B2 (en) 1978-05-17 1978-05-17 How to solder Ag lead wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53057644A JPS6052584B2 (en) 1978-05-17 1978-05-17 How to solder Ag lead wires

Publications (2)

Publication Number Publication Date
JPS54149578A JPS54149578A (en) 1979-11-22
JPS6052584B2 true JPS6052584B2 (en) 1985-11-20

Family

ID=13061594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53057644A Expired JPS6052584B2 (en) 1978-05-17 1978-05-17 How to solder Ag lead wires

Country Status (1)

Country Link
JP (1) JPS6052584B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005028951B4 (en) 2005-06-22 2018-05-30 Infineon Technologies Ag Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device

Also Published As

Publication number Publication date
JPS54149578A (en) 1979-11-22

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